From patchwork Mon Jul 16 11:28:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944315 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="TMsU6+OW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41Th6N1ndWz9ryt for ; Mon, 16 Jul 2018 21:30:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E7710C2212E; Mon, 16 Jul 2018 11:29:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5A4A2C21FEC; Mon, 16 Jul 2018 11:29:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id ECBDCC21EBE; Mon, 16 Jul 2018 11:29:10 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id 6231CC21C4A for ; Mon, 16 Jul 2018 11:29:09 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id k3-v6so7375453pgq.5 for ; Mon, 16 Jul 2018 04:29:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AcnHf1dG9qypKnMf1C+nmKkm9OeTmAs88A9a2R6xZSk=; b=TMsU6+OWEB1F/qpGo4X9m1/GerjsTOCI2/SJqcivzCl44I12qJxkIKoNJ347Cb0ABk kycftWdFziAlKhhttoUp1w2SNA6k1TifnRJ4XQt/yLzTE/+nOFdmAGpkdFCtX1dL/LFj COF5BqxTrknARmbwQB6VidXLkeD4qkBV0oTg8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AcnHf1dG9qypKnMf1C+nmKkm9OeTmAs88A9a2R6xZSk=; b=iBrqEz7uDhx3REVmXhOctlP3y2td4HR1/J7EWssoZb6gCV/UlRA/jgZdJDhF3awcPa jv6aZtwiH/j7RyKVbvSFRASVeyb8PkdzMQXmU56vEL/Y3EfvsXDtBtbgo/3jRRIq6NZ3 YfqlZ9fkUyWCOQaxLtM8oqXq44eBh8+z8fq4JBV65qvT1PNTqkVR7UYJdX9lMRWfnrkU oNUpY6slSM2FExhho1tA2T30as/aXp7yBCRfgeunf9Uf2QgmV7Pguv7DxQcNCCUozLD4 5W9S9wBPDb1aqUZqgm/ah62jIf8ka5cwIyJmsQ66t4Ati3IFGqS2JvxXQPOsK0p1Gh/l H4bg== X-Gm-Message-State: AOUpUlGrP+nqvI0Xe3J+UpNl8q8VDdVXR7gLhUfYOYKlA8kpSpLSWV/S N7IRRbN7VP+piJFB/Uw4b1g7sA== X-Google-Smtp-Source: AAOMgpenqiIDq6mddUFs4GXeaFc0Cz6PCuh16jRp4tQ+ecYO9xTx7Q4Ge851CfEuqQA11opZZMA0/Q== X-Received: by 2002:a63:c252:: with SMTP id l18-v6mr15134722pgg.76.1531740547985; Mon, 16 Jul 2018 04:29:07 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:07 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:16 +0530 Message-Id: <20180716112850.3961-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 01/35] clk: Kconfig: Ascending order to sub directiory kconfigs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" sourcing of sub directiory kconfig files are not in proper order, so keep them in ascending order. Signed-off-by: Jagan Teki --- drivers/clk/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index edb4ca58ea..3e66dd97c1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -83,12 +83,12 @@ config CLK_STM32MP1 Enable the STM32 clock (RCC) driver. Enable support for manipulating STM32MP1's on-SoC clocks. -source "drivers/clk/tegra/Kconfig" -source "drivers/clk/uniphier/Kconfig" -source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" -source "drivers/clk/renesas/Kconfig" +source "drivers/clk/exynos/Kconfig" source "drivers/clk/mvebu/Kconfig" +source "drivers/clk/renesas/Kconfig" +source "drivers/clk/tegra/Kconfig" +source "drivers/clk/uniphier/Kconfig" config ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver" From patchwork Mon Jul 16 11:28:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944318 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Mon, 16 Jul 2018 04:29:10 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:10 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:17 +0530 Message-Id: <20180716112850.3961-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 02/35] net: sun8i_emac: Make proper order for include files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Make proper ordering for include files to get rid of build issues with arch/clock.h Signed-off-by: Jagan Teki --- drivers/net/sun8i_emac.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 3ba3a1ff8b..709b5e26bd 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -10,16 +10,16 @@ * */ -#include -#include -#include #include #include #include -#include #include #include #include +#include +#include +#include +#include #include #ifdef CONFIG_DM_GPIO #include From patchwork Mon Jul 16 11:28:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944314 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="qlKaGh3x"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41Th6G50m5z9ryt for ; Mon, 16 Jul 2018 21:30:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3B11FC220DA; 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Mon, 16 Jul 2018 04:29:13 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:12 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:18 +0530 Message-Id: <20180716112850.3961-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 03/35] mtd: sunxi_nand_spl: Make proper order for include files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Make proper ordering for include files to get rid of build issues with arch/clock.h Signed-off-by: Jagan Teki --- drivers/mtd/nand/sunxi_nand_spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 6cde9814c4..3406761c1d 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -4,11 +4,11 @@ * Copyright (c) 2015, AW-SOM Technologies */ -#include -#include #include #include #include +#include +#include #include /* registers */ From patchwork Mon Jul 16 11:28:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944317 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="ZuUbFpMF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41Th8G0Mx6z9s2P for ; Mon, 16 Jul 2018 21:31:57 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 45CEDC22128; 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Mon, 16 Jul 2018 04:29:15 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:15 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:19 +0530 Message-Id: <20180716112850.3961-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 04/35] dt-bindings: reset: Sync sun4i-a10-ccu.h from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sync include/dt-bindings/reset/sun4i-a10-ccu.h from Linux with below commit details: commit c84f5683f6e9fee78e054431d89121225ccb7464 Author: Priit Laes Date: Wed Aug 23 20:23:29 2017 +0300 clk: sunxi-ng: Add sun4i/sun7i CCU driver Signed-off-by: Jagan Teki --- include/dt-bindings/reset/sun4i-a10-ccu.h | 69 +++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h new file mode 100644 index 0000000000..5f4480bedc --- /dev/null +++ b/include/dt-bindings/reset/sun4i-a10-ccu.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2017 Priit Laes + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN4I_A10_H +#define _DT_BINDINGS_RST_SUN4I_A10_H + +#define RST_USB_PHY0 1 +#define RST_USB_PHY1 2 +#define RST_USB_PHY2 3 +#define RST_GPS 4 +#define RST_DE_BE0 5 +#define RST_DE_BE1 6 +#define RST_DE_FE0 7 +#define RST_DE_FE1 8 +#define RST_DE_MP 9 +#define RST_TVE0 10 +#define RST_TCON0 11 +#define RST_TVE1 12 +#define RST_TCON1 13 +#define RST_CSI0 14 +#define RST_CSI1 15 +#define RST_VE 16 +#define RST_ACE 17 +#define RST_LVDS 18 +#define RST_GPU 19 +#define RST_HDMI_H 20 +#define RST_HDMI_SYS 21 +#define RST_HDMI_AUDIO_DMA 22 + +#endif /* DT_BINDINGS_RST_SUN4I_A10_H */ From patchwork Mon Jul 16 11:28:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944319 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_SUN5I_H_ +#define _DT_BINDINGS_CLK_SUN5I_H_ + +#define CLK_HOSC 1 + +#define CLK_PLL_VIDEO0_2X 9 + +#define CLK_PLL_VIDEO1_2X 16 +#define CLK_CPU 17 + +#define CLK_AHB_OTG 23 +#define CLK_AHB_EHCI 24 +#define CLK_AHB_OHCI 25 +#define CLK_AHB_SS 26 +#define CLK_AHB_DMA 27 +#define CLK_AHB_BIST 28 +#define CLK_AHB_MMC0 29 +#define CLK_AHB_MMC1 30 +#define CLK_AHB_MMC2 31 +#define CLK_AHB_NAND 32 +#define CLK_AHB_SDRAM 33 +#define CLK_AHB_EMAC 34 +#define CLK_AHB_TS 35 +#define CLK_AHB_SPI0 36 +#define CLK_AHB_SPI1 37 +#define CLK_AHB_SPI2 38 +#define CLK_AHB_GPS 39 +#define CLK_AHB_HSTIMER 40 +#define CLK_AHB_VE 41 +#define CLK_AHB_TVE 42 +#define CLK_AHB_LCD 43 +#define CLK_AHB_CSI 44 +#define CLK_AHB_HDMI 45 +#define CLK_AHB_DE_BE 46 +#define CLK_AHB_DE_FE 47 +#define CLK_AHB_IEP 48 +#define CLK_AHB_GPU 49 +#define CLK_APB0_CODEC 50 +#define CLK_APB0_SPDIF 51 +#define CLK_APB0_I2S 52 +#define CLK_APB0_PIO 53 +#define CLK_APB0_IR 54 +#define CLK_APB0_KEYPAD 55 +#define CLK_APB1_I2C0 56 +#define CLK_APB1_I2C1 57 +#define CLK_APB1_I2C2 58 +#define CLK_APB1_UART0 59 +#define CLK_APB1_UART1 60 +#define CLK_APB1_UART2 61 +#define CLK_APB1_UART3 62 +#define CLK_NAND 63 +#define CLK_MMC0 64 +#define CLK_MMC1 65 +#define CLK_MMC2 66 +#define CLK_TS 67 +#define CLK_SS 68 +#define CLK_SPI0 69 +#define CLK_SPI1 70 +#define CLK_SPI2 71 +#define CLK_IR 72 +#define CLK_I2S 73 +#define CLK_SPDIF 74 +#define CLK_KEYPAD 75 +#define CLK_USB_OHCI 76 +#define CLK_USB_PHY0 77 +#define CLK_USB_PHY1 78 +#define CLK_GPS 79 +#define CLK_DRAM_VE 80 +#define CLK_DRAM_CSI 81 +#define CLK_DRAM_TS 82 +#define CLK_DRAM_TVE 83 +#define CLK_DRAM_DE_FE 84 +#define CLK_DRAM_DE_BE 85 +#define CLK_DRAM_ACE 86 +#define CLK_DRAM_IEP 87 +#define CLK_DE_BE 88 +#define CLK_DE_FE 89 +#define CLK_TCON_CH0 90 + +#define CLK_TCON_CH1 92 +#define CLK_CSI 93 +#define CLK_VE 94 +#define CLK_CODEC 95 +#define CLK_AVS 96 +#define CLK_HDMI 97 +#define CLK_GPU 98 + +#define CLK_IEP 100 + +#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ From patchwork Mon Jul 16 11:28:21 2018 Content-Type: text/plain; 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Mon, 16 Jul 2018 04:29:20 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:20 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:21 +0530 Message-Id: <20180716112850.3961-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 06/35] dt-bindings: reset: Sync sun5i-ccu.h from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sync include/dt-bindings/reset/sun5i-ccu.h from Linux with below commit details: commit 5e73761786d6ff7e10c371703835528dee9306e3 Author: Maxime Ripard Date: Tue Oct 4 10:09:58 2016 +0200 clk: sunxi-ng: Add sun5i CCU driver Signed-off-by: Jagan Teki --- include/dt-bindings/reset/sun5i-ccu.h | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/reset/sun5i-ccu.h diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h new file mode 100644 index 0000000000..c2b9726b50 --- /dev/null +++ b/include/dt-bindings/reset/sun5i-ccu.h @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _RST_SUN5I_H_ +#define _RST_SUN5I_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_GPS 2 +#define RST_DE_BE 3 +#define RST_DE_FE 4 +#define RST_TVE 5 +#define RST_LCD 6 +#define RST_CSI 7 +#define RST_VE 8 +#define RST_GPU 9 +#define RST_IEP 10 + +#endif /* _RST_SUN5I_H_ */ From patchwork Mon Jul 16 11:28:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944321 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; 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Mon, 16 Jul 2018 04:29:23 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:22 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:22 +0530 Message-Id: <20180716112850.3961-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 07/35] dt-bindings: clock: Sync sun6i-a31-ccu.h from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sync include/dt-bindings/clock/sun6i-a31-ccu.h from Linux with below commit details: commit 80815004a45fc68b6e34653af4fca47be7fb96ed Author: Chen-Yu Tsai Date: Fri Sep 29 16:22:53 2017 +0800 clk: sunxi-ng: sun6i: Export video PLLs Signed-off-by: Jagan Teki --- include/dt-bindings/clock/sun6i-a31-ccu.h | 191 ++++++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h new file mode 100644 index 0000000000..c5d1334018 --- /dev/null +++ b/include/dt-bindings/clock/sun6i-a31-ccu.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ +#define _DT_BINDINGS_CLK_SUN6I_A31_H_ + +#define CLK_PLL_VIDEO0_2X 7 + +#define CLK_PLL_PERIPH 10 + +#define CLK_PLL_VIDEO1_2X 13 + +#define CLK_CPU 18 + +#define CLK_AHB1_MIPIDSI 23 +#define CLK_AHB1_SS 24 +#define CLK_AHB1_DMA 25 +#define CLK_AHB1_MMC0 26 +#define CLK_AHB1_MMC1 27 +#define CLK_AHB1_MMC2 28 +#define CLK_AHB1_MMC3 29 +#define CLK_AHB1_NAND1 30 +#define CLK_AHB1_NAND0 31 +#define CLK_AHB1_SDRAM 32 +#define CLK_AHB1_EMAC 33 +#define CLK_AHB1_TS 34 +#define CLK_AHB1_HSTIMER 35 +#define CLK_AHB1_SPI0 36 +#define CLK_AHB1_SPI1 37 +#define CLK_AHB1_SPI2 38 +#define CLK_AHB1_SPI3 39 +#define CLK_AHB1_OTG 40 +#define CLK_AHB1_EHCI0 41 +#define CLK_AHB1_EHCI1 42 +#define CLK_AHB1_OHCI0 43 +#define CLK_AHB1_OHCI1 44 +#define CLK_AHB1_OHCI2 45 +#define CLK_AHB1_VE 46 +#define CLK_AHB1_LCD0 47 +#define CLK_AHB1_LCD1 48 +#define CLK_AHB1_CSI 49 +#define CLK_AHB1_HDMI 50 +#define CLK_AHB1_BE0 51 +#define CLK_AHB1_BE1 52 +#define CLK_AHB1_FE0 53 +#define CLK_AHB1_FE1 54 +#define CLK_AHB1_MP 55 +#define CLK_AHB1_GPU 56 +#define CLK_AHB1_DEU0 57 +#define CLK_AHB1_DEU1 58 +#define CLK_AHB1_DRC0 59 +#define CLK_AHB1_DRC1 60 + +#define CLK_APB1_CODEC 61 +#define CLK_APB1_SPDIF 62 +#define CLK_APB1_DIGITAL_MIC 63 +#define CLK_APB1_PIO 64 +#define CLK_APB1_DAUDIO0 65 +#define CLK_APB1_DAUDIO1 66 + +#define CLK_APB2_I2C0 67 +#define CLK_APB2_I2C1 68 +#define CLK_APB2_I2C2 69 +#define CLK_APB2_I2C3 70 +#define CLK_APB2_UART0 71 +#define CLK_APB2_UART1 72 +#define CLK_APB2_UART2 73 +#define CLK_APB2_UART3 74 +#define CLK_APB2_UART4 75 +#define CLK_APB2_UART5 76 + +#define CLK_NAND0 77 +#define CLK_NAND1 78 +#define CLK_MMC0 79 +#define CLK_MMC0_SAMPLE 80 +#define CLK_MMC0_OUTPUT 81 +#define CLK_MMC1 82 +#define CLK_MMC1_SAMPLE 83 +#define CLK_MMC1_OUTPUT 84 +#define CLK_MMC2 85 +#define CLK_MMC2_SAMPLE 86 +#define CLK_MMC2_OUTPUT 87 +#define CLK_MMC3 88 +#define CLK_MMC3_SAMPLE 89 +#define CLK_MMC3_OUTPUT 90 +#define CLK_TS 91 +#define CLK_SS 92 +#define CLK_SPI0 93 +#define CLK_SPI1 94 +#define CLK_SPI2 95 +#define CLK_SPI3 96 +#define CLK_DAUDIO0 97 +#define CLK_DAUDIO1 98 +#define CLK_SPDIF 99 +#define CLK_USB_PHY0 100 +#define CLK_USB_PHY1 101 +#define CLK_USB_PHY2 102 +#define CLK_USB_OHCI0 103 +#define CLK_USB_OHCI1 104 +#define CLK_USB_OHCI2 105 + +#define CLK_DRAM_VE 110 +#define CLK_DRAM_CSI_ISP 111 +#define CLK_DRAM_TS 112 +#define CLK_DRAM_DRC0 113 +#define CLK_DRAM_DRC1 114 +#define CLK_DRAM_DEU0 115 +#define CLK_DRAM_DEU1 116 +#define CLK_DRAM_FE0 117 +#define CLK_DRAM_FE1 118 +#define CLK_DRAM_BE0 119 +#define CLK_DRAM_BE1 120 +#define CLK_DRAM_MP 121 + +#define CLK_BE0 122 +#define CLK_BE1 123 +#define CLK_FE0 124 +#define CLK_FE1 125 +#define CLK_MP 126 +#define CLK_LCD0_CH0 127 +#define CLK_LCD1_CH0 128 +#define CLK_LCD0_CH1 129 +#define CLK_LCD1_CH1 130 +#define CLK_CSI0_SCLK 131 +#define CLK_CSI0_MCLK 132 +#define CLK_CSI1_MCLK 133 +#define CLK_VE 134 +#define CLK_CODEC 135 +#define CLK_AVS 136 +#define CLK_DIGITAL_MIC 137 +#define CLK_HDMI 138 +#define CLK_HDMI_DDC 139 +#define CLK_PS 140 + +#define CLK_MIPI_DSI 143 +#define CLK_MIPI_DSI_DPHY 144 +#define CLK_MIPI_CSI_DPHY 145 +#define CLK_IEP_DRC0 146 +#define CLK_IEP_DRC1 147 +#define CLK_IEP_DEU0 148 +#define CLK_IEP_DEU1 149 +#define CLK_GPU_CORE 150 +#define CLK_GPU_MEMORY 151 +#define CLK_GPU_HYD 152 +#define CLK_ATS 153 +#define CLK_TRACE 154 + +#define CLK_OUT_A 155 +#define CLK_OUT_B 156 +#define CLK_OUT_C 157 + +#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ From patchwork Mon Jul 16 11:28:23 2018 Content-Type: text/plain; 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Mon, 16 Jul 2018 04:29:25 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:25 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:23 +0530 Message-Id: <20180716112850.3961-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 08/35] dt-bindings: reset: Sync sun6i-a31-ccu.h from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sync include/dt-bindings/reset/sun6i-a31-ccu.h from Linux with below commit details: commit c6e6c96d8fa6f21e80e625bdf56c9ef580f43acb Author: Chen-Yu Tsai Date: Thu Aug 25 14:21:59 2016 +0800 clk: sunxi-ng: Add A31/A31s clocks Signed-off-by: Jagan Teki --- include/dt-bindings/reset/sun6i-a31-ccu.h | 106 ++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h new file mode 100644 index 0000000000..fbff365ed6 --- /dev/null +++ b/include/dt-bindings/reset/sun6i-a31-ccu.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ +#define _DT_BINDINGS_RST_SUN6I_A31_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_PHY2 2 + +#define RST_AHB1_MIPI_DSI 3 +#define RST_AHB1_SS 4 +#define RST_AHB1_DMA 5 +#define RST_AHB1_MMC0 6 +#define RST_AHB1_MMC1 7 +#define RST_AHB1_MMC2 8 +#define RST_AHB1_MMC3 9 +#define RST_AHB1_NAND1 10 +#define RST_AHB1_NAND0 11 +#define RST_AHB1_SDRAM 12 +#define RST_AHB1_EMAC 13 +#define RST_AHB1_TS 14 +#define RST_AHB1_HSTIMER 15 +#define RST_AHB1_SPI0 16 +#define RST_AHB1_SPI1 17 +#define RST_AHB1_SPI2 18 +#define RST_AHB1_SPI3 19 +#define RST_AHB1_OTG 20 +#define RST_AHB1_EHCI0 21 +#define RST_AHB1_EHCI1 22 +#define RST_AHB1_OHCI0 23 +#define RST_AHB1_OHCI1 24 +#define RST_AHB1_OHCI2 25 +#define RST_AHB1_VE 26 +#define RST_AHB1_LCD0 27 +#define RST_AHB1_LCD1 28 +#define RST_AHB1_CSI 29 +#define RST_AHB1_HDMI 30 +#define RST_AHB1_BE0 31 +#define RST_AHB1_BE1 32 +#define RST_AHB1_FE0 33 +#define RST_AHB1_FE1 34 +#define RST_AHB1_MP 35 +#define RST_AHB1_GPU 36 +#define RST_AHB1_DEU0 37 +#define RST_AHB1_DEU1 38 +#define RST_AHB1_DRC0 39 +#define RST_AHB1_DRC1 40 +#define RST_AHB1_LVDS 41 + +#define RST_APB1_CODEC 42 +#define RST_APB1_SPDIF 43 +#define RST_APB1_DIGITAL_MIC 44 +#define RST_APB1_DAUDIO0 45 +#define RST_APB1_DAUDIO1 46 +#define RST_APB2_I2C0 47 +#define RST_APB2_I2C1 48 +#define RST_APB2_I2C2 49 +#define RST_APB2_I2C3 50 +#define RST_APB2_UART0 51 +#define RST_APB2_UART1 52 +#define RST_APB2_UART2 53 +#define RST_APB2_UART3 54 +#define RST_APB2_UART4 55 +#define RST_APB2_UART5 56 + +#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ From patchwork Mon Jul 16 11:28:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944322 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="MTMTBeCy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThDZ2g9Vz9s2g for ; Mon, 16 Jul 2018 21:35:42 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C6B26C21FEC; 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Mon, 16 Jul 2018 04:29:28 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:28 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:24 +0530 Message-Id: <20180716112850.3961-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 09/35] sunxi: clk: add DM clock driver template for the A64 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Andre Przywara Create the template for a new DM clock driver for the Allwinner A64 SoC. Signed-off-by: Andre Przywara Signed-off-by: Jagan Teki --- drivers/clk/Makefile | 1 + drivers/clk/sunxi/Makefile | 7 ++++ drivers/clk/sunxi/clk_a64.c | 77 +++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/clk/sunxi/Makefile create mode 100644 drivers/clk/sunxi/clk_a64.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 426c67db9b..5944b9bbb5 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,6 +11,7 @@ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_MVEBU) += mvebu/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile new file mode 100644 index 0000000000..6cf122c634 --- /dev/null +++ b/drivers/clk/sunxi/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 Arm Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_MACH_SUN50I) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c new file mode 100644 index 0000000000..77afbcafd3 --- /dev/null +++ b/drivers/clk/sunxi/clk_a64.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2018 Arm Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a64_clk_priv { + void *base; +}; + +static ulong a64_clk_get_rate(struct clk *clk) +{ + debug("%s(#%ld)\n", __func__, clk->id); + + debug(" unhandled\n"); + return -EINVAL; +} + +static ulong a64_clk_set_rate(struct clk *clk, ulong rate) +{ + debug("%s(#%ld, rate: %lu)\n", __func__, clk->id, rate); + + debug(" unhandled\n"); + return -EINVAL; +} + +static int a64_clk_enable(struct clk *clk) +{ + debug("%s(#%ld)\n", __func__, clk->id); + + debug(" unhandled\n"); + return -EINVAL; +} + +static struct clk_ops a64_clk_ops = { + .get_rate = a64_clk_get_rate, + .set_rate = a64_clk_set_rate, + .enable = a64_clk_enable, +}; + +static int a64_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a64_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a64_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a64_clk_ids[] = { + { .compatible = "allwinner,sun50i-a64-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun50i_a64) = { + .name = "sun50i_a64_ccu", + .id = UCLASS_CLK, + .of_match = a64_clk_ids, + .priv_auto_alloc_size = sizeof(struct a64_clk_priv), + .ofdata_to_platdata = a64_clk_ofdata_to_platdata, + .ops = &a64_clk_ops, + .probe = a64_clk_probe, +}; From patchwork Mon Jul 16 11:28:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944325 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="M/pVFtgd"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThHC6F4Nz9s29 for ; Mon, 16 Jul 2018 21:37:59 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 80FAEC220C5; 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Mon, 16 Jul 2018 04:29:31 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:30 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:25 +0530 Message-Id: <20180716112850.3961-11-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 10/35] clk: sunxi: Add Kconfig entry X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add proper kconfig entries for Allwinner platform, CLK_SUN50I_A64 is kconfig option for A64 clock driver. Signed-off-by: Jagan Teki --- drivers/clk/Kconfig | 1 + drivers/clk/sunxi/Kconfig | 18 ++++++++++++++++++ drivers/clk/sunxi/Makefile | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/sunxi/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3e66dd97c1..f32a2af70f 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -87,6 +87,7 @@ source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/sunxi/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig new file mode 100644 index 0000000000..3a86c91e75 --- /dev/null +++ b/drivers/clk/sunxi/Kconfig @@ -0,0 +1,18 @@ +config CLK_SUNXI + bool "Clock support for Allwinner SoCs" + depends on ARCH_SUNXI + select CLK + help + This enables support for common clock driver API on Allwinner + SoCs. + +if CLK_SUNXI + +config CLK_SUN50I_A64 + bool "Clock driver for Allwinner A64" + default MACH_SUN50I + help + This enables common clock driver support for platforms based + on Allwinner A64 SoC. + +endif # CLK_SUNXI diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 6cf122c634..fc9da34208 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_MACH_SUN50I) += clk_a64.o +obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o From patchwork Mon Jul 16 11:28:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944333 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="YEhDmT9s"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThPS2pqCz9s29 for ; Mon, 16 Jul 2018 21:43:24 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2A92AC2206E; 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Mon, 16 Jul 2018 04:29:33 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:33 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:26 +0530 Message-Id: <20180716112850.3961-12-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 11/35] clk: sunxi: a64: Add disable function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add clock disable function for clearing register bits. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/clk_a64.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 77afbcafd3..fb9dec3173 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -41,10 +41,19 @@ static int a64_clk_enable(struct clk *clk) return -EINVAL; } +static int a64_clk_disable(struct clk *clk) +{ + debug("%s(#%ld)\n", __func__, clk->id); + + debug(" unhandled\n"); + return -EINVAL; +} + static struct clk_ops a64_clk_ops = { .get_rate = a64_clk_get_rate, .set_rate = a64_clk_set_rate, .enable = a64_clk_enable, + .disable = a64_clk_disable, }; static int a64_clk_probe(struct udevice *dev) From patchwork Mon Jul 16 11:28:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944327 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="A7pGZcMf"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThMX2CpKz9ryt for ; Mon, 16 Jul 2018 21:41:42 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 96829C22120; Mon, 16 Jul 2018 11:38:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B1D6DC2206E; Mon, 16 Jul 2018 11:30:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 73A13C22153; Mon, 16 Jul 2018 11:29:41 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id CD6E0C22104 for ; Mon, 16 Jul 2018 11:29:37 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id n7-v6so501505pgq.4 for ; Mon, 16 Jul 2018 04:29:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rdNg8P7KaObpIr87TINeA3ieko4aLcFQg+VHRkhKlNA=; b=A7pGZcMf04Id5CkbIlzMnnGugkjzYk0IH3Q6ILf7JCtyj8fimIlF2SkBVthiT0W1GB 5V72MiIIfR2ZvRAYqrT3Oh1bpKe2ewmhRj+3aJ68kzDUB1PqWV/44NZ8okczCSpGuUob qNNMiEvGG3bbB5/STTve+gkvYFh7UhdapKwXo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rdNg8P7KaObpIr87TINeA3ieko4aLcFQg+VHRkhKlNA=; b=NpBG7AHhUu+W7oWikDuVYju/nHIiuAlY1oemQ7M/xbqcv1zfj/AGbMhLCrERwOFbJC YEFgAwrAsToE8UsGfLw+qkJfbIU99rSn1EVh5YmmcrAqbZlEdVuv49VVjpbRud4hhraL t6H/Bhwz2fQ3be0Dk2nUv19957vaWoTjfYzj8pspD2Qe4N6KkaG4gh2SKpQNOPkXwvxW ieJ0zcAUpaNutX1VPnsBOZ9nwcMJTY8kIPUxLds40NEb0Hq19XrKAMcA19YdeS6jAj76 wes/QJJGtwqVYsQ/cAFKLIKACW+7c3o56zSsXd8ULI6eNzXoNfb9NDycna2/0XkY7WbQ QC3A== X-Gm-Message-State: AOUpUlHPHjm8OF0zdhhxHn7U8yO5dWKbhJ+/IrNAppnkeWhEnpSqfqy5 byQRSSLfB6nqkhuUKL5RPr92+A== X-Google-Smtp-Source: AAOMgpc1EYgO9HnC0P/99yj/wNqT+Pey9Dh8yW2xVwNj1zzchjuMKheJH/7O5zxupOU66tSKzrGVSA== X-Received: by 2002:a62:3184:: with SMTP id x126-v6mr17746702pfx.49.1531740576457; Mon, 16 Jul 2018 04:29:36 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:35 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:27 +0530 Message-Id: <20180716112850.3961-13-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 12/35] clk: sunxi: a64: Implement USB clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement USB clock enable and disble functions for OHCI, EHCI, OTG and USBPHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/clk_a64.c | 62 ++++++++++++++++++++++++++++++++++--- 1 file changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index fb9dec3173..3997432260 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -35,18 +35,72 @@ static ulong a64_clk_set_rate(struct clk *clk, ulong rate) static int a64_clk_enable(struct clk *clk) { + struct a64_clk_priv *priv = dev_get_priv(clk->dev); + debug("%s(#%ld)\n", __func__, clk->id); - debug(" unhandled\n"); - return -EINVAL; + switch (clk->id) { + case CLK_BUS_OTG: + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + setbits_le32(priv->base + 0x60, + BIT(23 + (clk->id - CLK_BUS_OTG))); + return 0; + case CLK_BUS_OHCI0: + case CLK_BUS_OHCI1: + setbits_le32(priv->base + 0x60, + BIT(28 + (clk->id - CLK_BUS_OHCI0))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + setbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + case CLK_USB_OHCI1: + setbits_le32(priv->base + 0xcc, BIT(17)); + return 0; + default: + debug(" unhandled\n"); + return -ENODEV; + } } static int a64_clk_disable(struct clk *clk) { + struct a64_clk_priv *priv = dev_get_priv(clk->dev); + debug("%s(#%ld)\n", __func__, clk->id); - debug(" unhandled\n"); - return -EINVAL; + switch (clk->id) { + case CLK_BUS_OTG: + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + clrbits_le32(priv->base + 0x60, + BIT(23 + (clk->id - CLK_BUS_OTG))); + return 0; + case CLK_BUS_OHCI0: + case CLK_BUS_OHCI1: + clrbits_le32(priv->base + 0x60, + BIT(28 + (clk->id - CLK_BUS_OHCI0))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + clrbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + case CLK_USB_OHCI1: + clrbits_le32(priv->base + 0xcc, BIT(17)); + return 0; + default: + debug(" unhandled\n"); + return -ENODEV; + } } static struct clk_ops a64_clk_ops = { From patchwork Mon Jul 16 11:28:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944346 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="XqYVPoWe"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThX54lmfz9ryt for ; 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Mon, 16 Jul 2018 04:29:39 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:38 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:28 +0530 Message-Id: <20180716112850.3961-14-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 13/35] reset: sunxi: Add DM reset driver template for the A64 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Create the template for a new DM reset driver for the Allwinner A64 SoC. Signed-off-by: Jagan Teki --- drivers/reset/Kconfig | 2 + drivers/reset/Makefile | 1 + drivers/reset/sunxi/Kconfig | 19 ++++++++++ drivers/reset/sunxi/Makefile | 7 ++++ drivers/reset/sunxi/reset_a64.c | 67 +++++++++++++++++++++++++++++++++ 5 files changed, 96 insertions(+) create mode 100644 drivers/reset/sunxi/Kconfig create mode 100644 drivers/reset/sunxi/Makefile create mode 100644 drivers/reset/sunxi/reset_a64.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 33c39b7fb6..f95b38a35f 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -98,4 +98,6 @@ config RESET_SOCFPGA help Support for reset controller on SoCFPGA platform. +source "drivers/reset/sunxi/Kconfig" + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index ad08be4c8c..7530b5368d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SUNXI) += sunxi/ diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig new file mode 100644 index 0000000000..c0dfa56071 --- /dev/null +++ b/drivers/reset/sunxi/Kconfig @@ -0,0 +1,19 @@ +config RESET_SUNXI + bool "RESET support for Allwinner SoCs" + depends on ARCH_SUNXI + depends on CLK_SUNXI + select DM_RESET + help + This enables support for common reset driver API on Allwinner + SoCs. + +if RESET_SUNXI + +config RESET_SUN50I_A64 + bool "Reset driver for Allwinner A64" + default MACH_SUN50I + help + This enables common reset driver support for platforms based + on Allwinner A64 SoC. + +endif # RESET_SUNXI diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile new file mode 100644 index 0000000000..cc80b11818 --- /dev/null +++ b/drivers/reset/sunxi/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2018 Amarula Solutions +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_a64.c b/drivers/reset/sunxi/reset_a64.c new file mode 100644 index 0000000000..595af5aa6e --- /dev/null +++ b/drivers/reset/sunxi/reset_a64.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a64_reset_priv { + void *base; +}; + +static int a64_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a64_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a64_reset_assert(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + debug(" unhandled\n"); + return -EINVAL; +} + +static int a64_reset_deassert(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + debug(" unhandled\n"); + return -EINVAL; +} + +struct reset_ops a64_reset_ops = { + .request = a64_reset_request, + .free = a64_reset_free, + .rst_assert = a64_reset_assert, + .rst_deassert = a64_reset_deassert, +}; + +static int a64_reset_probe(struct udevice *dev) +{ + return 0; +} + +U_BOOT_DRIVER(reset_sun50i_a64) = { + .name = "sun50i_a64_reset", + .id = UCLASS_RESET, + .ops = &a64_reset_ops, + .probe = a64_reset_probe, + .priv_auto_alloc_size = sizeof(struct a64_reset_priv), +}; From patchwork Mon Jul 16 11:28:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944326 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="iIBZ6H6E"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThJQ0tycz9ryt for ; Mon, 16 Jul 2018 21:39:02 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id ADAA8C21FEC; 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Mon, 16 Jul 2018 04:29:41 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:41 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:29 +0530 Message-Id: <20180716112850.3961-15-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de, Chakra Divi Subject: [U-Boot] [RFC 14/35] reset: sunxi: a64: Bind reset from clock driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Since clock and reset drivers have same DT node, we cann't follow another binding for reset so bind the reset driver from clock driver. Binding here rely on name of the uclass driver rather than matching id. So, this patch will pick the clock driver name as input and replace the sunfix ccu with reset. This logic is suggested by 'Chakra Divi' Signed-off-by: Chakra Divi Signed-off-by: Jagan Teki --- arch/arm/include/asm/arch-sunxi/clock.h | 8 +++++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a64.c | 1 + drivers/clk/sunxi/clk_sunxi.c | 39 +++++++++++++++++++++++++ 4 files changed, 49 insertions(+) create mode 100644 drivers/clk/sunxi/clk_sunxi.c diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 46c3eed377..f8c5cb3fc5 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -34,4 +34,12 @@ void clock_init_sec(void); void clock_init_uart(void); #endif +/* + * sunxi_clk_bind() - Bind reset device as child of clock device + * + * @cdev: clock udevice + * @return 0 success, or error value + */ +int sunxi_clk_bind(struct udevice *cdev); + #endif /* _SUNXI_CLOCK_H */ diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index fc9da34208..860bb6dfea 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -4,4 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 3997432260..42d5974262 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -137,4 +137,5 @@ U_BOOT_DRIVER(clk_sun50i_a64) = { .ofdata_to_platdata = a64_clk_ofdata_to_platdata, .ops = &a64_clk_ops, .probe = a64_clk_probe, + .bind = sunxi_clk_bind, }; diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c new file mode 100644 index 0000000000..ca2544b1a0 --- /dev/null +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include + +int sunxi_clk_bind(struct udevice *cdev) +{ + struct udevice *rst_dev; + char *dev_name = "reset"; + char drv_name[30]; + int ret; + + /** + * reset driver doesn't have separate dt binding, so probe them + * using driver name. + * example: sun50i_a64_ccu is clock driver, + * sun50i_a64_reset is reset driver. + */ + strcpy(drv_name, cdev->driver->name); + memcpy(&drv_name[strlen(drv_name) - 3], dev_name, strlen(dev_name)); + + ret = device_bind_driver_to_node(cdev, drv_name, dev_name, + dev_ofnode(cdev), &rst_dev); + if (ret) { + debug("Warning: failed to bind (%s) reset driver: ret=%d\n", + drv_name, ret); + return ret; + } + + return 0; +} From patchwork Mon Jul 16 11:28:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944324 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="ONId+iF/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThGV1mdcz9ryt for ; Mon, 16 Jul 2018 21:37:22 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id CB606C22104; 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Mon, 16 Jul 2018 04:29:44 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:43 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:30 +0530 Message-Id: <20180716112850.3961-16-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 15/35] reset: Add default request ops X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Missing request ops from respective uclass driver generating "synchronous abort" in Allwinner platform, may be in arm. So add default request ops and give a chance to uclass driver to think whether they really need request or not. Signed-off-by: Jagan Teki --- drivers/reset/reset-uclass.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 3899537635..99881b8b99 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -14,6 +14,11 @@ static inline struct reset_ops *reset_dev_ops(struct udevice *dev) return (struct reset_ops *)dev->driver->ops; } +static int reset_request_default(struct reset_ctl *reset_ctl) +{ + return 0; +} + static int reset_of_xlate_default(struct reset_ctl *reset_ctl, struct ofnode_phandle_args *args) { @@ -69,7 +74,10 @@ int reset_get_by_index(struct udevice *dev, int index, return ret; } - ret = ops->request(reset_ctl); + if (ops->request) + ret = ops->request(reset_ctl); + else + ret = reset_request_default(reset_ctl); if (ret) { debug("ops->request() failed: %d\n", ret); return ret; From patchwork Mon Jul 16 11:28:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944349 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Jagan Teki --- drivers/reset/sunxi/reset_a64.c | 60 +++++++++++++++++++++++++++++---- 1 file changed, 54 insertions(+), 6 deletions(-) diff --git a/drivers/reset/sunxi/reset_a64.c b/drivers/reset/sunxi/reset_a64.c index 595af5aa6e..389641c7cd 100644 --- a/drivers/reset/sunxi/reset_a64.c +++ b/drivers/reset/sunxi/reset_a64.c @@ -20,6 +20,10 @@ static int a64_reset_request(struct reset_ctl *reset_ctl) { debug("%s(#%ld)\n", __func__, reset_ctl->id); + /* check dt-bindings/reset/sun50i-a64-ccu.h for max id */ + if (reset_ctl->id > 50) + return -EINVAL; + return 0; } @@ -32,18 +36,58 @@ static int a64_reset_free(struct reset_ctl *reset_ctl) static int a64_reset_assert(struct reset_ctl *reset_ctl) { - debug("%s(#%ld)\n", __func__, reset_ctl->id); + struct a64_reset_priv *priv = dev_get_priv(reset_ctl->dev); - debug(" unhandled\n"); - return -EINVAL; + debug("%s(#%ld)\n", __func__, reset_ctl->id); + switch(reset_ctl->id) { + case RST_BUS_OTG: + case RST_BUS_EHCI0: + case RST_BUS_EHCI1: + clrbits_le32(priv->base + 0x2c0, + BIT(23 + (reset_ctl->id - RST_BUS_OTG))); + return 0; + case RST_BUS_OHCI0: + case RST_BUS_OHCI1: + clrbits_le32(priv->base + 0x2c0, + BIT(28 + (reset_ctl->id - RST_BUS_OHCI0))); + return 0; + case RST_USB_PHY0: + case RST_USB_PHY1: + clrbits_le32(priv->base + 0x0cc, + BIT(reset_ctl->id - RST_USB_PHY0)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } } static int a64_reset_deassert(struct reset_ctl *reset_ctl) { - debug("%s(#%ld)\n", __func__, reset_ctl->id); + struct a64_reset_priv *priv = dev_get_priv(reset_ctl->dev); - debug(" unhandled\n"); - return -EINVAL; + debug("%s(#%ld)\n", __func__, reset_ctl->id); + switch(reset_ctl->id) { + case RST_BUS_OTG: + case RST_BUS_EHCI0: + case RST_BUS_EHCI1: + setbits_le32(priv->base + 0x2c0, + BIT(23 + (reset_ctl->id - RST_BUS_OTG))); + return 0; + case RST_BUS_OHCI0: + case RST_BUS_OHCI1: + setbits_le32(priv->base + 0x2c0, + BIT(28 + (reset_ctl->id - RST_BUS_OHCI0))); + return 0; + case RST_USB_PHY0: + case RST_USB_PHY1: + setbits_le32(priv->base + 0x0cc, + BIT(reset_ctl->id - RST_USB_PHY0)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } } struct reset_ops a64_reset_ops = { @@ -55,6 +99,10 @@ struct reset_ops a64_reset_ops = { static int a64_reset_probe(struct udevice *dev) { + struct a64_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + return 0; } From patchwork Mon Jul 16 11:28:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944340 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; 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Mon, 16 Jul 2018 04:29:49 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:49 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:32 +0530 Message-Id: <20180716112850.3961-18-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 17/35] clk: sunxi: Add initial CLK driver for H3_H5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial clock driver Allwinner for H3_H5. Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 ++ drivers/clk/sunxi/Makefile | 2 + drivers/clk/sunxi/clk_h3.c | 131 +++++++++++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/clk/sunxi/clk_h3.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 3a86c91e75..065cadf2fe 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -8,6 +8,13 @@ config CLK_SUNXI if CLK_SUNXI +config CLK_SUN8I_H3 + bool "Clock driver for Allwinner H3/H5" + default MACH_SUNXI_H3_H5 + help + This enables common clock driver support for platforms based + on Allwinner H3/H5 SoC. + config CLK_SUN50I_A64 bool "Clock driver for Allwinner A64" default MACH_SUN50I diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 860bb6dfea..37e6bcb147 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -5,4 +5,6 @@ # obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o + +obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c new file mode 100644 index 0000000000..e924017717 --- /dev/null +++ b/drivers/clk/sunxi/clk_h3.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct h3_clk_priv { + void *base; +}; + +static int h3_clk_enable(struct clk *clk) +{ + struct h3_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + case CLK_BUS_EHCI2: + case CLK_BUS_EHCI3: + case CLK_BUS_OHCI0: + case CLK_BUS_OHCI1: + case CLK_BUS_OHCI2: + case CLK_BUS_OHCI3: + setbits_le32(priv->base + 0x60, + BIT(23 + (clk->id - CLK_BUS_OTG))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + case CLK_USB_PHY3: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + case CLK_USB_OHCI3: + setbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int h3_clk_disable(struct clk *clk) +{ + struct h3_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + case CLK_BUS_EHCI2: + case CLK_BUS_EHCI3: + case CLK_BUS_OHCI0: + case CLK_BUS_OHCI1: + case CLK_BUS_OHCI2: + case CLK_BUS_OHCI3: + clrbits_le32(priv->base + 0x60, + BIT(23 + (clk->id - CLK_BUS_OTG))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + case CLK_USB_PHY3: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + case CLK_USB_OHCI3: + clrbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops h3_clk_ops = { + .enable = h3_clk_enable, + .disable = h3_clk_disable, +}; + +static int h3_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int h3_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct h3_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id h3_clk_ids[] = { + { .compatible = "allwinner,sun8i-h3-ccu" }, + { .compatible = "allwinner,sun50i-h5-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_h3) = { + .name = "sun8i_h3_ccu", + .id = UCLASS_CLK, + .of_match = h3_clk_ids, + .priv_auto_alloc_size = sizeof(struct h3_clk_priv), + .ofdata_to_platdata = h3_clk_ofdata_to_platdata, + .ops = &h3_clk_ops, + .probe = h3_clk_probe, + .bind = sunxi_clk_bind, +}; From patchwork Mon Jul 16 11:28:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944332 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Mon, 16 Jul 2018 04:29:52 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:51 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:33 +0530 Message-Id: <20180716112850.3961-19-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 18/35] reset: sunxi: Add initial RESET driver for H3_H5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial reset driver for Allwinner H3_H5. Implement reset deassert and assert functions for USB OHCI, EHCI, OTG and PHY bus reset and clock registers. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 7 ++ drivers/reset/sunxi/Makefile | 1 + drivers/reset/sunxi/reset_h3.c | 121 +++++++++++++++++++++++++++++++++ 3 files changed, 129 insertions(+) create mode 100644 drivers/reset/sunxi/reset_h3.c diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index c0dfa56071..5c3b79eb76 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -9,6 +9,13 @@ config RESET_SUNXI if RESET_SUNXI +config RESET_SUN8I_H3 + bool "Reset driver for Allwinner H3/H5" + default MACH_SUNXI_H3_H5 + help + This enables common reset driver support for platforms based + on Allwinner H3/H5 SoC. + config RESET_SUN50I_A64 bool "Reset driver for Allwinner A64" default MACH_SUN50I diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile index cc80b11818..6e4273b344 100644 --- a/drivers/reset/sunxi/Makefile +++ b/drivers/reset/sunxi/Makefile @@ -4,4 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_h3.c b/drivers/reset/sunxi/reset_h3.c new file mode 100644 index 0000000000..e4794cadb9 --- /dev/null +++ b/drivers/reset/sunxi/reset_h3.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct h3_reset_priv { + void *base; +}; + +static int h3_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun8i-h3-ccu.h for max id */ + if (reset_ctl->id > 54) + return -EINVAL; + + return 0; +} + +static int h3_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int h3_reset_assert(struct reset_ctl *reset_ctl) +{ + struct h3_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_PHY2: + case RST_USB_PHY3: + clrbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + case RST_BUS_EHCI0: + case RST_BUS_EHCI1: + case RST_BUS_EHCI2: + case RST_BUS_EHCI3: + case RST_BUS_OHCI0: + case RST_BUS_OHCI1: + case RST_BUS_OHCI2: + case RST_BUS_OHCI3: + clrbits_le32(priv->base + 0x2c0, + BIT(23 + (reset_ctl->id - RST_BUS_OTG))); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +static int h3_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct h3_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_PHY2: + case RST_USB_PHY3: + setbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + case RST_BUS_EHCI0: + case RST_BUS_EHCI1: + case RST_BUS_EHCI2: + case RST_BUS_EHCI3: + case RST_BUS_OHCI0: + case RST_BUS_OHCI1: + case RST_BUS_OHCI2: + case RST_BUS_OHCI3: + setbits_le32(priv->base + 0x2c0, + BIT(23 + (reset_ctl->id - RST_BUS_OTG))); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +struct reset_ops h3_reset_ops = { + .request = h3_reset_request, + .free = h3_reset_free, + .rst_assert = h3_reset_assert, + .rst_deassert = h3_reset_deassert, +}; + +static int h3_reset_probe(struct udevice *dev) +{ + struct h3_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +U_BOOT_DRIVER(reset_sun8i_h3) = { + .name = "sun8i_h3_reset", + .id = UCLASS_RESET, + .ops = &h3_reset_ops, + .probe = h3_reset_probe, + .priv_auto_alloc_size = sizeof(struct h3_reset_priv), +}; From patchwork Mon Jul 16 11:28:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944342 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; 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Mon, 16 Jul 2018 04:29:54 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:54 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:34 +0530 Message-Id: <20180716112850.3961-20-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 19/35] clk: sunxi: Add initial CLK driver for A10/A20 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial clock driver Allwinner for A10/A20. Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a10.c | 105 ++++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a10.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 065cadf2fe..36acfa1b88 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -8,6 +8,13 @@ config CLK_SUNXI if CLK_SUNXI +config CLK_SUN4I_A10 + bool "Clock driver for Allwinner A10/A20" + default MACH_SUN4I || MACH_SUN7I + help + This enables common clock driver support for platforms based + on Allwinner A10/A20 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 37e6bcb147..bcf2c4269d 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o +obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c new file mode 100644 index 0000000000..1d38d9e28e --- /dev/null +++ b/drivers/clk/sunxi/clk_a10.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a10_clk_priv { + void *base; +}; + +static int a10_clk_enable(struct clk *clk) +{ + struct a10_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI0: + case CLK_AHB_OHCI0: + case CLK_AHB_EHCI1: + case CLK_AHB_OHCI1: + setbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_PHY: + setbits_le32(priv->base + 0xcc, + BIT(6 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a10_clk_disable(struct clk *clk) +{ + struct a10_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI0: + case CLK_AHB_OHCI0: + case CLK_AHB_EHCI1: + case CLK_AHB_OHCI1: + clrbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_PHY: + clrbits_le32(priv->base + 0xcc, + BIT(6 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a10_clk_ops = { + .enable = a10_clk_enable, + .disable = a10_clk_disable, +}; + +static int a10_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a10_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a10_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a10_clk_ids[] = { + { .compatible = "allwinner,sun4i-a10-ccu" }, + { .compatible = "allwinner,sun7i-a20-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun4i_a10) = { + .name = "sun4i_a10_ccu", + .id = UCLASS_CLK, + .of_match = a10_clk_ids, + .priv_auto_alloc_size = sizeof(struct a10_clk_priv), + .ofdata_to_platdata = a10_clk_ofdata_to_platdata, + .ops = &a10_clk_ops, + .probe = a10_clk_probe, + .bind = sunxi_clk_bind, +}; From patchwork Mon Jul 16 11:28:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944336 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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b=edlS/33X2bXGD9XPo9DYh1iecbEXIEOnOEPmL6zaioL4aAJT6Ps+vG7TgWccai5XTl xOHHp4D+EX2YXvG/eXqvQoV5Cu0xgJFG8makP1gtpyHxv3DrUix9A0rc+NuJead+dDK9 0AywRfp97mgFi7QbSIq8xJ+/AasKJ+yrmIelxR2dXm/ABUSPm2w2Mdx3HC9InQvBKQ7r rlCZJjhncs1pOCOLnvRjg/8OwhHQOaFB/UNX4dRvl09lnrpjkcGp3Ayn4dSLboF3jjJv 3EQtBCF4S/A8xzEAisZJwZkge/LyfGhwatGU4C8DIso6d1gnUYfUmy+6I6q/l/PQvr+j Di4Q== X-Gm-Message-State: AOUpUlG7iZJjfu6ns4Z9wFGEKW2R2jA3s3NyswWv6Y/8OdKI2KhxAnze u1dODzmpqm55xllpPcuzdGZkbw== X-Google-Smtp-Source: AAOMgpdu8x3f1nNaWZKJodFRodgGitfBJQDbBOEspXSZ3piYINlDOsMkL5UyjRBdgvJuITk5xv/9Ww== X-Received: by 2002:a17:902:9b98:: with SMTP id y24-v6mr16096969plp.177.1531740597197; Mon, 16 Jul 2018 04:29:57 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:56 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:35 +0530 Message-Id: <20180716112850.3961-21-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 20/35] reset: sunxi: Add initial RESET driver for A10/A20 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial reset driver for Allwinner A10/A20. Implement reset deassert and assert functions for USB OHCI, EHCI, OTG and PHY bus reset and clock registers. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 7 +++ drivers/reset/sunxi/Makefile | 1 + drivers/reset/sunxi/reset_a10.c | 95 +++++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 drivers/reset/sunxi/reset_a10.c diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index 5c3b79eb76..523201a4e9 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -9,6 +9,13 @@ config RESET_SUNXI if RESET_SUNXI +config RESET_SUN4I_A10 + bool "Reset driver for Allwinner A10/A20" + default MACH_SUN4I || MACH_SUN7I + help + This enables common reset driver support for platforms based + on Allwinner A10/A20 SoC. + config RESET_SUN8I_H3 bool "Reset driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile index 6e4273b344..6dc0520b6a 100644 --- a/drivers/reset/sunxi/Makefile +++ b/drivers/reset/sunxi/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_RESET_SUN4I_A10) += reset_a10.o obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_a10.c b/drivers/reset/sunxi/reset_a10.c new file mode 100644 index 0000000000..d964ea42e8 --- /dev/null +++ b/drivers/reset/sunxi/reset_a10.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a10_reset_priv { + void *base; +}; + +static int a10_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun4i-a10-ccu.h for max id */ + if (reset_ctl->id > 22) + return -EINVAL; + + return 0; +} + +static int a10_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a10_reset_assert(struct reset_ctl *reset_ctl) +{ + struct a10_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_PHY2: + clrbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +static int a10_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct a10_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_PHY2: + setbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +struct reset_ops a10_reset_ops = { + .request = a10_reset_request, + .free = a10_reset_free, + .rst_assert = a10_reset_assert, + .rst_deassert = a10_reset_deassert, +}; + +static int a10_reset_probe(struct udevice *dev) +{ + struct a10_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +U_BOOT_DRIVER(reset_sun4i_a10) = { + .name = "sun4i_a10_reset", + .id = UCLASS_RESET, + .ops = &a10_reset_ops, + .probe = a10_reset_probe, + .priv_auto_alloc_size = sizeof(struct a10_reset_priv), +}; From patchwork Mon Jul 16 11:28:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944353 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a10s.c | 105 +++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a10s.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 36acfa1b88..6801b845cf 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -15,6 +15,13 @@ config CLK_SUN4I_A10 This enables common clock driver support for platforms based on Allwinner A10/A20 SoC. +config CLK_SUN5I_A10S + bool "Clock driver for Allwinner A10s/A13" + default MACH_SUN5I + help + This enables common clock driver support for platforms based + on Allwinner A10s/A13 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index bcf2c4269d..e217335a9b 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o +obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c new file mode 100644 index 0000000000..b5fc61c038 --- /dev/null +++ b/drivers/clk/sunxi/clk_a10s.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a10s_clk_priv { + void *base; +}; + +static int a10s_clk_enable(struct clk *clk) +{ + struct a10s_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI: + case CLK_AHB_OHCI: + setbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI: + setbits_le32(priv->base + 0xcc, BIT(6)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a10s_clk_disable(struct clk *clk) +{ + struct a10s_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI: + case CLK_AHB_OHCI: + clrbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI: + clrbits_le32(priv->base + 0xcc, BIT(6)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a10s_clk_ops = { + .enable = a10s_clk_enable, + .disable = a10s_clk_disable, +}; + +static int a10s_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a10s_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a10s_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a10s_clk_ids[] = { + { .compatible = "allwinner,sun5i-a10s-ccu" }, + { .compatible = "allwinner,sun5i-a13-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun5i_a10s) = { + .name = "sun5i_a10s_ccu", + .id = UCLASS_CLK, + .of_match = a10s_clk_ids, + .priv_auto_alloc_size = sizeof(struct a10s_clk_priv), + .ofdata_to_platdata = a10s_clk_ofdata_to_platdata, + .ops = &a10s_clk_ops, + .probe = a10s_clk_probe, + .bind = sunxi_clk_bind, +}; From patchwork Mon Jul 16 11:28:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944344 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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b=MZDh6vZikyhKk3a3Lmo0rOR/+IeVBvUFc6kFhdyHmfyLoMY5IKaKKAjAIrUeaO9dJL tocyePoOj9TcY8jHX2IcAMYh3CiIS8S8RjrEEwlKRy3MnbgXzxRTfSR4jgUDR8MRk3lm ds6Pr7PCetXqQttni9FiEYsc9jKy8buvt1YB/GQ74x1W9RIUT6T7bewxTu3qcpq6+WRS VDkbqNqV05p3WRNprd+3vV9cmYoUtTf9MEtRIqVZlYsi6qp6BiZnEg9nHtm5/MJBociB nl5tOqxO8d2TG4VRiYO1XFgqhSCr+49nZFViIkzbiBpT7c6SQOW68D5CK5YOB2lz+NM4 UOIQ== X-Gm-Message-State: AOUpUlGw03RNJgCjCJgQgkjtFFLRUtaVzwy+jyGlu1wpW/xPBo0hhKkX jbh6hQ7rK3Uw+cucdzCzEzt1xA== X-Google-Smtp-Source: AAOMgpcWZpcezDYJub/pXAz6UGtjNVE97qssdFMkpSJOe/mHQ1OjK7csDzjGd0RKwFLUgjYKfueykA== X-Received: by 2002:a62:ec41:: with SMTP id k62-v6mr17521145pfh.206.1531740602281; Mon, 16 Jul 2018 04:30:02 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:01 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:37 +0530 Message-Id: <20180716112850.3961-23-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 22/35] reset: sunxi: Add initial RESET driver for A10s/A13 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial reset driver for Allwinner A10s/A13. Implement reset deassert and assert functions for USB OHCI, EHCI, OTG and PHY bus reset and clock registers. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 7 +++ drivers/reset/sunxi/Makefile | 1 + drivers/reset/sunxi/reset_a10s.c | 93 ++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 drivers/reset/sunxi/reset_a10s.c diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index 523201a4e9..40f4f4d0e6 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -16,6 +16,13 @@ config RESET_SUN4I_A10 This enables common reset driver support for platforms based on Allwinner A10/A20 SoC. +config RESET_SUN5I_A10S + bool "Reset driver for Allwinner A10s/A13" + default MACH_SUN5I + help + This enables common reset driver support for platforms based + on Allwinner A10s/A13 SoC. + config RESET_SUN8I_H3 bool "Reset driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile index 6dc0520b6a..38b8907904 100644 --- a/drivers/reset/sunxi/Makefile +++ b/drivers/reset/sunxi/Makefile @@ -5,5 +5,6 @@ # obj-$(CONFIG_RESET_SUN4I_A10) += reset_a10.o +obj-$(CONFIG_RESET_SUN5I_A10S) += reset_a10s.o obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_a10s.c b/drivers/reset/sunxi/reset_a10s.c new file mode 100644 index 0000000000..fb65633836 --- /dev/null +++ b/drivers/reset/sunxi/reset_a10s.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a10s_reset_priv { + void *base; +}; + +static int a10s_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun5i-a10s-ccu.h for max id */ + if (reset_ctl->id > 10) + return -EINVAL; + + return 0; +} + +static int a10s_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a10s_reset_assert(struct reset_ctl *reset_ctl) +{ + struct a10s_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + setbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +static int a10s_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct a10s_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + clrbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +struct reset_ops a10s_reset_ops = { + .request = a10s_reset_request, + .free = a10s_reset_free, + .rst_assert = a10s_reset_assert, + .rst_deassert = a10s_reset_deassert, +}; + +static int a10s_reset_probe(struct udevice *dev) +{ + struct a10s_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +U_BOOT_DRIVER(reset_sun5i_a10s) = { + .name = "sun5i_a10s_reset", + .id = UCLASS_RESET, + .ops = &a10s_reset_ops, + .probe = a10s_reset_probe, + .priv_auto_alloc_size = sizeof(struct a10s_reset_priv), +}; From patchwork Mon Jul 16 11:28:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944341 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 ++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a31.c | 130 ++++++++++++++++++++++++++++++++++++ 3 files changed, 138 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a31.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 6801b845cf..1f44fed2b9 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -22,6 +22,13 @@ config CLK_SUN5I_A10S This enables common clock driver support for platforms based on Allwinner A10s/A13 SoC. +config CLK_SUN6I_A31 + bool "Clock driver for Allwinner A31/A31s" + default MACH_SUN6I + help + This enables common clock driver support for platforms based + on Allwinner A31/A31s SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index e217335a9b..e19aee9bf2 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o +obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c new file mode 100644 index 0000000000..3c8723c73c --- /dev/null +++ b/drivers/clk/sunxi/clk_a31.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a31_clk_priv { + void *base; +}; + +static int a31_clk_enable(struct clk *clk) +{ + struct a31_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB1_OTG: + setbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_AHB1_EHCI0: + case CLK_AHB1_EHCI1: + setbits_le32(priv->base + 0x60, + BIT(26 + (clk->id - CLK_AHB1_EHCI0))); + return 0; + case CLK_AHB1_OHCI0: + case CLK_AHB1_OHCI1: + case CLK_AHB1_OHCI2: + setbits_le32(priv->base + 0x60, + BIT(29 + (clk->id - CLK_AHB1_OHCI0))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + setbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a31_clk_disable(struct clk *clk) +{ + struct a31_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB1_OTG: + clrbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_AHB1_EHCI0: + case CLK_AHB1_EHCI1: + clrbits_le32(priv->base + 0x60, + BIT(26 + (clk->id - CLK_AHB1_EHCI0))); + return 0; + case CLK_AHB1_OHCI0: + case CLK_AHB1_OHCI1: + case CLK_AHB1_OHCI2: + clrbits_le32(priv->base + 0x60, + BIT(29 + (clk->id - CLK_AHB1_OHCI0))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + clrbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a31_clk_ops = { + .enable = a31_clk_enable, + .disable = a31_clk_disable, +}; + +static int a31_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a31_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a31_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a31_clk_ids[] = { + { .compatible = "allwinner,sun6i-a31-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun6i_a31) = { + .name = "sun6i_a31_ccu", + .id = UCLASS_CLK, + .of_match = a31_clk_ids, + .priv_auto_alloc_size = sizeof(struct a31_clk_priv), + .ofdata_to_platdata = a31_clk_ofdata_to_platdata, + .ops = &a31_clk_ops, + .probe = a31_clk_probe, + .bind = sunxi_clk_bind, +}; From patchwork Mon Jul 16 11:28:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944328 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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Mon, 16 Jul 2018 04:30:07 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:07 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:39 +0530 Message-Id: <20180716112850.3961-25-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 24/35] reset: sunxi: Add initial RESET driver for A31/A31s X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial reset driver for Allwinner A31/A31s. Implement reset deassert and assert functions for USB OHCI, EHCI, OTG and PHY bus reset and clock registers. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 7 ++ drivers/reset/sunxi/Makefile | 1 + drivers/reset/sunxi/reset_a31.c | 123 ++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/reset/sunxi/reset_a31.c diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index 40f4f4d0e6..bf1a2f05bf 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -23,6 +23,13 @@ config RESET_SUN5I_A10S This enables common reset driver support for platforms based on Allwinner A10s/A13 SoC. +config RESET_SUN6I_A31 + bool "Reset driver for Allwinner A31/A31s" + default MACH_SUN6I + help + This enables common reset driver support for platforms based + on Allwinner A31/A31s SoC. + config RESET_SUN8I_H3 bool "Reset driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile index 38b8907904..b599e1994b 100644 --- a/drivers/reset/sunxi/Makefile +++ b/drivers/reset/sunxi/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_RESET_SUN4I_A10) += reset_a10.o obj-$(CONFIG_RESET_SUN5I_A10S) += reset_a10s.o +obj-$(CONFIG_RESET_SUN6I_A31) += reset_a31.o obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_a31.c b/drivers/reset/sunxi/reset_a31.c new file mode 100644 index 0000000000..8c7a8a6bb9 --- /dev/null +++ b/drivers/reset/sunxi/reset_a31.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a31_reset_priv { + void *base; +}; + +static int a31_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun6i-a31-ccu.h for max id */ + if (reset_ctl->id > 56) + return -EINVAL; + + return 0; +} + +static int a31_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a31_reset_assert(struct reset_ctl *reset_ctl) +{ + struct a31_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_PHY2: + clrbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_AHB1_OTG: + clrbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_AHB1_EHCI0: + case RST_AHB1_EHCI1: + clrbits_le32(priv->base + 0x2c0, + BIT(26 + (reset_ctl->id - RST_AHB1_EHCI0))); + return 0; + case RST_AHB1_OHCI0: + case RST_AHB1_OHCI1: + case RST_AHB1_OHCI2: + clrbits_le32(priv->base + 0x2c0, + BIT(29 + (reset_ctl->id - RST_AHB1_OHCI0))); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +static int a31_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct a31_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_PHY2: + setbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_AHB1_OTG: + setbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_AHB1_EHCI0: + case RST_AHB1_EHCI1: + setbits_le32(priv->base + 0x2c0, + BIT(26 + (reset_ctl->id - RST_AHB1_EHCI0))); + return 0; + case RST_AHB1_OHCI0: + case RST_AHB1_OHCI1: + case RST_AHB1_OHCI2: + setbits_le32(priv->base + 0x2c0, + BIT(29 + (reset_ctl->id - RST_AHB1_OHCI0))); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +struct reset_ops a31_reset_ops = { + .request = a31_reset_request, + .free = a31_reset_free, + .rst_assert = a31_reset_assert, + .rst_deassert = a31_reset_deassert, +}; + +static int a31_reset_probe(struct udevice *dev) +{ + struct a31_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +U_BOOT_DRIVER(reset_sun6i_a31) = { + .name = "sun6i_a31_reset", + .id = UCLASS_RESET, + .ops = &a31_reset_ops, + .probe = a31_reset_probe, + .priv_auto_alloc_size = sizeof(struct a31_reset_priv), +}; From patchwork Mon Jul 16 11:28:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944338 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; 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Mon, 16 Jul 2018 04:30:10 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:09 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:40 +0530 Message-Id: <20180716112850.3961-26-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 25/35] clk: sunxi: Add initial CLK driver for A23 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial clock driver Allwinner A23. Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a23.c | 112 ++++++++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a23.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 1f44fed2b9..5f65c9ed44 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -29,6 +29,13 @@ config CLK_SUN6I_A31 This enables common clock driver support for platforms based on Allwinner A31/A31s SoC. +config CLK_SUN8I_A23 + bool "Clock driver for Allwinner A23" + default MACH_SUN8I_A23 + help + This enables common clock driver support for platforms based + on Allwinner A23 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index e19aee9bf2..8390602746 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -9,5 +9,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o +obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c new file mode 100644 index 0000000000..71f7447ea3 --- /dev/null +++ b/drivers/clk/sunxi/clk_a23.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a23_clk_priv { + void *base; +}; + +static int a23_clk_enable(struct clk *clk) +{ + struct a23_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + setbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_BUS_EHCI: + setbits_le32(priv->base + 0x60, BIT(26)); + return 0; + case CLK_BUS_OHCI: + setbits_le32(priv->base + 0x60, BIT(29)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI: + setbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a23_clk_disable(struct clk *clk) +{ + struct a23_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + clrbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_BUS_EHCI: + clrbits_le32(priv->base + 0x60, BIT(26)); + return 0; + case CLK_BUS_OHCI: + clrbits_le32(priv->base + 0x60, BIT(29)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI: + clrbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a23_clk_ops = { + .enable = a23_clk_enable, + .disable = a23_clk_disable, +}; + +static int a23_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a23_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a23_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a23_clk_ids[] = { + { .compatible = "allwinner,sun8i-a23-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_a23) = { + .name = "sun8i_a23_ccu", + .id = UCLASS_CLK, + .of_match = a23_clk_ids, + .priv_auto_alloc_size = sizeof(struct a23_clk_priv), + .ofdata_to_platdata = a23_clk_ofdata_to_platdata, + .ops = &a23_clk_ops, + .probe = a23_clk_probe, + .bind = sunxi_clk_bind, +}; From patchwork Mon Jul 16 11:28:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944335 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="KB2c3blu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThQd2Y9gz9ryt for ; Mon, 16 Jul 2018 21:44:25 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E8D35C220A3; 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Mon, 16 Jul 2018 04:30:12 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:12 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:41 +0530 Message-Id: <20180716112850.3961-27-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 26/35] reset: sunxi: Add initial RESET driver for A23 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial reset driver Allwinner A23. Implemented reset deassert and assert functions for USB OHCI, EHCI, OTG and PHY bus reset and clock registers. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 7 ++ drivers/reset/sunxi/Makefile | 1 + drivers/reset/sunxi/reset_a23.c | 111 ++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/reset/sunxi/reset_a23.c diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index bf1a2f05bf..6eb6a73205 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -30,6 +30,13 @@ config RESET_SUN6I_A31 This enables common reset driver support for platforms based on Allwinner A31/A31s SoC. +config RESET_SUN8I_A23 + bool "Reset driver for Allwinner A23" + default MACH_SUN8I_A23 + help + This enables common reset driver support for platforms based + on Allwinner A23 SoC. + config RESET_SUN8I_H3 bool "Reset driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile index b599e1994b..97452a275c 100644 --- a/drivers/reset/sunxi/Makefile +++ b/drivers/reset/sunxi/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_RESET_SUN4I_A10) += reset_a10.o obj-$(CONFIG_RESET_SUN5I_A10S) += reset_a10s.o obj-$(CONFIG_RESET_SUN6I_A31) += reset_a31.o +obj-$(CONFIG_RESET_SUN8I_A23) += reset_a23.o obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_a23.c b/drivers/reset/sunxi/reset_a23.c new file mode 100644 index 0000000000..2f315ff4bb --- /dev/null +++ b/drivers/reset/sunxi/reset_a23.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a23_reset_priv { + void *base; +}; + +static int a23_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun8i-a23-ccu.h for max id */ + if (reset_ctl->id > 39) + return -EINVAL; + + return 0; +} + +static int a23_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a23_reset_assert(struct reset_ctl *reset_ctl) +{ + struct a23_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + clrbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + clrbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_BUS_EHCI: + clrbits_le32(priv->base + 0x2c0, BIT(26)); + return 0; + case RST_BUS_OHCI: + clrbits_le32(priv->base + 0x2c0, BIT(29)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +static int a23_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct a23_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + setbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + setbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_BUS_EHCI: + setbits_le32(priv->base + 0x2c0, BIT(26)); + return 0; + case RST_BUS_OHCI: + setbits_le32(priv->base + 0x2c0, BIT(29)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +struct reset_ops a23_reset_ops = { + .request = a23_reset_request, + .free = a23_reset_free, + .rst_assert = a23_reset_assert, + .rst_deassert = a23_reset_deassert, +}; + +static int a23_reset_probe(struct udevice *dev) +{ + struct a23_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +U_BOOT_DRIVER(reset_sun8i_a23) = { + .name = "sun8i_a23_reset", + .id = UCLASS_RESET, + .ops = &a23_reset_ops, + .probe = a23_reset_probe, + .priv_auto_alloc_size = sizeof(struct a23_reset_priv), +}; From patchwork Mon Jul 16 11:28:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944350 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="kP8ikpqy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThZr4fFvz9s29 for ; Mon, 16 Jul 2018 21:51:32 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 52A38C2213D; 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Mon, 16 Jul 2018 04:30:15 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:14 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:42 +0530 Message-Id: <20180716112850.3961-28-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 27/35] clk: sunxi: a23: Add CLK support for A33 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" A33 has separate clock driver in Linux because of few clock differences wrt to A23 like audio etc,. these may not useful for U-Boot so added a33 ccu compatible on existing a23 clock driver. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 6 +++--- drivers/clk/sunxi/clk_a23.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 5f65c9ed44..40c6f999ca 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -30,11 +30,11 @@ config CLK_SUN6I_A31 on Allwinner A31/A31s SoC. config CLK_SUN8I_A23 - bool "Clock driver for Allwinner A23" - default MACH_SUN8I_A23 + bool "Clock driver for Allwinner A23/A33" + default MACH_SUN8I_A23 || MACH_SUN8I_A33 help This enables common clock driver support for platforms based - on Allwinner A23 SoC. + on Allwinner A23/A33 SoC. config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 71f7447ea3..84def883f1 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -97,6 +97,7 @@ static int a23_clk_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id a23_clk_ids[] = { { .compatible = "allwinner,sun8i-a23-ccu" }, + { .compatible = "allwinner,sun8i-a33-ccu" }, { } }; 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Mon, 16 Jul 2018 04:30:17 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:17 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:43 +0530 Message-Id: <20180716112850.3961-29-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 28/35] reset: sunxi: a23: Add RESET support A33 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Like CLK support is handling via A23 driver, even RESET can handle in similar way. So enable reset_a23 for A33 as well. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index 6eb6a73205..ce1215d9a8 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -31,11 +31,11 @@ config RESET_SUN6I_A31 on Allwinner A31/A31s SoC. config RESET_SUN8I_A23 - bool "Reset driver for Allwinner A23" - default MACH_SUN8I_A23 + bool "Reset driver for Allwinner A23/A33" + default MACH_SUN8I_A23 || MACH_SUN8I_A33 help This enables common reset driver support for platforms based - on Allwinner A23 SoC. + on Allwinner A23/A33 SoC. config RESET_SUN8I_H3 bool "Reset driver for Allwinner H3/H5" From patchwork Mon Jul 16 11:28:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944348 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="lRK5a6Ef"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThZV2gHcz9ryt for ; Mon, 16 Jul 2018 21:51:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 155ECC2216B; Mon, 16 Jul 2018 11:40:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D00ECC22101; Mon, 16 Jul 2018 11:31:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4EE95C220E8; Mon, 16 Jul 2018 11:30:29 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id BCE9AC2216A for ; Mon, 16 Jul 2018 11:30:21 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id e11-v6so2165219plb.3 for ; Mon, 16 Jul 2018 04:30:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OG/1m4JM4Xr28tGEmQj41rbAWavnyjjJA5CU5UgjtAw=; b=lRK5a6EfL8i1o8Z57bV3inEoxRsqhrM7hybF73yDvUQYtPG4FzhzSUm6S0OB+O6OPk 2qGOSi/jGPqt+BCSj9HzKMpLOcDGMds20GrXI/G6u4A6PNpO2xjCJ8uzepmurNDnTcku Raf57yuhAbcWQpdXv2+v37h0imJiGN6V4W82o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OG/1m4JM4Xr28tGEmQj41rbAWavnyjjJA5CU5UgjtAw=; b=pMGH2Ym2We0iHvXk7+9ls+nywIaztWtSnuJfdbV5q3SBoeE9AgaGjG+ZqQQO+ZGPp4 rR+y+JbH8lxesx1kpnoEMKFRtg+x208Delp8KasgYduGOup6udYhl54ldxEEn3Jp8Uj8 n7MU8ryQt/ob9p5wrM4DhW/ZJC8kFadcSIuoFjlaCaOiP4qg6VIY1hJEZYraw+zcQnX8 OO6Kzb7dFXVzs97HAEdSbVVudm8amXdyEAdo/mZeQOZMhVEqhAtw0pkJ6+MGPTRKkOlc nhY3FEumLlwYeRlCkCypepC+V3TAH5SqCtgh5k7HD0LtWxFuRG9M2OC/no+Vxh1XEcd1 kmUw== X-Gm-Message-State: AOUpUlEYnhqJA7/+aZSZ+jAaPrVJclxV9WpkEB5ruw9VbSpYXuzr0d3C KFsSglHeuhTQblooXhlr2MHCs3RS X-Google-Smtp-Source: AAOMgpewYildWYgCmRUhmIpN20QgLNeFnlzs/NhZcybRTjT6OtrlhzIR0w0wCV9sdqWPVn/xU4aiMQ== X-Received: by 2002:a17:902:8482:: with SMTP id c2-v6mr7361214plo.45.1531740620353; Mon, 16 Jul 2018 04:30:20 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:19 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:44 +0530 Message-Id: <20180716112850.3961-30-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 29/35] clk: sunxi: Add initial CLK driver for A83T X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial clock driver Allwinner A83T. Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 ++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a83t.c | 120 +++++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a83t.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 40c6f999ca..2378fb2992 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -36,6 +36,13 @@ config CLK_SUN8I_A23 This enables common clock driver support for platforms based on Allwinner A23/A33 SoC. +config CLK_SUN8I_A83T + bool "Clock driver for Allwinner A83T" + default MACH_SUN8I_A83T + help + This enables common clock driver support for platforms based + on Allwinner A83T SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 8390602746..90013c5b25 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o +obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c new file mode 100644 index 0000000000..524e8a0d33 --- /dev/null +++ b/drivers/clk/sunxi/clk_a83t.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a83t_clk_priv { + void *base; +}; + +static int a83t_clk_enable(struct clk *clk) +{ + struct a83t_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + setbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + setbits_le32(priv->base + 0x60, + BIT(26 + (clk->id - CLK_BUS_EHCI0))); + return 0; + case CLK_BUS_OHCI0: + setbits_le32(priv->base + 0x60, BIT(29)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_HSIC: + case CLK_USB_HSIC_12M: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + setbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a83t_clk_disable(struct clk *clk) +{ + struct a83t_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + clrbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + clrbits_le32(priv->base + 0x60, + BIT(26 + (clk->id - CLK_BUS_EHCI0))); + return 0; + case CLK_BUS_OHCI0: + clrbits_le32(priv->base + 0x60, BIT(29)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_HSIC: + case CLK_USB_HSIC_12M: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + clrbits_le32(priv->base + 0xcc, BIT(16)); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a83t_clk_ops = { + .enable = a83t_clk_enable, + .disable = a83t_clk_disable, +}; + +static int a83t_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a83t_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a83t_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a83t_clk_ids[] = { + { .compatible = "allwinner,sun8i-a83t-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_a83t) = { + .name = "sun8i_a83t_ccu", + .id = UCLASS_CLK, + .of_match = a83t_clk_ids, + .priv_auto_alloc_size = sizeof(struct a83t_clk_priv), + .ofdata_to_platdata = a83t_clk_ofdata_to_platdata, + .ops = &a83t_clk_ops, + .probe = a83t_clk_probe, + .bind = sunxi_clk_bind, +}; From patchwork Mon Jul 16 11:28:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944347 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Mon, 16 Jul 2018 04:30:22 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:22 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:45 +0530 Message-Id: <20180716112850.3961-31-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 30/35] reset: sunxi: Add initial RESET driver for A83T X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial reset driver for Allwinner A83T. Implement reset deassert and assert functions for USB OHCI, EHCI, OTG and PHY bus reset and clock registers. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 7 ++ drivers/reset/sunxi/Makefile | 1 + drivers/reset/sunxi/reset_a83t.c | 117 +++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 drivers/reset/sunxi/reset_a83t.c diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index ce1215d9a8..578351305e 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -37,6 +37,13 @@ config RESET_SUN8I_A23 This enables common reset driver support for platforms based on Allwinner A23/A33 SoC. +config RESET_SUN8I_A83T + bool "Reset driver for Allwinner A83T" + default MACH_SUN8I_A83T + help + This enables common reset driver support for platforms based + on Allwinner A83T SoC. + config RESET_SUN8I_H3 bool "Reset driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile index 97452a275c..58b2f7df9f 100644 --- a/drivers/reset/sunxi/Makefile +++ b/drivers/reset/sunxi/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_RESET_SUN4I_A10) += reset_a10.o obj-$(CONFIG_RESET_SUN5I_A10S) += reset_a10s.o obj-$(CONFIG_RESET_SUN6I_A31) += reset_a31.o obj-$(CONFIG_RESET_SUN8I_A23) += reset_a23.o +obj-$(CONFIG_RESET_SUN8I_A83T) += reset_a83t.o obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_a83t.c b/drivers/reset/sunxi/reset_a83t.c new file mode 100644 index 0000000000..c9a11fe15a --- /dev/null +++ b/drivers/reset/sunxi/reset_a83t.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a83t_reset_priv { + void *base; +}; + +static int a83t_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun8i-a83t-ccu.h for max id */ + if (reset_ctl->id > 44) + return -EINVAL; + + return 0; +} + +static int a83t_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a83t_reset_assert(struct reset_ctl *reset_ctl) +{ + struct a83t_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_HSIC: + clrbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + clrbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_BUS_EHCI0: + case RST_BUS_EHCI1: + clrbits_le32(priv->base + 0x2c0, + BIT(26 + (reset_ctl->id - RST_BUS_EHCI0))); + return 0; + case RST_BUS_OHCI0: + clrbits_le32(priv->base + 0x60, BIT(29)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +static int a83t_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct a83t_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + case RST_USB_HSIC: + setbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + setbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_BUS_EHCI0: + case RST_BUS_EHCI1: + setbits_le32(priv->base + 0x2c0, + BIT(26 + (reset_ctl->id - RST_BUS_EHCI0))); + return 0; + case RST_BUS_OHCI0: + setbits_le32(priv->base + 0x60, BIT(29)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +struct reset_ops a83t_reset_ops = { + .request = a83t_reset_request, + .free = a83t_reset_free, + .rst_assert = a83t_reset_assert, + .rst_deassert = a83t_reset_deassert, +}; + +static int a83t_reset_probe(struct udevice *dev) +{ + struct a83t_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +U_BOOT_DRIVER(reset_sun8i_a83t) = { + .name = "sun8i_a83t_reset", + .id = UCLASS_RESET, + .ops = &a83t_reset_ops, + .probe = a83t_reset_probe, + .priv_auto_alloc_size = sizeof(struct a83t_reset_priv), +}; From patchwork Mon Jul 16 11:28:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944352 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="pIhVQox/"; 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Mon, 16 Jul 2018 04:30:25 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:25 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:46 +0530 Message-Id: <20180716112850.3961-32-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 31/35] sunxi: Enable CLK and RESET X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" CLK and RESET drivers are now available for most of the Allwinner platforms, so enable in mach-sunxi/Kconfig Signed-off-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index be1ff10212..1d8ef8dc91 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -126,6 +126,8 @@ endif config MACH_SUNXI_H3_H5 bool + select CLK_SUNXI + select RESET_SUNXI select DM_I2C select DM_MMC if MMC select PHY_SUN4I_USB @@ -142,6 +144,8 @@ choice config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A + select CLK_SUNXI + select RESET_SUNXI select ARM_CORTEX_CPU_IS_UP select DM_MMC if MMC select DM_SCSI if SCSI @@ -153,6 +157,8 @@ config MACH_SUN4I config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7A + select CLK_SUNXI + select RESET_SUNXI select ARM_CORTEX_CPU_IS_UP select DRAM_SUN4I select DM_MMC if MMC @@ -167,6 +173,8 @@ config MACH_SUN6I select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK_SUNXI + select RESET_SUNXI select DRAM_SUN6I select DM_MMC if MMC select PHY_SUN4I_USB @@ -182,6 +190,8 @@ config MACH_SUN7I select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK_SUNXI + select RESET_SUNXI select DRAM_SUN4I select DM_MMC if MMC select PHY_SUN4I_USB @@ -195,6 +205,8 @@ config MACH_SUN8I_A23 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK_SUNXI + select RESET_SUNXI select DRAM_SUN8I_A23 select DM_MMC if MMC select PHY_SUN4I_USB @@ -209,6 +221,8 @@ config MACH_SUN8I_A33 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK_SUNXI + select RESET_SUNXI select DRAM_SUN8I_A33 select DM_MMC if MMC select PHY_SUN4I_USB @@ -221,6 +235,8 @@ config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7A select DM_MMC if MMC + select CLK_SUNXI + select RESET_SUNXI select DRAM_SUN8I_A83T select PHY_SUN4I_USB select SUNXI_GEN_SUN6I @@ -276,6 +292,8 @@ config MACH_SUN50I select ARM64 select DM_I2C select DM_MMC if MMC + select CLK_SUNXI + select RESET_SUNXI select PHY_SUN4I_USB select SUNXI_DE2 select SUNXI_GEN_SUN6I From patchwork Mon Jul 16 11:28:47 2018 Content-Type: text/plain; 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Mon, 16 Jul 2018 04:30:28 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:27 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:47 +0530 Message-Id: <20180716112850.3961-33-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Marek Vasut , Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 32/35] musb-new: sunxi: Use CLK and RESET support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver. Cc: Marek Vasut Signed-off-by: Jagan Teki --- drivers/usb/musb-new/sunxi.c | 82 +++++++++++++++++++++++------------- 1 file changed, 53 insertions(+), 29 deletions(-) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 9f71b84fd1..440be83f4e 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -16,9 +16,11 @@ * This file is part of the Inventra Controller Driver for Linux. */ #include +#include #include #include #include +#include #include #include #include @@ -78,16 +80,15 @@ struct sunxi_musb_config { struct musb_hdrc_config *config; - u8 rst_bit; - u8 clkgate_bit; }; struct sunxi_glue { struct musb_host_data mdata; - struct sunxi_ccm_reg *ccm; struct sunxi_musb_config *cfg; struct device dev; struct phy phy; + struct clk clocks; + struct reset_ctl resets; }; #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev) @@ -291,6 +292,18 @@ static int sunxi_musb_init(struct musb *musb) pr_debug("%s():\n", __func__); + ret = clk_enable(&glue->clocks); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + ret = reset_deassert(&glue->resets); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + return ret; + } + ret = generic_phy_init(&glue->phy); if (ret) { pr_err("failed to init USB PHY\n"); @@ -299,17 +312,6 @@ static int sunxi_musb_init(struct musb *musb) musb->isr = sunxi_musb_interrupt; - setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - setbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->rst_bit) - setbits_le32(&glue->ccm->ahb_reset0_cfg, - BIT(glue->cfg->rst_bit)); -#endif - USBC_ConfigFIFO_Base(); USBC_EnableDpDmPullUp(musb->mregs); USBC_EnableIdPullUp(musb->mregs); @@ -339,16 +341,17 @@ static int sunxi_musb_exit(struct musb *musb) } } -#ifdef CONFIG_SUNXI_GEN_SUN6I - clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->rst_bit) - clrbits_le32(&glue->ccm->ahb_reset0_cfg, - BIT(glue->cfg->rst_bit)); -#endif - clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - clrbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); + ret = reset_assert(&glue->resets); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + return ret; + } + + ret = clk_disable(&glue->clocks); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } return 0; } @@ -433,6 +436,7 @@ static int musb_usb_probe(struct udevice *dev) struct usb_bus_priv *priv = dev_get_uclass_priv(dev); struct musb_hdrc_platform_data pdata; void *base = dev_read_addr_ptr(dev); + int clock_nb, reset_nb; int ret; if (!base) @@ -442,9 +446,31 @@ static int musb_usb_probe(struct udevice *dev) if (!glue->cfg) return -EINVAL; - glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(glue->ccm)) - return PTR_ERR(glue->ccm); + clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks", + "#clock-cells"); + if (clock_nb < 0) { + dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb); + return clock_nb; + } + + ret = clk_get_by_index(dev, 0, &glue->clocks); + if (ret) { + dev_err(dev, "failed to get clock 0\n"); + clk_free(&glue->clocks); + } + + reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets", + "#reset-cells"); + if (reset_nb < 0) { + dev_err(dev, "failed to get reset phandle(%d)\n", clock_nb); + return reset_nb; + } + + ret = reset_get_by_index(dev, 0, &glue->resets); + if (ret) { + dev_err(dev, "failed to get reset 0\n"); + reset_free(&glue->resets); + } ret = generic_phy_get_by_name(dev, "usb", &glue->phy); if (ret) { @@ -499,8 +525,6 @@ static const struct sunxi_musb_config sun4i_a10_cfg = { static const struct sunxi_musb_config sun8i_h3_cfg = { .config = &musb_config_h3, - .rst_bit = 23, - .clkgate_bit = 23, }; static const struct udevice_id sunxi_musb_ids[] = { From patchwork Mon Jul 16 11:28:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944351 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="CHQFkiye"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41Thb51lBHz9ryt for ; Mon, 16 Jul 2018 21:51:45 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D85BAC2213D; Mon, 16 Jul 2018 11:40:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EAD0DC2218E; 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b=rVtKdvUrfuehVjqUqONjOuaDvF75gwAGRy5Vgy+OIvNUtqi8x510GvKDbOOIZIbAbL h9STHtrKiLzyzNup5IqYSxmr0Z3I4KIMHL2cPH+/EQi3n6kaLAh6KyeNDkRWtf5bhH04 P+aiDSA1eSYLoCGB+c+s1Y6BX7nJzXClpNnWzGh9GsD4FUepTbwINcXhhboShdU1sWb8 uuwDuij+zzndibD2DHyzFq2hk6hyzXLu4HmNBnr9OFYkf4wU0OnzEtXgSQkRpJJsMseE djPTqar5zuvCi5LB5qR2h6vIE7FAn1ZpY/487KR60e3hNOWH+NJChSKJasE5wO44iYwo IcuQ== X-Gm-Message-State: AOUpUlHaaxgS0/2+ShwOBbr7K4/aOYkyC3RgjHNDZBPE5f/rmOyEO9rK xqIcDBKuh1IGXFjvrxcWAHB54A== X-Google-Smtp-Source: AAOMgpcEgwphc0Yqv0bVlr9VZiIu6p7RmlfFB8/L/N8Clf/Rp6Fx8HQSNoPfPUoJXbd1+ebBPK1sEg== X-Received: by 2002:a17:902:b594:: with SMTP id a20-v6mr11081448pls.140.1531740631188; Mon, 16 Jul 2018 04:30:31 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:30 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:48 +0530 Message-Id: <20180716112850.3961-34-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Marek Vasut , Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 33/35] phy: sun4i-usb: Use CLK and RESET support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver. Cc: Marek Vasut Signed-off-by: Jagan Teki --- drivers/phy/allwinner/phy-sun4i-usb.c | 63 ++++++++++++++++++--------- 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 81fcd1f910..36db435e37 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -11,10 +11,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -88,38 +90,26 @@ struct sun4i_usb_phy_info { const char *gpio_vbus; const char *gpio_vbus_det; const char *gpio_id_det; - int rst_mask; } phy_info[] = { { .gpio_vbus = CONFIG_USB0_VBUS_PIN, .gpio_vbus_det = CONFIG_USB0_VBUS_DET, .gpio_id_det = CONFIG_USB0_ID_DET, - .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK), }, { .gpio_vbus = CONFIG_USB1_VBUS_PIN, .gpio_vbus_det = NULL, .gpio_id_det = NULL, - .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK), }, { .gpio_vbus = CONFIG_USB2_VBUS_PIN, .gpio_vbus_det = NULL, .gpio_id_det = NULL, -#ifdef CONFIG_MACH_SUN8I_A83T - .rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | - CCM_USB_CTRL_12M_CLK), -#else - .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK), -#endif }, { .gpio_vbus = CONFIG_USB3_VBUS_PIN, .gpio_vbus_det = NULL, .gpio_id_det = NULL, -#ifdef CONFIG_MACH_SUNXI_H3_H5 - .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK), -#endif }, }; @@ -129,13 +119,13 @@ struct sun4i_usb_phy_plat { int gpio_vbus; int gpio_vbus_det; int gpio_id_det; - int rst_mask; + struct clk clocks; + struct reset_ctl resets; int id; }; struct sun4i_usb_phy_data { void __iomem *base; - struct sunxi_ccm_reg *ccm; const struct sun4i_usb_phy_cfg *cfg; struct sun4i_usb_phy_plat *usb_phy; }; @@ -269,8 +259,19 @@ static int sun4i_usb_phy_init(struct phy *phy) struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; u32 val; + int ret; - setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask); + ret = clk_enable(&usb_phy->clocks); + if (ret) { + dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id); + return ret; + } + + ret = reset_deassert(&usb_phy->resets); + if (ret) { + dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id); + return ret; + } if (data->cfg->type == sun8i_a83t_phy) { if (phy->id == 0) { @@ -311,6 +312,7 @@ static int sun4i_usb_phy_exit(struct phy *phy) { struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; + int ret; if (phy->id == 0) { if (data->cfg->type == sun8i_a83t_phy) { @@ -323,7 +325,17 @@ static int sun4i_usb_phy_exit(struct phy *phy) sun4i_usb_phy_passby(phy, false); - clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask); + ret = clk_disable(&usb_phy->clocks); + if (ret) { + dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id); + return ret; + } + + ret = reset_assert(&usb_phy->resets); + if (ret) { + dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id); + return ret; + } return 0; } @@ -410,10 +422,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev) if (IS_ERR(data->base)) return PTR_ERR(data->base); - data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(data->ccm)) - return PTR_ERR(data->ccm); - data->usb_phy = plat; for (i = 0; i < data->cfg->num_phys; i++) { struct sun4i_usb_phy_plat *phy = &plat[i]; @@ -451,6 +459,20 @@ static int sun4i_usb_phy_probe(struct udevice *dev) sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP); } + snprintf(name, sizeof(name), "usb%d_phy", i); + ret = clk_get_by_name(dev, name, &phy->clocks); + if (ret) { + dev_err(dev, "failed to get usb%d_phy clock phandle\n", i); + return ret; + } + + snprintf(name, sizeof(name), "usb%d_reset", i); + ret = reset_get_by_name(dev, name, &phy->resets); + if (ret) { + dev_err(dev, "failed to get usb%d_reset reset phandle\n", i); + return ret; + } + if (i || data->cfg->phy0_dual_route) { snprintf(name, sizeof(name), "pmu%d", i); phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name); @@ -459,7 +481,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev) } phy->id = i; - phy->rst_mask = info->rst_mask; }; debug("Allwinner Sun4I USB PHY driver loaded\n"); From patchwork Mon Jul 16 11:28:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944334 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="DF9mqwox"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThPz2vzRz9ryt for ; Mon, 16 Jul 2018 21:43:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D967AC22113; Mon, 16 Jul 2018 11:43:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E704EC22127; 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b=TVqkHQQTFPuE1WseZym6md4RBLdyWQaJPKjh/iY075fTCANaGSlCmbkBYsdtUMLfYB 3O9ZnMzq4g6iEFAbsUrZ6Krid5s/g7aOINpmpFA5KCZBsCKoiXCVirBI3W5q731Vw6ib I2RpNb/UIb21tUFYl98gZjluynWqFnUzIXDShSZKxatGYC6Jq3LK7SJvDHr425y1uY1q 8UruIz7OmI5V6fUVK6ZBBS8czeBrm+675OrM519Us5kk55o4cbm/n+XDt+Dup0mHOawR U1fzbIFohoDkjUmuRTgE5XYSE9ztsecMmR41sMx4rZK5I83E5LNkTryxBLmwVdzJdoyn dW0A== X-Gm-Message-State: AOUpUlHChq9xMCEagRyKSqkC61zpU6+OqEelLA45lh+CyHjQQ9r4K4HL QILBWhWfF0Rf/487XUNTyGm3xQ== X-Google-Smtp-Source: AAOMgpcWxVUqrUdayTzETGOnqE3X7FdrXoVobStKDsSSg3J9mNs0RGvV6PfCnaWUJWdUjEDCUZoJgA== X-Received: by 2002:a65:4c87:: with SMTP id m7-v6mr14978673pgt.98.1531740634217; Mon, 16 Jul 2018 04:30:34 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:33 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:49 +0530 Message-Id: <20180716112850.3961-35-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Marek Vasut , Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 34/35] sunxi: usb: Switch to Generic host controllers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Once of key blocker for using USB Generic host controller drivers in Allwinner are CLK and RESET drivers, now these available for USB usage. So switch to use EHCI and OHCI Generic controllers. Enabling USB is wisely a board choise, so Enable USB_OHCI_HCD where it already have USB_EHCI_HCD Cc: Marek Vasut Signed-off-by: Jagan Teki --- configs/A10-OLinuXino-Lime_defconfig | 1 + configs/A10s-OLinuXino-M_defconfig | 1 + configs/A13-OLinuXinoM_defconfig | 1 + configs/A13-OLinuXino_defconfig | 1 + configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 + configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-OLinuXino-Lime_defconfig | 1 + configs/A20-Olimex-SOM204-EVB_defconfig | 2 ++ configs/Auxtek-T003_defconfig | 1 + configs/Auxtek-T004_defconfig | 1 + configs/Bananapi_defconfig | 1 + configs/Bananapi_m2m_defconfig | 1 + configs/Bananapro_defconfig | 1 + configs/CHIP_defconfig | 1 + configs/CHIP_pro_defconfig | 1 + configs/CSQ_CS908_defconfig | 1 + configs/Colombus_defconfig | 1 + configs/Cubieboard2_defconfig | 1 + configs/Cubieboard_defconfig | 1 + configs/Cubietruck_plus_defconfig | 1 + configs/Hummingbird_A31_defconfig | 1 + configs/Itead_Ibox_A20_defconfig | 1 + configs/Linksprite_pcDuino3_Nano_defconfig | 1 + configs/Linksprite_pcDuino3_defconfig | 1 + configs/Linksprite_pcDuino_defconfig | 1 + configs/MK808C_defconfig | 1 + configs/Marsboard_A10_defconfig | 1 + configs/Mele_A1000G_quad_defconfig | 1 + configs/Mele_A1000_defconfig | 1 + configs/Mele_I7_defconfig | 1 + configs/Mele_M3_defconfig | 1 + configs/Mele_M5_defconfig | 1 + configs/Mele_M9_defconfig | 1 + configs/Mini-X_defconfig | 1 + configs/Orangepi_defconfig | 1 + configs/Orangepi_mini_defconfig | 1 + configs/Sinlinx_SinA31s_defconfig | 1 + configs/Sinlinx_SinA33_defconfig | 1 + configs/Sinovoip_BPI_M2_Plus_defconfig | 1 + configs/Sinovoip_BPI_M2_defconfig | 1 + configs/Sinovoip_BPI_M3_defconfig | 1 + configs/Wexler_TAB7200_defconfig | 1 + configs/Wobo_i5_defconfig | 1 + configs/a64-olinuxino_defconfig | 1 + configs/ba10_tv_box_defconfig | 1 + configs/bananapi_m1_plus_defconfig | 1 + configs/bananapi_m64_defconfig | 1 + configs/ga10h_v1_1_defconfig | 1 + configs/h8_homlet_v2_defconfig | 1 + configs/i12-tvbox_defconfig | 1 + configs/icnova-a20-swac_defconfig | 1 + configs/inet1_defconfig | 1 + configs/inet_q972_defconfig | 1 + configs/jesurun_q5_defconfig | 1 + configs/libretech_all_h3_cc_h2_plus_defconfig | 1 + configs/libretech_all_h3_cc_h3_defconfig | 1 + configs/libretech_all_h3_cc_h5_defconfig | 1 + configs/mixtile_loftq_defconfig | 1 + configs/mk802_a10s_defconfig | 1 + configs/mk802_defconfig | 1 + configs/mk802ii_defconfig | 1 + configs/nanopi_a64_defconfig | 1 + configs/nanopi_m1_defconfig | 1 + configs/nanopi_m1_plus_defconfig | 1 + configs/nanopi_neo2_defconfig | 1 + configs/nanopi_neo_air_defconfig | 1 + configs/nanopi_neo_defconfig | 1 + configs/nanopi_neo_plus2_defconfig | 1 + configs/orangepi_2_defconfig | 1 + configs/orangepi_lite_defconfig | 1 + configs/orangepi_one_defconfig | 1 + configs/orangepi_pc2_defconfig | 1 + configs/orangepi_pc_defconfig | 1 + configs/orangepi_pc_plus_defconfig | 1 + configs/orangepi_plus2e_defconfig | 1 + configs/orangepi_plus_defconfig | 1 + configs/orangepi_prime_defconfig | 1 + configs/orangepi_r1_defconfig | 1 + configs/orangepi_win_defconfig | 1 + configs/orangepi_zero_defconfig | 1 + configs/orangepi_zero_plus2_defconfig | 1 + configs/orangepi_zero_plus_defconfig | 1 + configs/parrot_r16_defconfig | 1 + configs/pine64_plus_defconfig | 1 + configs/r7-tv-dongle_defconfig | 1 + configs/sopine_baseboard_defconfig | 1 + configs/sun8i_a23_evb_defconfig | 1 + configs/sunxi_Gemei_G9_defconfig | 1 + configs/tbs_a711_defconfig | 1 + drivers/usb/host/Kconfig | 2 ++ include/configs/sun4i.h | 4 ---- include/configs/sun50i.h | 5 ----- include/configs/sun5i.h | 4 ---- include/configs/sun6i.h | 4 ---- include/configs/sun7i.h | 4 ---- include/configs/sun8i.h | 4 ---- include/configs/sunxi-common.h | 1 - 97 files changed, 92 insertions(+), 26 deletions(-) diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index feb1173c0b..e8fecbe15f 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -20,5 +20,6 @@ CONFIG_SUN4I_EMAC=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 9498a6d752..bee913cb0b 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -16,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SUN4I_EMAC=y CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index ed507cdf0b..dd5c25ca9f 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -18,5 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUNXI_NO_PMIC=y CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index b8ec1e54db..04682dcac4 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -25,6 +25,7 @@ CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 98a8ceb178..bc5820263c 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -28,6 +28,7 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 134d1d3fef..99987a8683 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -26,6 +26,7 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index b7c13a6932..1b59174120 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -19,5 +19,6 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index cfb7ffa556..0537378ba1 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_USB_OHCI_HCD=y CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN7I=y @@ -27,6 +28,7 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index ce4806cf5e..a2bf5037ed 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 5faf45c3d7..4c1117e4bb 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -12,5 +12,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 7a9b5fe0e5..53752b2e12 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index 2316437c94..a21796fa67 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 5a8ded0493..ad4ce1f662 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -22,5 +22,6 @@ CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO4_VOLT=2500 CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index c122944881..2dfa5237bc 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -16,6 +16,7 @@ CONFIG_DFU_RAM=y CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 5d63fadef5..1333877957 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_NAND_OOBSIZE=0x100 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index b103e7e00d..7612cc8989 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -14,6 +14,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index c85e47cb11..6310420c29 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -24,5 +24,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 418da63ba8..6e883155b9 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -16,5 +16,6 @@ CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 27223d201e..dbeda7370d 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SCSI_AHCI=y CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index d76bc6748b..6a0e4c5836 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -22,6 +22,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_AXP_FLDO1_VOLT=1200 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 24126fde28..81eb59ebd1 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -16,5 +16,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index dfef071476..93c89890a7 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -16,5 +16,6 @@ CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 2df6761455..8487263fd8 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index d7e9c26cbf..7a1fc26434 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -18,5 +18,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_DM_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 500f885599..b18b02307f 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -11,5 +11,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN4I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 62768b8656..c3d914efe3 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -9,5 +9,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 55c27b8435..37bdeb0c37 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -12,5 +12,6 @@ CONFIG_SCSI_AHCI=y CONFIG_SUN4I_EMAC=y CONFIG_SUNXI_NO_PMIC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index e084454293..b3a05f2c0d 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -17,6 +17,7 @@ CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 367f2aaf7a..021753c221 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SCSI_AHCI=y CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 4fa61d311f..c9398676e2 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -16,5 +16,6 @@ CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index 93a2395aee..bc447a4a90 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -16,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index 6b198be6f6..37e90e1eaf 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -17,5 +17,6 @@ CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index af89c50ee1..94190499bf 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -16,5 +16,6 @@ CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index e32935e132..dfaa649e95 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index 88e55495d5..c347e32927 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -21,5 +21,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index d562273bef..cfab739552 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -24,5 +24,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 9744aef096..0aa02d687c 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -17,5 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s" CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 061f27c9db..2d7b295188 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_DFU=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 diff --git a/configs/Sinovoip_BPI_M2_Plus_defconfig b/configs/Sinovoip_BPI_M2_Plus_defconfig index a325e9f806..b01aa560d2 100644 --- a/configs/Sinovoip_BPI_M2_Plus_defconfig +++ b/configs/Sinovoip_BPI_M2_Plus_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index 65d81a5284..fa42670355 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -16,5 +16,6 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_AXP_ALDO2_VOLT=1800 CONFIG_AXP_DLDO1_VOLT=3000 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 479dd05dfb..91a3621d77 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -23,6 +23,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_SW_ON=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 9a431ee4cd..d031b05f1a 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 88ccfd406e..8ae00abcff 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index b32df990a0..54f6a98472 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 88199c8e78..b6776e3cb9 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN4I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 539ed73495..dde7b17229 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -19,4 +19,5 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 40c1c18aca..df0bbb4db5 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 02cc9677aa..4196ad6863 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -22,6 +22,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 80bdb20e8a..380949b1c2 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -15,6 +15,7 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index a3c4b0e76c..983627afbb 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index 8fca6e81ed..6d6792553e 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -20,5 +20,6 @@ CONFIG_CMD_UNZIP=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 100d075960..46f8f3c095 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index b928622813..9a22499b23 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -19,6 +19,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 00bb745be2..c0c46a1d4e 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN4I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index 0cbcd48aad..b511ef1abe 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -11,5 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-libretech-all-h3-cc" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 185facdf3e..1298ec7829 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -11,5 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index 061bddc8fd..e53a74de71 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -11,5 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-libretech-all-h3-cc" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 79d984ba7b..59321b108d 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -16,5 +16,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 5129b49506..233925ee6e 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 81d121fb84..454339a7cf 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUNXI_NO_PMIC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 84ae234fdc..2ce58ca64d 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -8,5 +8,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 0a04911c81..091f395db3 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index e0ae3c7c60..8440bd28c9 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1" # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index ee22364760..3918b7e21e 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 35058186f5..100f144ed0 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index f953b71f03..c2659627bc 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -12,5 +12,6 @@ CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index 66919e5a2b..44cd1036dd 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -13,5 +13,6 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 70798a8e9f..bcaf2e5068 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 577a32255b..e88615c8c6 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index f3fd864a6d..21b05daf45 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 23f4973e5b..4c7f6027ac 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -11,5 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index ca1e586e89..3dabfeb300 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 134db79e72..083e0eba9b 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index 01c1cd7736..4068afb20e 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index a6e61a5065..f049d3f8b9 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 8e32b0af32..4c1d609760 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -17,5 +17,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 6161863258..b20835b0d7 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index 8e6ee7b2db..289f8d7650 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1" CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index d7211b5823..e14faacfaf 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 6afd4a3bfa..6f2a64002f 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index fdb6bb4ed9..95c3d29b85 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index fc656ce733..cd61b17cd4 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index 553a8d6572..936f08185f 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot" # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_CONS_INDEX=5 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 21ce06f370..c632d24456 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -12,5 +12,6 @@ CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_PHY_REALTEK=y CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 9a66ee90f9..eaf7f4816a 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -12,5 +12,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index c79c111b5d..0da899c155 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -16,5 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index 4cb2798ce7..c32f024cd2 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -13,5 +13,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=5 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index d88dd4ebad..c42074c0d8 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index 5d58f5ceb4..d7d99c4dba 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -18,6 +18,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_DCDC5_VOLT=1200 +CONFIG_USB_OHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b4dd005651..60a152704a 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -191,6 +191,7 @@ config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL depends on DM_USB + default ARCH_SUNXI default n ---help--- Enables support for generic EHCI controller. @@ -221,6 +222,7 @@ config USB_OHCI_GENERIC bool "Support for generic OHCI USB controller" depends on OF_CONTROL depends on DM_USB + default ARCH_SUNXI select USB_HOST ---help--- Enables support for generic OHCI controller. diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index af079a71ee..6033760583 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -11,10 +11,6 @@ * A10 specific configuration */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_SUNXI -#endif - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 8cfac38106..9321373fb5 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -10,11 +10,6 @@ * A64 specific configuration */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_SUNXI -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index c3692caa73..ee42af80d4 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -11,10 +11,6 @@ * High Level Configuration Options */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_SUNXI -#endif - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 1523684fad..1e490daac1 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -14,10 +14,6 @@ * A31 specific configuration */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_SUNXI -#endif - #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index bb8f217b25..d2fd586672 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -12,10 +12,6 @@ * A20 specific configuration */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_SUNXI -#endif - #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 7dc8693b76..9b4675e4c3 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -12,10 +12,6 @@ * A23 specific configuration */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_SUNXI -#endif - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5ee6dbd216..220b74c4d5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -297,7 +297,6 @@ extern int soft_i2c_gpio_scl; #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_OHCI_SUNXI #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #endif From patchwork Mon Jul 16 11:28:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944354 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: 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smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:36 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:50 +0530 Message-Id: <20180716112850.3961-36-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Marek Vasut , Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 35/35] usb: host: Drop [e-o]hci-sunxi drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now Allwinner platform is all set to use Generic USB controller drivers, so remove the legacy sunxi drivers. Cc: Marek Vasut Signed-off-by: Jagan Teki --- drivers/usb/host/Makefile | 2 - drivers/usb/host/ehci-sunxi.c | 204 ----------------------------- drivers/usb/host/ohci-sunxi.c | 233 ---------------------------------- scripts/config_whitelist.txt | 2 - 4 files changed, 441 deletions(-) delete mode 100644 drivers/usb/host/ehci-sunxi.c delete mode 100644 drivers/usb/host/ohci-sunxi.c diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index cb8c315a15..b62fdbb1d2 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o -obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o @@ -37,7 +36,6 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o -obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c deleted file mode 100644 index 7a79931a97..0000000000 --- a/drivers/usb/host/ehci-sunxi.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Sunxi ehci glue - * - * Copyright (C) 2015 Hans de Goede - * Copyright (C) 2014 Roman Byshko - * - * Based on code from - * Allwinner Technology Co., Ltd. - */ - -#include -#include -#include -#include -#include "ehci.h" -#include - -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define BASE_DIST 0x8000 -#define AHB_CLK_DIST 2 -#else -#define BASE_DIST 0x1000 -#define AHB_CLK_DIST 1 -#endif - -#define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0 -#define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0 - -struct ehci_sunxi_cfg { - bool has_reset; - u32 extra_ahb_gate_mask; - u32 reset0_cfg_offset; -}; - -struct ehci_sunxi_priv { - struct ehci_ctrl ehci; - struct sunxi_ccm_reg *ccm; - u32 *reset0_cfg; - int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ - struct phy phy; - const struct ehci_sunxi_cfg *cfg; -}; - -static int ehci_usb_probe(struct udevice *dev) -{ - struct usb_platdata *plat = dev_get_platdata(dev); - struct ehci_sunxi_priv *priv = dev_get_priv(dev); - struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev); - struct ehci_hcor *hcor; - int extra_ahb_gate_mask = 0; - u8 reg_mask = 0; - int phys, ret; - - priv->cfg = (const struct ehci_sunxi_cfg *)dev_get_driver_data(dev); - priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(priv->ccm)) - return PTR_ERR(priv->ccm); - - priv->reset0_cfg = (void *)priv->ccm + - priv->cfg->reset0_cfg_offset; - - phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); - if (phys < 0) { - phys = 0; - goto no_phy; - } - - ret = generic_phy_get_by_name(dev, "usb", &priv->phy); - if (ret) { - pr_err("failed to get %s usb PHY\n", dev->name); - return ret; - } - - ret = generic_phy_init(&priv->phy); - if (ret) { - pr_err("failed to init %s USB PHY\n", dev->name); - return ret; - } - - ret = generic_phy_power_on(&priv->phy); - if (ret) { - pr_err("failed to power on %s USB PHY\n", dev->name); - return ret; - } - -no_phy: - /* - * This should go away once we've moved to the driver model for - * clocks resp. phys. - */ - reg_mask = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; - extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; - priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - - setbits_le32(&priv->ccm->ahb_gate0, - priv->ahb_gate_mask | extra_ahb_gate_mask); - if (priv->cfg->has_reset) - setbits_le32(priv->reset0_cfg, - priv->ahb_gate_mask | extra_ahb_gate_mask); - - hcor = (struct ehci_hcor *)((uintptr_t)hccr + - HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - - return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type); -} - -static int ehci_usb_remove(struct udevice *dev) -{ - struct ehci_sunxi_priv *priv = dev_get_priv(dev); - int ret; - - if (generic_phy_valid(&priv->phy)) { - ret = generic_phy_exit(&priv->phy); - if (ret) { - pr_err("failed to exit %s USB PHY\n", dev->name); - return ret; - } - } - - ret = ehci_deregister(dev); - if (ret) - return ret; - - if (priv->cfg->has_reset) - clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask); - clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); - - return 0; -} - -static const struct ehci_sunxi_cfg sun4i_a10_cfg = { - .has_reset = false, -}; - -static const struct ehci_sunxi_cfg sun6i_a31_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ehci_sunxi_cfg sun8i_h3_cfg = { - .has_reset = true, - .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ehci_sunxi_cfg sun9i_a80_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct udevice_id ehci_usb_ids[] = { - { - .compatible = "allwinner,sun4i-a10-ehci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun5i-a13-ehci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun6i-a31-ehci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun7i-a20-ehci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun8i-a23-ehci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-a83t-ehci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-h3-ehci", - .data = (ulong)&sun8i_h3_cfg, - }, - { - .compatible = "allwinner,sun9i-a80-ehci", - .data = (ulong)&sun9i_a80_cfg, - }, - { - .compatible = "allwinner,sun50i-a64-ehci", - .data = (ulong)&sun8i_h3_cfg, - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(ehci_sunxi) = { - .name = "ehci_sunxi", - .id = UCLASS_USB, - .of_match = ehci_usb_ids, - .probe = ehci_usb_probe, - .remove = ehci_usb_remove, - .ops = &ehci_usb_ops, - .platdata_auto_alloc_size = sizeof(struct usb_platdata), - .priv_auto_alloc_size = sizeof(struct ehci_sunxi_priv), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c deleted file mode 100644 index bb3c2475df..0000000000 --- a/drivers/usb/host/ohci-sunxi.c +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Sunxi ohci glue - * - * Copyright (C) 2015 Hans de Goede - * - * Based on code from - * Allwinner Technology Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include "ohci.h" -#include - -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define BASE_DIST 0x8000 -#define AHB_CLK_DIST 2 -#else -#define BASE_DIST 0x1000 -#define AHB_CLK_DIST 1 -#endif - -#define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0 -#define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0 - -struct ohci_sunxi_cfg { - bool has_reset; - u32 extra_ahb_gate_mask; - u32 extra_usb_gate_mask; - u32 reset0_cfg_offset; -}; - -struct ohci_sunxi_priv { - ohci_t ohci; - struct sunxi_ccm_reg *ccm; - u32 *reset0_cfg; - int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ - int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */ - struct phy phy; - const struct ohci_sunxi_cfg *cfg; -}; - -static fdt_addr_t last_ohci_addr = 0; - -static int ohci_usb_probe(struct udevice *dev) -{ - struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); - struct ohci_sunxi_priv *priv = dev_get_priv(dev); - struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev); - int extra_ahb_gate_mask = 0; - u8 reg_mask = 0; - int phys, ret; - - if ((fdt_addr_t)regs > last_ohci_addr) - last_ohci_addr = (fdt_addr_t)regs; - - priv->cfg = (const struct ohci_sunxi_cfg *)dev_get_driver_data(dev); - priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(priv->ccm)) - return PTR_ERR(priv->ccm); - - priv->reset0_cfg = (void *)priv->ccm + - priv->cfg->reset0_cfg_offset; - - phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); - if (phys < 0) { - phys = 0; - goto no_phy; - } - - ret = generic_phy_get_by_name(dev, "usb", &priv->phy); - if (ret) { - pr_err("failed to get %s usb PHY\n", dev->name); - return ret; - } - - ret = generic_phy_init(&priv->phy); - if (ret) { - pr_err("failed to init %s USB PHY\n", dev->name); - return ret; - } - - ret = generic_phy_power_on(&priv->phy); - if (ret) { - pr_err("failed to power on %s USB PHY\n", dev->name); - return ret; - } - -no_phy: - bus_priv->companion = true; - - /* - * This should go away once we've moved to the driver model for - * clocks resp. phys. - */ - reg_mask = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; - extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - priv->usb_gate_mask <<= reg_mask; - - setbits_le32(&priv->ccm->ahb_gate0, - priv->ahb_gate_mask | extra_ahb_gate_mask); - setbits_le32(&priv->ccm->usb_clk_cfg, - priv->usb_gate_mask | priv->cfg->extra_usb_gate_mask); - if (priv->cfg->has_reset) - setbits_le32(priv->reset0_cfg, - priv->ahb_gate_mask | extra_ahb_gate_mask); - - return ohci_register(dev, regs); -} - -static int ohci_usb_remove(struct udevice *dev) -{ - struct ohci_sunxi_priv *priv = dev_get_priv(dev); - fdt_addr_t base_addr = devfdt_get_addr(dev); - int ret; - - if (generic_phy_valid(&priv->phy)) { - ret = generic_phy_exit(&priv->phy); - if (ret) { - pr_err("failed to exit %s USB PHY\n", dev->name); - return ret; - } - } - - ret = ohci_deregister(dev); - if (ret) - return ret; - - if (priv->cfg->has_reset) - clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask); - /* - * On the A64 CLK_USB_OHCI0 is the parent of CLK_USB_OHCI1, so - * we have to wait with bringing down any clock until the last - * OHCI controller is removed. - */ - if (!priv->cfg->extra_usb_gate_mask || base_addr == last_ohci_addr) { - u32 usb_gate_mask = priv->usb_gate_mask; - - usb_gate_mask |= priv->cfg->extra_usb_gate_mask; - clrbits_le32(&priv->ccm->usb_clk_cfg, usb_gate_mask); - } - - clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); - - return 0; -} - -static const struct ohci_sunxi_cfg sun4i_a10_cfg = { - .has_reset = false, -}; - -static const struct ohci_sunxi_cfg sun6i_a31_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ohci_sunxi_cfg sun8i_h3_cfg = { - .has_reset = true, - .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ohci_sunxi_cfg sun9i_a80_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ohci_sunxi_cfg sun50i_a64_cfg = { - .has_reset = true, - .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, - .extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct udevice_id ohci_usb_ids[] = { - { - .compatible = "allwinner,sun4i-a10-ohci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun5i-a13-ohci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun6i-a31-ohci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun7i-a20-ohci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun8i-a23-ohci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-a83t-ohci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-h3-ohci", - .data = (ulong)&sun8i_h3_cfg, - }, - { - .compatible = "allwinner,sun9i-a80-ohci", - .data = (ulong)&sun9i_a80_cfg, - }, - { - .compatible = "allwinner,sun50i-a64-ohci", - .data = (ulong)&sun50i_a64_cfg, - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(usb_ohci) = { - .name = "ohci_sunxi", - .id = UCLASS_USB, - .of_match = ohci_usb_ids, - .probe = ohci_usb_probe, - .remove = ohci_usb_remove, - .ops = &ohci_usb_ops, - .platdata_auto_alloc_size = sizeof(struct usb_platdata), - .priv_auto_alloc_size = sizeof(struct ohci_sunxi_priv), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a724ed5850..bd59afdd27 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4622,7 +4622,6 @@ CONFIG_USB_EHCI_MX5 CONFIG_USB_EHCI_MXC CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_SPEAR -CONFIG_USB_EHCI_SUNXI CONFIG_USB_EHCI_TEGRA CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_EHCI_VCT @@ -4664,7 +4663,6 @@ CONFIG_USB_OHCI CONFIG_USB_OHCI_EP93XX CONFIG_USB_OHCI_LPC32XX CONFIG_USB_OHCI_NEW -CONFIG_USB_OHCI_SUNXI CONFIG_USB_OTG CONFIG_USB_OTG_BLACKLIST_HUB CONFIG_USB_PHY_CFG_BASE