From patchwork Thu Jul 5 15:14:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pascal PAILLET-LME X-Patchwork-Id: 939984 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41M1cW4G82z9s1b for ; Fri, 6 Jul 2018 01:14:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754098AbeGEPOt convert rfc822-to-8bit (ORCPT ); Thu, 5 Jul 2018 11:14:49 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:57377 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754004AbeGEPOr (ORCPT ); Thu, 5 Jul 2018 11:14:47 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w65F9FVj017072; Thu, 5 Jul 2018 17:14:23 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2k1k1j0twu-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 05 Jul 2018 17:14:23 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E543D34; Thu, 5 Jul 2018 15:14:22 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node1.st.com [10.75.127.16]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B1CEC26DC; Thu, 5 Jul 2018 15:14:22 +0000 (GMT) Received: from SFHDAG6NODE2.st.com (10.75.127.17) by SFHDAG6NODE1.st.com (10.75.127.16) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 5 Jul 2018 17:14:22 +0200 Received: from SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6]) by SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6%20]) with mapi id 15.00.1347.000; Thu, 5 Jul 2018 17:14:22 +0200 From: Pascal PAILLET-LME To: "dmitry.torokhov@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "lee.jones@linaro.org" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "wim@linux-watchdog.org" , "linux@roeck-us.net" , "linux-input@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-watchdog@vger.kernel.org" , "benjamin.gaignard@linaro.org" CC: Pascal PAILLET-LME Subject: [PATCH 1/8] dt-bindings: mfd: document stpmu1 pmic Thread-Topic: [PATCH 1/8] dt-bindings: mfd: document stpmu1 pmic Thread-Index: AQHUFHLaBR9//vlFr0qcgonUrwaf9A== Date: Thu, 5 Jul 2018 15:14:22 +0000 Message-ID: <1530803657-17684-2-git-send-email-p.paillet@st.com> References: <1530803657-17684-1-git-send-email-p.paillet@st.com> In-Reply-To: <1530803657-17684-1-git-send-email-p.paillet@st.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-05_05:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: pascal paillet stpmu1 is a pmic from STMicroelectronics. The stpmu1 integrates 10 regulators and 3 switches with various capabilities. Signed-off-by: pascal paillet --- .../devicetree/bindings/mfd/st,stpmu1.txt | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/st,stpmu1.txt diff --git a/Documentation/devicetree/bindings/mfd/st,stpmu1.txt b/Documentation/devicetree/bindings/mfd/st,stpmu1.txt new file mode 100644 index 0000000..53bdab4 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/st,stpmu1.txt @@ -0,0 +1,138 @@ +* STMicroelectronics STPMU1 Power Management IC + +Required parent device properties: +- compatible: "st,stpmu1" +- reg: the I2C slave address for the stpmu1 chip +- interrupts-extended: interrupt lines to use: second irq is for wakeup. +- #interrupt-cells: should be 2. +- interrupt-controller: describes the STPMU1 as an interrupt + controller (has its own domain). interrupt number are the following: + /* Interrupt Register 1 (0x50 for latch) */ + IT_SWOUT_R=0 + IT_SWOUT_F=1 + IT_VBUS_OTG_R=2 + IT_VBUS_OTG_F=3 + IT_WAKEUP_R=4 + IT_WAKEUP_F=5 + IT_PONKEY_R=6 + IT_PONKEY_F=7 + /* Interrupt Register 2 (0x51 for latch) */ + IT_OVP_BOOST=8 + IT_OCP_BOOST=9 + IT_OCP_SWOUT=10 + IT_OCP_OTG=11 + IT_CURLIM_BUCK4=12 + IT_CURLIM_BUCK3=13 + IT_CURLIM_BUCK2=14 + IT_CURLIM_BUCK1=15 + /* Interrupt Register 3 (0x52 for latch) */ + IT_SHORT_SWOUT=16 + IT_SHORT_SWOTG=17 + IT_CURLIM_LDO6=18 + IT_CURLIM_LDO5=19 + IT_CURLIM_LDO4=20 + IT_CURLIM_LDO3=21 + IT_CURLIM_LDO2=22 + IT_CURLIM_LDO1=23 + /* Interrupt Register 3 (0x52 for latch) */ + IT_SWIN_R=24 + IT_SWIN_F=25 + IT_RESERVED_1=26 + IT_RESERVED_2=27 + IT_VINLOW_R=28 + IT_VINLOW_F=29 + IT_TWARN_R=30 + IT_TWARN_F=31 + +Optional parent device properties: +- st,main_control_register: + -bit 1: Power cycling will be performed on turn OFF condition + -bit 2: PWRCTRL is functional + -bit 3: PWRCTRL active high +- st,pads_pull_register: + -bit 1: WAKEUP pull down is not active + -bit 2: PWRCTRL pull up is active + -bit 3: PWRCTRL pull down is active + -bit 4: WAKEUP detector is disabled +- st,vin_control_register: + -bit 0: VINLOW monitoring is enabled + -bit [1...3]: VINLOW rising threshold + 000 VINOK_f + 50mV + 001 VINOK_f + 100mV + 010 VINOK_f + 150mV + 011 VINOK_f + 200mV + 100 VINOK_f + 250mV + 101 VINOK_f + 300mV + 110 VINOK_f + 350mV + 111 VINOK_f + 400mV + -bit [4...5]: VINLOW hyst + 00 100mV + 01 200mV + 10 300mV + 11 400mV + -bit 6: SW_OUT detector is disabled + -bit 7: SW_IN detector is enabled. +- st,usb_control_register: + -bit 3: SW_OUT current limit + 0: 600mA + 1: 1.1A + -bit 4: VBUS_OTG discharge is enabled + -bit 5: SW_OUT discharge is enabled + -bit 6: VBUS_OTG detection is enabled + -bit 7: BOOST_OVP is disabled + + +stpmu1 consists is a varied group of sub-devices: + +Device Description +------ ------------ +stpmu1-onkey : On key +stpmu1-regulators : Regulators +stpmu1-wdt : Watchdog + +each sub-device bindings is be described in associated driver +documentation section. + +Example: + +pmic: stpmu1@33 { + compatible = "st,stpmu1"; + reg = <0x33>; + interrupts = <0 2>; + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_NONE>, + <&exti 55 1>; + st,version_status = <0x10>; + st,main_control_register=<0x0c>; + interrupt-controller; + #interrupt-cells = <2>; + onkey { + compatible = "st,stpmu1-onkey"; + interrupt-parent = <&pmic>; + interrupts = <7 0>,<6 1>; + st,onkey-pwroff-enabled; + st,onkey-press-seconds = <10>; + }; + + watchdog { + compatible = "st,stpmu1-wdt"; + }; + + regulators { + compatible = "st,stpmu1-regulators"; + + vdd_core: regulator@0 { + regulator-compatible = "buck1"; + regulator-name = "vdd_core"; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1200000>; + }; + vdd: regulator@1 { + regulator-compatible = "buck3"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-pull-down; + }; + }; From patchwork Thu Jul 5 15:14:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pascal PAILLET-LME X-Patchwork-Id: 939988 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41M1f943v7z9s3C for ; Fri, 6 Jul 2018 01:16:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754040AbeGEPPp convert rfc822-to-8bit (ORCPT ); Thu, 5 Jul 2018 11:15:45 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:53306 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754329AbeGEPOw (ORCPT ); Thu, 5 Jul 2018 11:14:52 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w65F9PVt022966; Thu, 5 Jul 2018 17:14:24 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2k0dnr1ucu-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 05 Jul 2018 17:14:24 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8D6C038; Thu, 5 Jul 2018 15:14:23 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4FCE626D4; Thu, 5 Jul 2018 15:14:23 +0000 (GMT) Received: from SFHDAG6NODE2.st.com (10.75.127.17) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 5 Jul 2018 17:14:22 +0200 Received: from SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6]) by SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6%20]) with mapi id 15.00.1347.000; Thu, 5 Jul 2018 17:14:22 +0200 From: Pascal PAILLET-LME To: "dmitry.torokhov@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "lee.jones@linaro.org" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "wim@linux-watchdog.org" , "linux@roeck-us.net" , "linux-input@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-watchdog@vger.kernel.org" , "benjamin.gaignard@linaro.org" CC: Pascal PAILLET-LME Subject: [PATCH 2/8] mfd: stpmu1: add stpmu1 pmic driver Thread-Topic: [PATCH 2/8] mfd: stpmu1: add stpmu1 pmic driver Thread-Index: AQHUFHLaKOnksVxEZUKN7td2/IYexg== Date: Thu, 5 Jul 2018 15:14:22 +0000 Message-ID: <1530803657-17684-3-git-send-email-p.paillet@st.com> References: <1530803657-17684-1-git-send-email-p.paillet@st.com> In-Reply-To: <1530803657-17684-1-git-send-email-p.paillet@st.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-05_05:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: pascal paillet stpmu1 is a pmic from STMicroelectronics. The stpmu1 integrates 10 regulators and 3 switches with various capabilities. Signed-off-by: pascal paillet --- drivers/mfd/Kconfig | 14 ++ drivers/mfd/Makefile | 1 + drivers/mfd/stpmu1.c | 490 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/mfd/st,stpmu1.h | 46 ++++ include/linux/mfd/stpmu1.h | 220 ++++++++++++++++ 5 files changed, 771 insertions(+) create mode 100644 drivers/mfd/stpmu1.c create mode 100644 include/dt-bindings/mfd/st,stpmu1.h create mode 100644 include/linux/mfd/stpmu1.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b860eb5..e15140b 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1812,6 +1812,20 @@ config MFD_STM32_TIMERS for PWM and IIO Timer. This driver allow to share the registers between the others drivers. +config MFD_STPMU1 + tristate "Support for STPMU1 PMIC" + depends on (I2C=y && OF) + select REGMAP_I2C + select REGMAP_IRQ + select MFD_CORE + help + Support for ST Microelectronics STPMU1 PMIC. Stpmu1 mfd driver is + the core driver for stpmu1 component that mainly handles interrupts. + + To compile this driver as a module, choose M here: the + module will be called stpmu1. + + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e9fd20d..f1c4be1 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -220,6 +220,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o obj-$(CONFIG_MFD_MT6397) += mt6397-core.o obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o +obj-$(CONFIG_MFD_STPMU1) += stpmu1.o obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o diff --git a/drivers/mfd/stpmu1.c b/drivers/mfd/stpmu1.c new file mode 100644 index 0000000..a284a3e --- /dev/null +++ b/drivers/mfd/stpmu1.c @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Philippe Peurichard , + * Pascal Paillet for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static bool stpmu1_reg_readable(struct device *dev, unsigned int reg); +static bool stpmu1_reg_writeable(struct device *dev, unsigned int reg); +static bool stpmu1_reg_volatile(struct device *dev, unsigned int reg); + +const struct regmap_config stpmu1_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .max_register = PMIC_MAX_REGISTER_ADDRESS, + .readable_reg = stpmu1_reg_readable, + .writeable_reg = stpmu1_reg_writeable, + .volatile_reg = stpmu1_reg_volatile, +}; + +#define FILL_IRQS(_index) \ + [(_index)] = { \ + .reg_offset = ((_index) >> 3), \ + .mask = (1 << (_index % 8)), \ + } + +static const struct regmap_irq stpmu1_irqs[] = { + FILL_IRQS(IT_PONKEY_F), + FILL_IRQS(IT_PONKEY_R), + FILL_IRQS(IT_WAKEUP_F), + FILL_IRQS(IT_WAKEUP_R), + FILL_IRQS(IT_VBUS_OTG_F), + FILL_IRQS(IT_VBUS_OTG_R), + FILL_IRQS(IT_SWOUT_F), + FILL_IRQS(IT_SWOUT_R), + + FILL_IRQS(IT_CURLIM_BUCK1), + FILL_IRQS(IT_CURLIM_BUCK2), + FILL_IRQS(IT_CURLIM_BUCK3), + FILL_IRQS(IT_CURLIM_BUCK4), + FILL_IRQS(IT_OCP_OTG), + FILL_IRQS(IT_OCP_SWOUT), + FILL_IRQS(IT_OCP_BOOST), + FILL_IRQS(IT_OVP_BOOST), + + FILL_IRQS(IT_CURLIM_LDO1), + FILL_IRQS(IT_CURLIM_LDO2), + FILL_IRQS(IT_CURLIM_LDO3), + FILL_IRQS(IT_CURLIM_LDO4), + FILL_IRQS(IT_CURLIM_LDO5), + FILL_IRQS(IT_CURLIM_LDO6), + FILL_IRQS(IT_SHORT_SWOTG), + FILL_IRQS(IT_SHORT_SWOUT), + + FILL_IRQS(IT_TWARN_F), + FILL_IRQS(IT_TWARN_R), + FILL_IRQS(IT_VINLOW_F), + FILL_IRQS(IT_VINLOW_R), + FILL_IRQS(IT_SWIN_F), + FILL_IRQS(IT_SWIN_R), +}; + +static const struct regmap_irq_chip stpmu1_regmap_irq_chip = { + .name = "pmic_irq", + .status_base = INT_PENDING_R1, + .mask_base = INT_CLEAR_MASK_R1, + .unmask_base = INT_SET_MASK_R1, + .ack_base = INT_CLEAR_R1, + .num_regs = STPMU1_PMIC_NUM_IRQ_REGS, + .irqs = stpmu1_irqs, + .num_irqs = ARRAY_SIZE(stpmu1_irqs), +}; + +static bool stpmu1_reg_readable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case TURN_ON_SR: + case TURN_OFF_SR: + case ICC_LDO_TURN_OFF_SR: + case ICC_BUCK_TURN_OFF_SR: + case RREQ_STATE_SR: + case VERSION_SR: + case SWOFF_PWRCTRL_CR: + case PADS_PULL_CR: + case BUCKS_PD_CR: + case LDO14_PD_CR: + case LDO56_VREF_PD_CR: + case VBUS_DET_VIN_CR: + case PKEY_TURNOFF_CR: + case BUCKS_MASK_RANK_CR: + case BUCKS_MASK_RESET_CR: + case LDOS_MASK_RANK_CR: + case LDOS_MASK_RESET_CR: + case WCHDG_CR: + case WCHDG_TIMER_CR: + case BUCKS_ICCTO_CR: + case LDOS_ICCTO_CR: + case BUCK1_ACTIVE_CR: + case BUCK2_ACTIVE_CR: + case BUCK3_ACTIVE_CR: + case BUCK4_ACTIVE_CR: + case VREF_DDR_ACTIVE_CR: + case LDO1_ACTIVE_CR: + case LDO2_ACTIVE_CR: + case LDO3_ACTIVE_CR: + case LDO4_ACTIVE_CR: + case LDO5_ACTIVE_CR: + case LDO6_ACTIVE_CR: + case BUCK1_STDBY_CR: + case BUCK2_STDBY_CR: + case BUCK3_STDBY_CR: + case BUCK4_STDBY_CR: + case VREF_DDR_STDBY_CR: + case LDO1_STDBY_CR: + case LDO2_STDBY_CR: + case LDO3_STDBY_CR: + case LDO4_STDBY_CR: + case LDO5_STDBY_CR: + case LDO6_STDBY_CR: + case BST_SW_CR: + case INT_PENDING_R1: + case INT_PENDING_R2: + case INT_PENDING_R3: + case INT_PENDING_R4: + case INT_DBG_LATCH_R1: + case INT_DBG_LATCH_R2: + case INT_DBG_LATCH_R3: + case INT_DBG_LATCH_R4: + case INT_CLEAR_R1: + case INT_CLEAR_R2: + case INT_CLEAR_R3: + case INT_CLEAR_R4: + case INT_MASK_R1: + case INT_MASK_R2: + case INT_MASK_R3: + case INT_MASK_R4: + case INT_SET_MASK_R1: + case INT_SET_MASK_R2: + case INT_SET_MASK_R3: + case INT_SET_MASK_R4: + case INT_CLEAR_MASK_R1: + case INT_CLEAR_MASK_R2: + case INT_CLEAR_MASK_R3: + case INT_CLEAR_MASK_R4: + case INT_SRC_R1: + case INT_SRC_R2: + case INT_SRC_R3: + case INT_SRC_R4: + return true; + default: + return false; + } +} + +static bool stpmu1_reg_writeable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SWOFF_PWRCTRL_CR: + case PADS_PULL_CR: + case BUCKS_PD_CR: + case LDO14_PD_CR: + case LDO56_VREF_PD_CR: + case VBUS_DET_VIN_CR: + case PKEY_TURNOFF_CR: + case BUCKS_MASK_RANK_CR: + case BUCKS_MASK_RESET_CR: + case LDOS_MASK_RANK_CR: + case LDOS_MASK_RESET_CR: + case WCHDG_CR: + case WCHDG_TIMER_CR: + case BUCKS_ICCTO_CR: + case LDOS_ICCTO_CR: + case BUCK1_ACTIVE_CR: + case BUCK2_ACTIVE_CR: + case BUCK3_ACTIVE_CR: + case BUCK4_ACTIVE_CR: + case VREF_DDR_ACTIVE_CR: + case LDO1_ACTIVE_CR: + case LDO2_ACTIVE_CR: + case LDO3_ACTIVE_CR: + case LDO4_ACTIVE_CR: + case LDO5_ACTIVE_CR: + case LDO6_ACTIVE_CR: + case BUCK1_STDBY_CR: + case BUCK2_STDBY_CR: + case BUCK3_STDBY_CR: + case BUCK4_STDBY_CR: + case VREF_DDR_STDBY_CR: + case LDO1_STDBY_CR: + case LDO2_STDBY_CR: + case LDO3_STDBY_CR: + case LDO4_STDBY_CR: + case LDO5_STDBY_CR: + case LDO6_STDBY_CR: + case BST_SW_CR: + case INT_DBG_LATCH_R1: + case INT_DBG_LATCH_R2: + case INT_DBG_LATCH_R3: + case INT_DBG_LATCH_R4: + case INT_CLEAR_R1: + case INT_CLEAR_R2: + case INT_CLEAR_R3: + case INT_CLEAR_R4: + case INT_SET_MASK_R1: + case INT_SET_MASK_R2: + case INT_SET_MASK_R3: + case INT_SET_MASK_R4: + case INT_CLEAR_MASK_R1: + case INT_CLEAR_MASK_R2: + case INT_CLEAR_MASK_R3: + case INT_CLEAR_MASK_R4: + return true; + default: + return false; + } +} + +static bool stpmu1_reg_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case TURN_ON_SR: + case TURN_OFF_SR: + case ICC_LDO_TURN_OFF_SR: + case ICC_BUCK_TURN_OFF_SR: + case RREQ_STATE_SR: + case INT_PENDING_R1: + case INT_PENDING_R2: + case INT_PENDING_R3: + case INT_PENDING_R4: + case INT_SRC_R1: + case INT_SRC_R2: + case INT_SRC_R3: + case INT_SRC_R4: + case WCHDG_CR: + return true; + default: + return false; + } +} + +static int stpmu1_configure_from_dt(struct stpmu1_dev *pmic_dev) +{ + struct device_node *np = pmic_dev->np; + u32 reg = 0; + int ret = 0; + int irq; + + irq = of_irq_get(np, 0); + if (irq <= 0) { + dev_err(pmic_dev->dev, + "Failed to get irq config: %d\n", irq); + return irq ? irq : -ENODEV; + } + pmic_dev->irq = irq; + + irq = of_irq_get(np, 1); + if (irq <= 0) { + dev_err(pmic_dev->dev, + "Failed to get irq_wake config: %d\n", irq); + return irq ? irq : -ENODEV; + } + pmic_dev->irq_wake = irq; + + device_init_wakeup(pmic_dev->dev, true); + ret = dev_pm_set_dedicated_wake_irq(pmic_dev->dev, pmic_dev->irq_wake); + if (ret) + dev_warn(pmic_dev->dev, "failed to set up wakeup irq"); + + if (!of_property_read_u32(np, "st,main_control_register", ®)) { + ret = regmap_update_bits(pmic_dev->regmap, + SWOFF_PWRCTRL_CR, + PWRCTRL_POLARITY_HIGH | + PWRCTRL_PIN_VALID | + RESTART_REQUEST_ENABLED, + reg); + if (ret) { + dev_err(pmic_dev->dev, + "Failed to update main control register: %d\n", + ret); + return ret; + } + } + + if (!of_property_read_u32(np, "st,pads_pull_register", ®)) { + ret = regmap_update_bits(pmic_dev->regmap, + PADS_PULL_CR, + WAKEUP_DETECTOR_DISABLED | + PWRCTRL_PD_ACTIVE | + PWRCTRL_PU_ACTIVE | + WAKEUP_PD_ACTIVE, + reg); + if (ret) { + dev_err(pmic_dev->dev, + "Failed to update pads control register: %d\n", + ret); + return ret; + } + } + + if (!of_property_read_u32(np, "st,vin_control_register", ®)) { + ret = regmap_update_bits(pmic_dev->regmap, + VBUS_DET_VIN_CR, + VINLOW_CTRL_REG_MASK, + reg); + if (ret) { + dev_err(pmic_dev->dev, + "Failed to update vin control register: %d\n", + ret); + return ret; + } + } + + if (!of_property_read_u32(np, "st,usb_control_register", ®)) { + ret = regmap_update_bits(pmic_dev->regmap, BST_SW_CR, + BOOST_OVP_DISABLED | + VBUS_OTG_DETECTION_DISABLED | + SW_OUT_DISCHARGE | + VBUS_OTG_DISCHARGE | + OCP_LIMIT_HIGH, + reg); + if (ret) { + dev_err(pmic_dev->dev, + "Failed to update usb control register: %d\n", + ret); + return ret; + } + } + + return 0; +} + +int stpmu1_device_init(struct stpmu1_dev *pmic_dev) +{ + int ret; + unsigned int val; + + pmic_dev->regmap = + devm_regmap_init_i2c(pmic_dev->i2c, &stpmu1_regmap_config); + + if (IS_ERR(pmic_dev->regmap)) { + ret = PTR_ERR(pmic_dev->regmap); + dev_err(pmic_dev->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + ret = stpmu1_configure_from_dt(pmic_dev); + if (ret < 0) { + dev_err(pmic_dev->dev, + "Unable to configure PMIC from Device Tree: %d\n", ret); + return ret; + } + + /* Read Version ID */ + ret = regmap_read(pmic_dev->regmap, VERSION_SR, &val); + if (ret < 0) { + dev_err(pmic_dev->dev, "Unable to read pmic version\n"); + return ret; + } + dev_dbg(pmic_dev->dev, "PMIC Chip Version: 0x%x\n", val); + + /* Initialize PMIC IRQ Chip & IRQ domains associated */ + ret = devm_regmap_add_irq_chip(pmic_dev->dev, pmic_dev->regmap, + pmic_dev->irq, + IRQF_ONESHOT | IRQF_SHARED, + 0, &stpmu1_regmap_irq_chip, + &pmic_dev->irq_data); + if (ret < 0) { + dev_err(pmic_dev->dev, "IRQ Chip registration failed: %d\n", + ret); + return ret; + } + + return 0; +} + +static const struct of_device_id stpmu1_dt_match[] = { + {.compatible = "st,stpmu1"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, stpmu1_dt_match); + +static int stpmu1_remove(struct i2c_client *i2c) +{ + struct stpmu1_dev *pmic_dev = i2c_get_clientdata(i2c); + + of_platform_depopulate(pmic_dev->dev); + + return 0; +} + +static int stpmu1_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct stpmu1_dev *pmic; + struct device *dev = &i2c->dev; + int ret = 0; + + pmic = devm_kzalloc(dev, sizeof(struct stpmu1_dev), GFP_KERNEL); + if (!pmic) + return -ENOMEM; + + pmic->np = dev->of_node; + + dev_set_drvdata(dev, pmic); + pmic->dev = dev; + pmic->i2c = i2c; + + ret = stpmu1_device_init(pmic); + if (ret < 0) + goto err; + + ret = of_platform_populate(pmic->np, NULL, NULL, pmic->dev); + + dev_dbg(dev, "stpmu1 driver probed\n"); +err: + return ret; +} + +static const struct i2c_device_id stpmu1_id[] = { + {"stpmu1", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, stpmu1_id); + +#ifdef CONFIG_PM_SLEEP +static int stpmu1_suspend(struct device *dev) +{ + struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); + struct stpmu1_dev *pmic_dev = i2c_get_clientdata(i2c); + + if (device_may_wakeup(dev)) + enable_irq_wake(pmic_dev->irq_wake); + + disable_irq(pmic_dev->irq); + return 0; +} + +static int stpmu1_resume(struct device *dev) +{ + struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); + struct stpmu1_dev *pmic_dev = i2c_get_clientdata(i2c); + + regcache_sync(pmic_dev->regmap); + + if (device_may_wakeup(dev)) + disable_irq_wake(pmic_dev->irq_wake); + + enable_irq(pmic_dev->irq); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(stpmu1_pm, stpmu1_suspend, stpmu1_resume); + +static struct i2c_driver stpmu1_driver = { + .driver = { + .name = "stpmu1", + .owner = THIS_MODULE, + .pm = &stpmu1_pm, + .of_match_table = of_match_ptr(stpmu1_dt_match), + }, + .probe = stpmu1_probe, + .remove = stpmu1_remove, + .id_table = stpmu1_id, +}; + +module_i2c_driver(stpmu1_driver); + +MODULE_DESCRIPTION("STPMU1 PMIC I2C Client"); +MODULE_AUTHOR(""); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/mfd/st,stpmu1.h b/include/dt-bindings/mfd/st,stpmu1.h new file mode 100644 index 0000000..2d3bdf1 --- /dev/null +++ b/include/dt-bindings/mfd/st,stpmu1.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Philippe Peurichard , + * Pascal Paillet for STMicroelectronics. + */ + +#ifndef __DT_BINDINGS_STPMU1_H__ +#define __DT_BINDINGS_STPMU1_H__ + +/* IRQ definitions */ +#define IT_PONKEY_F 0 +#define IT_PONKEY_R 1 +#define IT_WAKEUP_F 2 +#define IT_WAKEUP_R 3 +#define IT_VBUS_OTG_F 4 +#define IT_VBUS_OTG_R 5 +#define IT_SWOUT_F 6 +#define IT_SWOUT_R 7 + +#define IT_CURLIM_BUCK1 8 +#define IT_CURLIM_BUCK2 9 +#define IT_CURLIM_BUCK3 10 +#define IT_CURLIM_BUCK4 11 +#define IT_OCP_OTG 12 +#define IT_OCP_SWOUT 13 +#define IT_OCP_BOOST 14 +#define IT_OVP_BOOST 15 + +#define IT_CURLIM_LDO1 16 +#define IT_CURLIM_LDO2 17 +#define IT_CURLIM_LDO3 18 +#define IT_CURLIM_LDO4 19 +#define IT_CURLIM_LDO5 20 +#define IT_CURLIM_LDO6 21 +#define IT_SHORT_SWOTG 22 +#define IT_SHORT_SWOUT 23 + +#define IT_TWARN_F 24 +#define IT_TWARN_R 25 +#define IT_VINLOW_F 26 +#define IT_VINLOW_R 27 +#define IT_SWIN_F 30 +#define IT_SWIN_R 31 + +#endif /* __DT_BINDINGS_STPMU1_H__ */ diff --git a/include/linux/mfd/stpmu1.h b/include/linux/mfd/stpmu1.h new file mode 100644 index 0000000..05fd029 --- /dev/null +++ b/include/linux/mfd/stpmu1.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Philippe Peurichard , + * Pascal Paillet for STMicroelectronics. + */ + +#ifndef __LINUX_MFD_STPMU1_H +#define __LINUX_MFD_STPMU1_H + +#define TURN_ON_SR 0x1 +#define TURN_OFF_SR 0x2 +#define ICC_LDO_TURN_OFF_SR 0x3 +#define ICC_BUCK_TURN_OFF_SR 0x4 +#define RREQ_STATE_SR 0x5 +#define VERSION_SR 0x6 + +#define SWOFF_PWRCTRL_CR 0x10 +#define PADS_PULL_CR 0x11 +#define BUCKS_PD_CR 0x12 +#define LDO14_PD_CR 0x13 +#define LDO56_VREF_PD_CR 0x14 +#define VBUS_DET_VIN_CR 0x15 +#define PKEY_TURNOFF_CR 0x16 +#define BUCKS_MASK_RANK_CR 0x17 +#define BUCKS_MASK_RESET_CR 0x18 +#define LDOS_MASK_RANK_CR 0x19 +#define LDOS_MASK_RESET_CR 0x1A +#define WCHDG_CR 0x1B +#define WCHDG_TIMER_CR 0x1C +#define BUCKS_ICCTO_CR 0x1D +#define LDOS_ICCTO_CR 0x1E + +#define BUCK1_ACTIVE_CR 0x20 +#define BUCK2_ACTIVE_CR 0x21 +#define BUCK3_ACTIVE_CR 0x22 +#define BUCK4_ACTIVE_CR 0x23 +#define VREF_DDR_ACTIVE_CR 0x24 +#define LDO1_ACTIVE_CR 0x25 +#define LDO2_ACTIVE_CR 0x26 +#define LDO3_ACTIVE_CR 0x27 +#define LDO4_ACTIVE_CR 0x28 +#define LDO5_ACTIVE_CR 0x29 +#define LDO6_ACTIVE_CR 0x2A + +#define BUCK1_STDBY_CR 0x30 +#define BUCK2_STDBY_CR 0x31 +#define BUCK3_STDBY_CR 0x32 +#define BUCK4_STDBY_CR 0x33 +#define VREF_DDR_STDBY_CR 0x34 +#define LDO1_STDBY_CR 0x35 +#define LDO2_STDBY_CR 0x36 +#define LDO3_STDBY_CR 0x37 +#define LDO4_STDBY_CR 0x38 +#define LDO5_STDBY_CR 0x39 +#define LDO6_STDBY_CR 0x3A + +#define BST_SW_CR 0x40 + +#define INT_PENDING_R1 0x50 +#define INT_PENDING_R2 0x51 +#define INT_PENDING_R3 0x52 +#define INT_PENDING_R4 0x53 + +#define INT_DBG_LATCH_R1 0x60 +#define INT_DBG_LATCH_R2 0x61 +#define INT_DBG_LATCH_R3 0x62 +#define INT_DBG_LATCH_R4 0x63 + +#define INT_CLEAR_R1 0x70 +#define INT_CLEAR_R2 0x71 +#define INT_CLEAR_R3 0x72 +#define INT_CLEAR_R4 0x73 + +#define INT_MASK_R1 0x80 +#define INT_MASK_R2 0x81 +#define INT_MASK_R3 0x82 +#define INT_MASK_R4 0x83 + +#define INT_SET_MASK_R1 0x90 +#define INT_SET_MASK_R2 0x91 +#define INT_SET_MASK_R3 0x92 +#define INT_SET_MASK_R4 0x93 + +#define INT_CLEAR_MASK_R1 0xA0 +#define INT_CLEAR_MASK_R2 0xA1 +#define INT_CLEAR_MASK_R3 0xA2 +#define INT_CLEAR_MASK_R4 0xA3 + +#define INT_SRC_R1 0xB0 +#define INT_SRC_R2 0xB1 +#define INT_SRC_R3 0xB2 +#define INT_SRC_R4 0xB3 + +#define PMIC_MAX_REGISTER_ADDRESS INT_SRC_R4 + +#define STPMU1_PMIC_NUM_IRQ_REGS 4 + +#define TURN_OFF_SR_ICC_EVENT 0x08 + +#define LDO_VOLTAGE_MASK GENMASK(6, 2) +#define BUCK_VOLTAGE_MASK GENMASK(7, 2) +#define LDO_BUCK_VOLTAGE_SHIFT 2 + +#define LDO_ENABLE_MASK BIT(0) +#define BUCK_ENABLE_MASK BIT(0) + +#define BUCK_HPLP_ENABLE_MASK BIT(1) +#define BUCK_HPLP_SHIFT 1 + +#define STDBY_ENABLE_MASK BIT(0) + +#define BUCKS_PD_CR_REG_MASK GENMASK(7, 0) +#define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0) +#define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0) +#define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0) +#define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0) +#define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0) +#define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0) + +#define BUCK1_PULL_DOWN_REG BUCKS_PD_CR +#define BUCK1_PULL_DOWN_MASK BIT(0) +#define BUCK2_PULL_DOWN_REG BUCKS_PD_CR +#define BUCK2_PULL_DOWN_MASK BIT(2) +#define BUCK3_PULL_DOWN_REG BUCKS_PD_CR +#define BUCK3_PULL_DOWN_MASK BIT(4) +#define BUCK4_PULL_DOWN_REG BUCKS_PD_CR +#define BUCK4_PULL_DOWN_MASK BIT(6) + +#define LDO1_PULL_DOWN_REG LDO14_PD_CR +#define LDO1_PULL_DOWN_MASK BIT(0) +#define LDO2_PULL_DOWN_REG LDO14_PD_CR +#define LDO2_PULL_DOWN_MASK BIT(2) +#define LDO3_PULL_DOWN_REG LDO14_PD_CR +#define LDO3_PULL_DOWN_MASK BIT(4) +#define LDO4_PULL_DOWN_REG LDO14_PD_CR +#define LDO4_PULL_DOWN_MASK BIT(6) +#define LDO5_PULL_DOWN_REG LDO56_VREF_PD_CR +#define LDO5_PULL_DOWN_MASK BIT(0) +#define LDO6_PULL_DOWN_REG LDO56_VREF_PD_CR +#define LDO6_PULL_DOWN_MASK BIT(2) +#define VREF_DDR_PULL_DOWN_REG LDO56_VREF_PD_CR +#define VREF_DDR_PULL_DOWN_MASK BIT(4) + +#define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0) +#define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0) + +#define LDO_BYPASS_MASK BIT(7) + +/* Main PMIC Control Register + * SWOFF_PWRCTRL_CR + * Address : 0x10 + */ +#define ICC_EVENT_ENABLED BIT(4) +#define PWRCTRL_POLARITY_HIGH BIT(3) +#define PWRCTRL_PIN_VALID BIT(2) +#define RESTART_REQUEST_ENABLED BIT(1) +#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) + +/* Main PMIC PADS Control Register + * PADS_PULL_CR + * Address : 0x11 + */ +#define WAKEUP_DETECTOR_DISABLED BIT(4) +#define PWRCTRL_PD_ACTIVE BIT(3) +#define PWRCTRL_PU_ACTIVE BIT(2) +#define WAKEUP_PD_ACTIVE BIT(1) +#define PONKEY_PU_ACTIVE BIT(0) + +/* Main PMIC VINLOW Control Register + * VBUS_DET_VIN_CRC DMSC + * Address : 0x15 + */ +#define SWIN_DETECTOR_ENABLED BIT(7) +#define SWOUT_DETECTOR_ENABLED BIT(6) +#define VINLOW_ENABLED BIT(0) +#define VINLOW_CTRL_REG_MASK GENMASK(7, 0) + +/* USB Control Register + * Address : 0x40 + */ +#define BOOST_OVP_DISABLED BIT(7) +#define VBUS_OTG_DETECTION_DISABLED BIT(6) +#define SW_OUT_DISCHARGE BIT(5) +#define VBUS_OTG_DISCHARGE BIT(4) +#define OCP_LIMIT_HIGH BIT(3) +#define SWIN_SWOUT_ENABLED BIT(2) +#define USBSW_OTG_SWITCH_ENABLED BIT(1) +#define BOOST_ENABLED BIT(0) + +/* PKEY_TURNOFF_CR + * Address : 0x16 + */ +#define PONKEY_PWR_OFF BIT(7) +#define PONKEY_CC_FLAG_CLEAR BIT(6) +#define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0) +#define PONKEY_TURNOFF_MASK GENMASK(7, 0) + +/* + * struct stpmu1_dev - stpmu1 master device for sub-drivers + * @dev: master device of the chip (can be used to access platform data) + * @i2c: i2c client private data for regulator + * @np: device DT node pointer + * @irq_base: base IRQ numbers + * @irq: generic IRQ number + * @irq_wake: wakeup IRQ number + * @regmap_irq_chip_data: irq chip data + */ +struct stpmu1_dev { + struct device *dev; + struct i2c_client *i2c; + struct regmap *regmap; + struct device_node *np; + unsigned int irq_base; + int irq; + int irq_wake; + struct regmap_irq_chip_data *irq_data; +}; + +#endif /* __LINUX_MFD_STPMU1_H */ From patchwork Thu Jul 5 15:14:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pascal PAILLET-LME X-Patchwork-Id: 939986 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; 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cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 05 Jul 2018 17:14:27 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DE6563A; Thu, 5 Jul 2018 15:14:23 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node1.st.com [10.75.127.16]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BC57126DC; Thu, 5 Jul 2018 15:14:23 +0000 (GMT) Received: from SFHDAG6NODE2.st.com (10.75.127.17) by SFHDAG6NODE1.st.com (10.75.127.16) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 5 Jul 2018 17:14:23 +0200 Received: from SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6]) by SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6%20]) with mapi id 15.00.1347.000; Thu, 5 Jul 2018 17:14:23 +0200 From: Pascal PAILLET-LME To: "dmitry.torokhov@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "lee.jones@linaro.org" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "wim@linux-watchdog.org" , "linux@roeck-us.net" , "linux-input@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-watchdog@vger.kernel.org" , "benjamin.gaignard@linaro.org" CC: Pascal PAILLET-LME Subject: [PATCH 3/8] dt-bindings: regulator: document stpmu1 pmic regulators Thread-Topic: [PATCH 3/8] dt-bindings: regulator: document stpmu1 pmic regulators Thread-Index: AQHUFHLawd6akLRFR0aIjrL33ybRIw== Date: Thu, 5 Jul 2018 15:14:23 +0000 Message-ID: <1530803657-17684-4-git-send-email-p.paillet@st.com> References: <1530803657-17684-1-git-send-email-p.paillet@st.com> In-Reply-To: <1530803657-17684-1-git-send-email-p.paillet@st.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-05_05:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: pascal paillet The STPMU1 regulators supply power to the application processor as well as to the external system peripherals such as DDR, Flash memories and system devices. Signed-off-by: pascal paillet --- .../bindings/regulator/st,stpmu1-regulator.txt | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/st,stpmu1-regulator.txt diff --git a/Documentation/devicetree/bindings/regulator/st,stpmu1-regulator.txt b/Documentation/devicetree/bindings/regulator/st,stpmu1-regulator.txt new file mode 100644 index 0000000..888e759 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/st,stpmu1-regulator.txt @@ -0,0 +1,72 @@ +STMicroelectronics STPMU1 Voltage regulators + +Regulator Nodes are optional depending on needs. + +Available Regulators in STPMU1 device are: + - buck1 for Buck BUCK1 + - buck2 for Buck BUCK2 + - buck3 for Buck BUCK3 + - buck4 for Buck BUCK4 + - ldo1 for LDO LDO1 + - ldo2 for LDO LDO2 + - ldo3 for LDO LDO3 + - ldo4 for LDO LDO4 + - ldo5 for LDO LDO5 + - ldo6 for LDO LDO6 + - vref_ddr for LDO Vref DDR + - boost for Buck BOOST + - pwr_sw1 for VBUS_OTG switch + - pwr_sw2 for SW_OUT switch + +Switches are fixed voltage regulators with only enable/disable capability. + +Optional properties: +- st,mask_reset: stay on during Reset for particular regulator +- regulator-pull-down: enable high pull down + if not specified light pull down is used +- regulator-over-current-protection: + if set, all regulators are switched off in case of over-current detection + on this regulator, + if not set, the driver only send an over-current event. +- interrupt-parent: phandle to the parent interrupt controller +- interrupts: index of current limit detection interrupt +- -supply: phandle to the parent supply/regulator node + each regulator supply can be described except vref_ddr. + +Example: +regulators { + compatible = "st,stpmu1-regulators"; + + ldo6-supply = <&v3v3>; + + vdd_core: regulator@0 { + regulator-compatible = "buck1"; + regulator-name = "vdd_core"; + interrupts = ; + interrupt-parent = <&pmic>; + st,mask_reset; + regulator-pull-down; + st,pulldown_config = <2>; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1200000>; + }; + + v3v3: buck4 { + regulator-compatible = "buck4"; + regulator-name = "v3v3"; + interrupts = ; + interrupt-parent = <&mypmic>; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + v1v8: ldo6 { + regulator-compatible = "ldo6"; + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-over-current-protection; + }; + +}; From patchwork Thu Jul 5 15:14:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pascal PAILLET-LME X-Patchwork-Id: 939990 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41M1gR3gntz9s2g for ; Fri, 6 Jul 2018 01:17:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754073AbeGEPQe convert rfc822-to-8bit (ORCPT ); Thu, 5 Jul 2018 11:16:34 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:15319 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754330AbeGEPOw (ORCPT ); Thu, 5 Jul 2018 11:14:52 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w65F9KNp017110; Thu, 5 Jul 2018 17:14:25 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2k1k1j0twv-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 05 Jul 2018 17:14:25 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DFA7B3D; Thu, 5 Jul 2018 15:14:24 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node2.st.com [10.75.127.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BE7AF26DF; Thu, 5 Jul 2018 15:14:24 +0000 (GMT) Received: from SFHDAG6NODE2.st.com (10.75.127.17) by SFHDAG6NODE2.st.com (10.75.127.17) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 5 Jul 2018 17:14:24 +0200 Received: from SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6]) by SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6%20]) with mapi id 15.00.1347.000; Thu, 5 Jul 2018 17:14:24 +0200 From: Pascal PAILLET-LME To: "dmitry.torokhov@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "lee.jones@linaro.org" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "wim@linux-watchdog.org" , "linux@roeck-us.net" , "linux-input@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-watchdog@vger.kernel.org" , "benjamin.gaignard@linaro.org" CC: Pascal PAILLET-LME Subject: [PATCH 5/8] dt-bindings: input: document stpmu1 pmic onkey Thread-Topic: [PATCH 5/8] dt-bindings: input: document stpmu1 pmic onkey Thread-Index: AQHUFHLbkAuWORwl9ECG4KcKZQv+TA== Date: Thu, 5 Jul 2018 15:14:24 +0000 Message-ID: <1530803657-17684-6-git-send-email-p.paillet@st.com> References: <1530803657-17684-1-git-send-email-p.paillet@st.com> In-Reply-To: <1530803657-17684-1-git-send-email-p.paillet@st.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-05_05:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: pascal paillet The stpmu1 pmic is able to manage an onkey button. It can be configured to shut-down the power supplies on a long key-press with an adjustable duration. Signed-off-by: pascal paillet --- .../devicetree/bindings/input/st,stpmu1-onkey.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/st,stpmu1-onkey.txt diff --git a/Documentation/devicetree/bindings/input/st,stpmu1-onkey.txt b/Documentation/devicetree/bindings/input/st,stpmu1-onkey.txt new file mode 100644 index 0000000..cc42b7f --- /dev/null +++ b/Documentation/devicetree/bindings/input/st,stpmu1-onkey.txt @@ -0,0 +1,31 @@ +STMicroelectronics STPMU1 Onkey + +Required properties: + +- compatible = "st,stpmu1-onkey"; +- interrupt-parent: phandle to the parent interrupt controller +- interrupts: interrupt line to use +- interrupt-names = "onkey-falling", "onkey-rising" + onkey-falling: happens when onkey is pressed; IT_PONKEY_F of pmic + onkey-rising: happens when onkey is released; IT_PONKEY_R of pmic + +Optional properties: + +- st,onkey-pwroff-enabled: power off on long key-press +- st,onkey-long-press-seconds: long key-press duration from 1 to 16s + (default 16s) +- st,onkey-clear-cc-flag: onkey is able power on after an + over-current shutdown event. +- st,onkey-pu-inactive: onkey pull up is not active + +Example: + +onkey { + compatible = "st,stpmu1-onkey"; + interrupt-parent = <&pmic>; + interrupts = <7 0>,<6 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + st,onkey-pwroff-enabled; + st,onkey-long-press-seconds = <10>; +}; From patchwork Thu Jul 5 15:14:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pascal PAILLET-LME X-Patchwork-Id: 939989 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41M1g30H57z9s1b for ; Fri, 6 Jul 2018 01:17:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932363AbeGEPQg convert rfc822-to-8bit (ORCPT ); Thu, 5 Jul 2018 11:16:36 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:44794 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754328AbeGEPOw (ORCPT ); Thu, 5 Jul 2018 11:14:52 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w65F9SIj022982; Thu, 5 Jul 2018 17:14:26 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2k0dnr1ud5-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 05 Jul 2018 17:14:26 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 04CBE34; Thu, 5 Jul 2018 15:14:25 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node2.st.com [10.75.127.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CEF7526DF; Thu, 5 Jul 2018 15:14:25 +0000 (GMT) Received: from SFHDAG6NODE2.st.com (10.75.127.17) by SFHDAG6NODE2.st.com (10.75.127.17) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 5 Jul 2018 17:14:25 +0200 Received: from SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6]) by SFHDAG6NODE2.st.com ([fe80::a56f:c186:bab7:13d6%20]) with mapi id 15.00.1347.000; Thu, 5 Jul 2018 17:14:25 +0200 From: Pascal PAILLET-LME To: "dmitry.torokhov@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "lee.jones@linaro.org" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "wim@linux-watchdog.org" , "linux@roeck-us.net" , "linux-input@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-watchdog@vger.kernel.org" , "benjamin.gaignard@linaro.org" CC: Pascal PAILLET-LME Subject: [PATCH 7/8] dt-bindings: watchdog: document stpmu1 pmic watchdog Thread-Topic: [PATCH 7/8] dt-bindings: watchdog: document stpmu1 pmic watchdog Thread-Index: AQHUFHLcRgC6tuoDo0WRb0mTcMYvJg== Date: Thu, 5 Jul 2018 15:14:25 +0000 Message-ID: <1530803657-17684-8-git-send-email-p.paillet@st.com> References: <1530803657-17684-1-git-send-email-p.paillet@st.com> In-Reply-To: <1530803657-17684-1-git-send-email-p.paillet@st.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-05_05:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: pascal paillet The stpmu1 PMIC embeds a watchdog which is disabled by default. In case of watchdog, the PMIC goes off. Signed-off-by: pascal paillet --- Documentation/devicetree/bindings/watchdog/st,stpmu1-wdt.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/st,stpmu1-wdt.txt diff --git a/Documentation/devicetree/bindings/watchdog/st,stpmu1-wdt.txt b/Documentation/devicetree/bindings/watchdog/st,stpmu1-wdt.txt new file mode 100644 index 0000000..b558b3c --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/st,stpmu1-wdt.txt @@ -0,0 +1,11 @@ +STMicroelectronics STPMU1 Watchdog + +Required properties: + +- compatible : should be "st,stpmu1-wdt" + +Example: + +watchdog { + compatible = "st,stpmu1-wdt"; +};