From patchwork Tue Jul 3 00:22:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 938287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-480878-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="KZbhOOE7"; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="bEe1ORyK"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41KPvx3ggSz9s3R for ; Tue, 3 Jul 2018 10:22:34 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=p+8bydpdEgYX 2BVRLsRtatqYqFYlsLlVkdB9lDpSKs/zktyU2LZeGW3tdoJYkxJAWRITYFb0J43v WYW3g6YYFOe0pVLoQwl6vSR6/v4ZwRoVPMd94cAvKRzcLxnyJPemQuIyT3xgdMlZ ojfro15InjiMXiGDcbQixKLMv1Dk+dk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=0awpdokdIU00aoIgxQ BWjn81riA=; b=KZbhOOE7p3n7ov6OnBvMMuUyb+pPg8PJb/wnOZbtiVZdD2fCX3 PI9yGi5m7P5UALr8b0yPiJ+HgeB9/TxMirhl53iaEZ7kLunLfEH8CLexSfh06s0h wrhyyOm+yKyBQSl1z2UHforwemKntuUDbRNqqQlMdx5Hyp4Ba5JS49jSM= Received: (qmail 115674 invoked by alias); 3 Jul 2018 00:22:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115659 invoked by uid 89); 3 Jul 2018 00:22:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=jim, HX-HELO:sk:mail-pl, H*r:sk:mail-pl X-HELO: mail-pl0-f46.google.com Received: from mail-pl0-f46.google.com (HELO mail-pl0-f46.google.com) (209.85.160.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Jul 2018 00:22:24 +0000 Received: by mail-pl0-f46.google.com with SMTP id 31-v6so104737plc.4 for ; Mon, 02 Jul 2018 17:22:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=0+iTAmNb9ylGtNeQQv0XtOGpo1QYpYQ3HFOZVFywFtk=; b=bEe1ORyKw5XAy5hIRJMWEy9xoMsWRLWg1b6k8d21A64WW46IcZ6K/ut+NoHKkBXhau /js/Jam8yWTtajZxgEfqrcl0IUvendoNn4/Rm6AWc1trY8T4LPW+smKoi6YV8qmaZwET j7l4KOeVmVdCzh3qcaecv4whLeYUHQr2HjOnQZR9v4E8EZgxX1hyo1M89KENyCOPQKtM 30ukZD5afQ0vm1OCnyIpseWKuVHy0ATmL9mIENSnqg/eMu+b9ixj9J7rGkZekjnc87dj 3+zMrxYsvLAAywVjB3Gbre8Vt7C8LazNBXAwU789OS+HLW5j/iT9fBqotmgg2r9mrjXG bkWQ== Received: from rohan.guest.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id p20-v6sm25287445pfn.181.2018.07.02.17.22.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 02 Jul 2018 17:22:21 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Fix interrupt support for -g. Date: Mon, 2 Jul 2018 17:22:14 -0700 Message-Id: <20180703002214.31628-1-jimw@sifive.com> This fixes a problem found by someone trying to use the new RISC-V interrupt attribute support. With a slightly non-trivial example, and the -g option, we get an abort in dwarf2cfi for an inconsistent CFI state. This is my fault for not making the new interrupt return patterns look enough like regular return patterns, which is simple to fix. Tested with cross riscv32-elf and riscv64-linux builds and tests. There were no regressions. The new testcase fails without the patch and works with the patch. Committed. Jim gcc/ * config/riscv/riscv.c (riscv_expand_epilogue): Use emit_jump_insn instead of emit_insn for interrupt returns. * config/riscv/riscv.md (riscv_met): Add (return) to rtl. (riscv_sret, riscv_uret): Likewise. gcc/testsuite/ * gcc.target/riscv/interrupt-debug.c: New. --- gcc/config/riscv/riscv.c | 6 +++--- gcc/config/riscv/riscv.md | 9 ++++++--- gcc/testsuite/gcc.target/riscv/interrupt-debug.c | 15 +++++++++++++++ 3 files changed, 24 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-debug.c diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 2709ebdd797..d87836f53f8 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3985,11 +3985,11 @@ riscv_expand_epilogue (int style) enum riscv_privilege_levels mode = cfun->machine->interrupt_mode; if (mode == MACHINE_MODE) - emit_insn (gen_riscv_mret ()); + emit_jump_insn (gen_riscv_mret ()); else if (mode == SUPERVISOR_MODE) - emit_insn (gen_riscv_sret ()); + emit_jump_insn (gen_riscv_sret ()); else - emit_insn (gen_riscv_uret ()); + emit_jump_insn (gen_riscv_uret ()); } else if (style != SIBCALL_RETURN) emit_jump_insn (gen_simple_return_internal (ra)); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 7b411f0538e..613af9d79e4 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2328,17 +2328,20 @@ "fsflags\t%0") (define_insn "riscv_mret" - [(unspec_volatile [(const_int 0)] UNSPECV_MRET)] + [(return) + (unspec_volatile [(const_int 0)] UNSPECV_MRET)] "" "mret") (define_insn "riscv_sret" - [(unspec_volatile [(const_int 0)] UNSPECV_SRET)] + [(return) + (unspec_volatile [(const_int 0)] UNSPECV_SRET)] "" "sret") (define_insn "riscv_uret" - [(unspec_volatile [(const_int 0)] UNSPECV_URET)] + [(return) + (unspec_volatile [(const_int 0)] UNSPECV_URET)] "" "uret") diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-debug.c b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c new file mode 100644 index 00000000000..a1b6dac8fbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c @@ -0,0 +1,15 @@ +/* Verify that we can compile with debug info. */ +/* { dg-do compile } */ +/* { dg-options "-Og -g" } */ +extern int var1; +extern int var2; +extern void sub2 (void); + +void __attribute__ ((interrupt)) +sub (void) +{ + if (var1) + var2 = 0; + else + sub2 (); +}