From patchwork Sat Jun 30 21:53:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 937481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-480802-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="qhtgd5V1"; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="blrwgYZa"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41J6jL0nQtz9rvt for ; Sun, 1 Jul 2018 07:53:55 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=bWAwGw987e4V WbSsN+oaOpVabrH63QZArJsS3UScZugoJi+CeKtacjCnVhAyI7gUi4o32hpzYvz/ cG/T+cQW3YEgboelmR8DIxwCqR2V26nghhjnKgaGbBGye70I4rDV2bwvAS9aDBy6 eMhdD3xxNjp4FrKwQYz0UcB3zAPnUSM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=925k2wRPlegNuSYmen YCYLs/qTs=; b=qhtgd5V1Lwf/EgvhUzLxDdhNjjfd1AQ8k/WMmecAXRGr6IeUW5 CN+Wvl4YrRV0Ke+XQLMEmgeukZumNSfRpsfRt/8i8dmVqRvpLFu0v3wmQfhbgHvc +A9DnYZJNzw4lZlIxXjcVdsjdnWKTv+ZEa2vfQ/ijgKTGVxJ9AwOwZvLI= Received: (qmail 92161 invoked by alias); 30 Jun 2018 21:53:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 92149 invoked by uid 89); 30 Jun 2018 21:53:46 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=bruce, Bruce, lp64, ilp32 X-HELO: mail-pl0-f52.google.com Received: from mail-pl0-f52.google.com (HELO mail-pl0-f52.google.com) (209.85.160.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 30 Jun 2018 21:53:44 +0000 Received: by mail-pl0-f52.google.com with SMTP id 31-v6so6126618plc.4 for ; Sat, 30 Jun 2018 14:53:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=TG/wUIiI+12CElqUOaqQOEnDB7qwzg787XyzLxCPi08=; b=blrwgYZaJUGv7/mbJQKnFejVGJ/YZ1YfncXSBrWpyxNxTpzoFZPdvCS9Qh4K1qE2aX I1aVAS8Hx9ZXllFzKYdWLw1YPMrJ0XQDFtnYS7AfehbeVDgedJse1brA+bUWERADyROs FwXnSEXt5auHsF12EttDtQUUPe4VzSe64DuL7SGTxsUXi3+l7HGpqK9qpo83gBEnvGbQ NbOuDy0BUDRDqExMSO5IpcMNwNNiedCXeUmuP5yYNvVA9w34DrMU/tOrfKnYe/mGMJXm 8VqpICz61pMxzr/gHNUOKdV87hgE3agtFfMEyA4wj88FhS7Q4Uh0fteDgW0jn5C0Gfxt vD+g== Received: from rohan.hsd1.ca.comcast.net ([2601:646:c103:8ec:cd63:61bc:bfe4:2bd6]) by smtp.gmail.com with ESMTPSA id n6-v6sm42765483pfk.36.2018.06.30.14.53.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 30 Jun 2018 14:53:41 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Add patterns to convert AND mask to two shifts. Date: Sat, 30 Jun 2018 14:53:37 -0700 Message-Id: <20180630215337.14058-1-jimw@sifive.com> This fixes a problem reported by Bruce Hoult on the RISC-V isa-dev mailing list. Given a testcase with two shifts, gcc canonicalizes to an AND with a mask, and then we get 3 instructions at the end when we should have two. This adds combiner patterns to convert AND mask back to two shifts when that is beneficial. I added 3 testcases to verify the optimization. This was tested with riscv64-linux native, and riscv32-elf cross. There were no regressions. Committed. Jim gcc/ * config/riscv/predicates.md (p2m1_shift_operand): New. (high_mask_shift_operand): New. * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): New combiner pattern using p2m1_shift_operand. (lshsi3_zero_extend_3+2): New combiner pattern using high_mask_shift_operand. gcc/testsuite/ * gcc.target/riscv/shift-shift-1.c: New. * gcc.target/riscv/shift-shift-2.c: New. * gcc.target/riscv/shift-shift-3.c: New. --- gcc/config/riscv/predicates.md | 20 ++++++++++++ gcc/config/riscv/riscv.md | 32 +++++++++++++++++++ .../gcc.target/riscv/shift-shift-1.c | 17 ++++++++++ .../gcc.target/riscv/shift-shift-2.c | 29 +++++++++++++++++ .../gcc.target/riscv/shift-shift-3.c | 18 +++++++++++ 5 files changed, 116 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-3.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index a2799d4cb98..cffc831bbc7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -71,6 +71,26 @@ return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op)); }) +(define_predicate "p2m1_shift_operand" + (match_code "const_int") +{ + int val = exact_log2 (INTVAL (op) + 1); + if (val < 12) + return false; + return true; + }) + +(define_predicate "high_mask_shift_operand" + (match_code "const_int") +{ + int val1 = clz_hwi (~ INTVAL (op)); + int val0 = ctz_hwi (INTVAL (op)); + if ((val0 + val1 == BITS_PER_WORD) + && val0 > 31 && val0 < 64) + return true; + return false; +}) + (define_predicate "move_operand" (match_operand 0 "general_operand") { diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index a5940dcc425..7b411f0538e 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1711,6 +1711,38 @@ [(set_attr "type" "shift") (set_attr "mode" "SI")]) +;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into +;; two logical shifts. Otherwise it requires 3 instructions: lui, +;; xor/addi/srli, and. +(define_split + [(set (match_operand:GPR 0 "register_operand") + (and:GPR (match_operand:GPR 1 "register_operand") + (match_operand:GPR 2 "p2m1_shift_operand")))] + "" + [(set (match_dup 0) + (ashift:GPR (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (lshiftrt:GPR (match_dup 0) (match_dup 2)))] +{ + operands[2] = GEN_INT (BITS_PER_WORD + - exact_log2 (INTVAL (operands[2]) + 1)); +}) + +;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros. This can be +;; split into two shifts. Otherwise it requires 3 instructions: li, sll, and. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "high_mask_shift_operand")))] + "TARGET_64BIT" + [(set (match_dup 0) + (lshiftrt:DI (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (ashift:DI (match_dup 0) (match_dup 2)))] +{ + operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2]))); +}) + ;; ;; .................... ;; diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-1.c b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c new file mode 100644 index 00000000000..a5343a31b14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -O" } */ + +/* Test for lshrsi3_zero_extend_3+1 pattern that uses p2m1_shift_operand. */ +unsigned int +sub1 (unsigned int i) +{ + return (i << 1) >> 1; +} + +unsigned int +sub2 (unsigned int i) +{ + return (i << 20) >> 20; +} +/* { dg-final { scan-assembler-times "slli" 2 } } */ +/* { dg-final { scan-assembler-times "srli" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c new file mode 100644 index 00000000000..3f07e7776e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */ + +/* Test for lshrsi3_zero_extend_3+1 pattern that uses p2m1_shift_operand. */ +unsigned int +sub1 (unsigned int i) +{ + return (i << 1) >> 1; +} + +unsigned int +sub2 (unsigned int i) +{ + return (i << 20) >> 20; +} + +unsigned long +sub3 (unsigned long i) +{ + return (i << 1) >> 1; +} + +unsigned long +sub4 (unsigned long i) +{ + return (i << 52) >> 52; +} +/* { dg-final { scan-assembler-times "slli" 4 } } */ +/* { dg-final { scan-assembler-times "srli" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-3.c b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c new file mode 100644 index 00000000000..c974e75b38a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */ + +/* Test for lshrsi3_zero_extend_3+2 pattern that uses + high_mask_shift_operand. */ +unsigned long +sub1 (unsigned long i) +{ + return (i >> 32) << 32; +} + +unsigned long +sub2 (unsigned long i) +{ + return (i >> 63) << 63; +} +/* { dg-final { scan-assembler-times "slli" 2 } } */ +/* { dg-final { scan-assembler-times "srli" 2 } } */