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d="scan'208";a="265916743" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa010.fm.intel.com with ESMTP; 02 Sep 2026 22:58:17 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 1/3] RISC-V: Allow RVV register overlap for vwmaccu.vx undef Date: Thu, 3 Sep 2026 13:54:45 +0800 Message-ID: <20260903055814.549187-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260903055814.549187-1-pan2.li@intel.com> References: <20260903055814.549187-1-pan2.li@intel.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Like vwmacc[u].vx, allow the rvv register overlap for the undef form of the dual widen ternary vx insn vwmaccu.vx. The undef form comes from the combine of the vec_duplicate and the vwmaccu.vv instead of the intrinsic. After that, all the dual widen ternary vx insns are able to overlap. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li --- gcc/config/riscv/vector.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index bbdbe8eddd1..e760f708faf 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -9181,24 +9181,24 @@ (define_expand "@pred_mul_plus_vx" }) (define_insn "*pred_widen_mul_plus_u_vx_undef" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vd") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 6 "vector_length_operand" " rvl") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "Wc1, vm") + (match_operand 6 "vector_length_operand" "rvl,rvl") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (zero_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " rJ"))) + (match_operand: 3 "register_operand" " rJ, rJ"))) (zero_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 5 "register_operand" " 0")) + (match_operand: 4 "register_operand" "Wvr,Wvr"))) + (match_operand:VWEXTI 5 "register_operand" " 0, 0")) (match_operand:VWEXTI 2 "vector_undef_operand")))] "TARGET_VECTOR" "vwmaccu.vx\t%0,%z3,%4%p1" From patchwork Thu Sep 3 05:54:46 2026 Content-Type: text/plain; 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d="scan'208";a="265916758" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa010.fm.intel.com with ESMTP; 02 Sep 2026 22:58:20 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 2/3] RISC-V: Add test cases for vwmaccu.vx undef reg overlap Date: Thu, 3 Sep 2026 13:54:46 +0800 Message-ID: <20260903055814.549187-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260903055814.549187-1-pan2.li@intel.com> References: <20260903055814.549187-1-pan2.li@intel.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c: New test. Signed-off-by: Pan Li --- .../group_overlap/vwmaccu_vx_undef-u16-m1.c | 21 ++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u16-m2.c | 23 +++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u16-m4.c | 26 +++++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u16-mf2.c | 19 ++++++++++++ .../group_overlap/vwmaccu_vx_undef-u16-mf4.c | 19 ++++++++++++ .../group_overlap/vwmaccu_vx_undef-u32-m1.c | 21 ++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u32-m2.c | 21 ++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u32-m4.c | 23 +++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u32-mf2.c | 19 ++++++++++++ .../group_overlap/vwmaccu_vx_undef-u8-m1.c | 23 +++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u8-m2.c | 26 +++++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u8-m4.c | 29 +++++++++++++++++++ .../group_overlap/vwmaccu_vx_undef-u8-mf2.c | 19 ++++++++++++ .../group_overlap/vwmaccu_vx_undef-u8-mf4.c | 19 ++++++++++++ .../group_overlap/vwmaccu_vx_undef-u8-mf8.c | 19 ++++++++++++ 15 files changed, 327 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c new file mode 100644 index 00000000000..7c33fa79b8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x8_t __attribute__ ((vector_size (32))); +typedef unsigned int u32x4_t __attribute__ ((vector_size (16))); +typedef unsigned short u16x8_t __attribute__ ((vector_size (16))); + +u32x8_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x8_t acc, unsigned int x) +{ + u32x4_t hi = __builtin_shufflevector (acc, acc, 4, 5, 6, 7); + u16x8_t narrow = (u16x8_t) hi; + u32x8_t widen = __builtin_convertvector (narrow, u32x8_t); + unsigned int nx = x & 0xffff; + u32x8_t vx = { nx, nx, nx, nx, nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c new file mode 100644 index 00000000000..b7c6a4e5613 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x16_t __attribute__ ((vector_size (64))); +typedef unsigned int u32x8_t __attribute__ ((vector_size (32))); +typedef unsigned short u16x16_t __attribute__ ((vector_size (32))); + +u32x16_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x16_t acc, unsigned int x) +{ + u32x8_t hi = __builtin_shufflevector (acc, acc, 8, 9, 10, 11, 12, 13, 14, 15); + u16x16_t narrow = (u16x16_t) hi; + u32x16_t widen = __builtin_convertvector (narrow, u32x16_t); + unsigned int nx = x & 0xffff; + u32x16_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c new file mode 100644 index 00000000000..4bb61dc2fdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x32_t __attribute__ ((vector_size (128))); +typedef unsigned int u32x16_t __attribute__ ((vector_size (64))); +typedef unsigned short u16x32_t __attribute__ ((vector_size (64))); + +u32x32_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x32_t acc, unsigned int x) +{ + u32x16_t hi = __builtin_shufflevector ( + acc, acc, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); + u16x32_t narrow = (u16x32_t) hi; + u32x32_t widen = __builtin_convertvector (narrow, u32x32_t); + unsigned int nx = x & 0xffff; + u32x32_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c new file mode 100644 index 00000000000..ef80ef7fa4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x4_t __attribute__ ((vector_size (16))); +typedef unsigned short u16x4_t __attribute__ ((vector_size (8))); + +u32x4_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x4_t acc, u16x4_t narrow, + unsigned int x) +{ + u32x4_t widen = __builtin_convertvector (narrow, u32x4_t); + unsigned int nx = x & 0xffff; + u32x4_t vx = { nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c new file mode 100644 index 00000000000..08588d06215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x2_t __attribute__ ((vector_size (8))); +typedef unsigned short u16x2_t __attribute__ ((vector_size (4))); + +u32x2_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x2_t acc, u16x2_t narrow, + unsigned int x) +{ + u32x2_t widen = __builtin_convertvector (narrow, u32x2_t); + unsigned int nx = x & 0xffff; + u32x2_t vx = { nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c new file mode 100644 index 00000000000..af57bacc9a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x4_t __attribute__ ((vector_size (32))); +typedef unsigned long long u64x2_t __attribute__ ((vector_size (16))); +typedef unsigned int u32x4_t __attribute__ ((vector_size (16))); + +u64x4_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x4_t acc, unsigned long long x) +{ + u64x2_t hi = __builtin_shufflevector (acc, acc, 2, 3); + u32x4_t narrow = (u32x4_t) hi; + u64x4_t widen = __builtin_convertvector (narrow, u64x4_t); + unsigned long long nx = x & 0xffffffff; + u64x4_t vx = { nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c new file mode 100644 index 00000000000..3b106acad06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x8_t __attribute__ ((vector_size (64))); +typedef unsigned long long u64x4_t __attribute__ ((vector_size (32))); +typedef unsigned int u32x8_t __attribute__ ((vector_size (32))); + +u64x8_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x8_t acc, unsigned long long x) +{ + u64x4_t hi = __builtin_shufflevector (acc, acc, 4, 5, 6, 7); + u32x8_t narrow = (u32x8_t) hi; + u64x8_t widen = __builtin_convertvector (narrow, u64x8_t); + unsigned long long nx = x & 0xffffffff; + u64x8_t vx = { nx, nx, nx, nx, nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c new file mode 100644 index 00000000000..d3080a16aef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x16_t __attribute__ ((vector_size (128))); +typedef unsigned long long u64x8_t __attribute__ ((vector_size (64))); +typedef unsigned int u32x16_t __attribute__ ((vector_size (64))); + +u64x16_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x16_t acc, unsigned long long x) +{ + u64x8_t hi = __builtin_shufflevector (acc, acc, 8, 9, 10, 11, 12, 13, 14, 15); + u32x16_t narrow = (u32x16_t) hi; + u64x16_t widen = __builtin_convertvector (narrow, u64x16_t); + unsigned long long nx = x & 0xffffffff; + u64x16_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c new file mode 100644 index 00000000000..c41bff3e4e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x2_t __attribute__ ((vector_size (16))); +typedef unsigned int u32x2_t __attribute__ ((vector_size (8))); + +u64x2_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x2_t acc, u32x2_t narrow, + unsigned long long x) +{ + u64x2_t widen = __builtin_convertvector (narrow, u64x2_t); + unsigned long long nx = x & 0xffffffff; + u64x2_t vx = { nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c new file mode 100644 index 00000000000..799eefd7e6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x16_t __attribute__ ((vector_size (32))); +typedef unsigned short u16x8_t __attribute__ ((vector_size (16))); +typedef unsigned char u8x16_t __attribute__ ((vector_size (16))); + +u16x16_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x16_t acc, unsigned short x) +{ + u16x8_t hi = __builtin_shufflevector (acc, acc, 8, 9, 10, 11, 12, 13, 14, 15); + u8x16_t narrow = (u8x16_t) hi; + u16x16_t widen = __builtin_convertvector (narrow, u16x16_t); + unsigned short nx = x & 0xff; + u16x16_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c new file mode 100644 index 00000000000..094c680c6f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x32_t __attribute__ ((vector_size (64))); +typedef unsigned short u16x16_t __attribute__ ((vector_size (32))); +typedef unsigned char u8x32_t __attribute__ ((vector_size (32))); + +u16x32_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x32_t acc, unsigned short x) +{ + u16x16_t hi = __builtin_shufflevector ( + acc, acc, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); + u8x32_t narrow = (u8x32_t) hi; + u16x32_t widen = __builtin_convertvector (narrow, u16x32_t); + unsigned short nx = x & 0xff; + u16x32_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c new file mode 100644 index 00000000000..9fc3c20f597 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x64_t __attribute__ ((vector_size (128))); +typedef unsigned short u16x32_t __attribute__ ((vector_size (64))); +typedef unsigned char u8x64_t __attribute__ ((vector_size (64))); + +u16x64_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x64_t acc, unsigned short x) +{ + u16x32_t hi = __builtin_shufflevector ( + acc, acc, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63); + u8x64_t narrow = (u8x64_t) hi; + u16x64_t widen = __builtin_convertvector (narrow, u16x64_t); + unsigned short nx = x & 0xff; + u16x64_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c new file mode 100644 index 00000000000..c78fc378b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x8_t __attribute__ ((vector_size (16))); +typedef unsigned char u8x8_t __attribute__ ((vector_size (8))); + +u16x8_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x8_t acc, u8x8_t narrow, + unsigned short x) +{ + u16x8_t widen = __builtin_convertvector (narrow, u16x8_t); + unsigned short nx = x & 0xff; + u16x8_t vx = { nx, nx, nx, nx, nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c new file mode 100644 index 00000000000..e8f15f87950 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x4_t __attribute__ ((vector_size (8))); +typedef unsigned char u8x4_t __attribute__ ((vector_size (4))); + +u16x4_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x4_t acc, u8x4_t narrow, + unsigned short x) +{ + u16x4_t widen = __builtin_convertvector (narrow, u16x4_t); + unsigned short nx = x & 0xff; + u16x4_t vx = { nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c new file mode 100644 index 00000000000..1cacf5236f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x2_t __attribute__ ((vector_size (4))); +typedef unsigned char u8x2_t __attribute__ ((vector_size (2))); + +u16x2_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x2_t acc, u8x2_t narrow, + unsigned short x) +{ + u16x2_t widen = __builtin_convertvector (narrow, u16x2_t); + unsigned short nx = x & 0xff; + u16x2_t vx = { nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ From patchwork Thu Sep 3 05:54:47 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 2297272 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=gciRpKIQ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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d="scan'208";a="100045563" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2026 22:58:25 -0700 X-CSE-ConnectionGUID: 1Gu3ZMhaT2aJ5kBwTZAa7g== X-CSE-MsgGUID: O9FEF3xgT66UDQoQ4s4cdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,258,1779174000"; d="scan'208";a="265916767" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa010.fm.intel.com with ESMTP; 02 Sep 2026 22:58:22 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 3/3] RISC-V: Add more test cases for vwmaccu.vx undef Date: Thu, 3 Sep 2026 13:54:47 +0800 Message-ID: <20260903055814.549187-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260903055814.549187-1-pan2.li@intel.com> References: <20260903055814.549187-1-pan2.li@intel.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li For csrr not asm check when enable overlap enabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-59.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-59.c | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c new file mode 100644 index 00000000000..410b00c7004 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n, uint16_t x) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vuint32m4_t v0 = __riscv_vle32_v_u32m4 (in, 4);in+=100; + vuint16m2_t v0_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v0, 1)); + v0 = __riscv_vwmaccu_vx_u32m4_tu (v0, x, v0_n, 4); + asm volatile("nop" ::: "memory"); + vuint32m4_t v1 = __riscv_vle32_v_u32m4 (in, 4);in+=100; + vuint16m2_t v1_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v1, 1)); + v1 = __riscv_vwmaccu_vx_u32m4_tu (v1, x, v1_n, 4); + asm volatile("nop" ::: "memory"); + vuint32m4_t v2 = __riscv_vle32_v_u32m4 (in, 4);in+=100; + vuint16m2_t v2_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v2, 1)); + v2 = __riscv_vwmaccu_vx_u32m4_tu (v2, x, v2_n, 4); + asm volatile("nop" ::: "memory"); + vuint32m4_t v3 = __riscv_vle32_v_u32m4 (in, 4);in+=100; + vuint16m2_t v3_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v3, 1)); + v3 = __riscv_vwmaccu_vx_u32m4_tu (v3, x, v3_n, 4); + asm volatile("nop" ::: "memory"); + vuint32m4_t v4 = __riscv_vle32_v_u32m4 (in, 4);in+=100; + vuint16m2_t v4_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v4, 1)); + v4 = __riscv_vwmaccu_vx_u32m4_tu (v4, x, v4_n, 4); + asm volatile("nop" ::: "memory"); + vuint32m4_t v5 = __riscv_vle32_v_u32m4 (in, 4);in+=100; + vuint16m2_t v5_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v5, 1)); + v5 = __riscv_vwmaccu_vx_u32m4_tu (v5, x, v5_n, 4); + asm volatile("nop" ::: "memory"); + vuint32m4_t v6 = __riscv_vle32_v_u32m4 (in, 4);in+=100; + vuint16m2_t v6_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v6, 1)); + v6 = __riscv_vwmaccu_vx_u32m4_tu (v6, x, v6_n, 4); + asm volatile("nop" ::: "memory"); + vuint16m2_t v7_n = __riscv_vle16_v_u16m2 (in, 4);in+=100; + vuint32m4_t v7 = __riscv_vwcvtu_x_x_v_u32m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse32_v_u32m4 (out, 4, v0, 4);out+=100; + __riscv_vsse32_v_u32m4 (out, 4, v1, 4);out+=100; + __riscv_vsse32_v_u32m4 (out, 4, v2, 4);out+=100; + __riscv_vsse32_v_u32m4 (out, 4, v3, 4);out+=100; + __riscv_vsse32_v_u32m4 (out, 4, v4, 4);out+=100; + __riscv_vsse32_v_u32m4 (out, 4, v5, 4);out+=100; + __riscv_vsse32_v_u32m4 (out, 4, v6, 4);out+=100; + __riscv_vsse32_v_u32m4 (out, 4, v7, 4);out+=100; + } +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */