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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce5927b68sm62703165e9.1.2026.09.02.08.20.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 08:20:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , Pierrick Bouvier , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/11] target/arm: Call arm*_cpu_do_interrupt directly instead of via TCGCPUOps Date: Wed, 2 Sep 2026 17:20:32 +0200 Message-ID: <20260902152044.31291-2-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-GUID: nakIpAGURYwzqhIUeTTnY_D6Ui2G3u2W X-Authority-Analysis: v=2.4 cv=FeAHAp+6 c=1 sm=1 tr=0 ts=6a983eda cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=dCDxpQg89NXWVkCnum4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfX7M80SXKprfxq Lm3JUe3uU529jSRrQCj5m7k2HPPwQHUriJQdT4Kdbrp+L+hPB91hF6m+/r6d+5ZQj0577CA4lQK L81DmwjHyUtyyFcqzDRdsJ9SL8a5oMY= X-Proofpoint-ORIG-GUID: nakIpAGURYwzqhIUeTTnY_D6Ui2G3u2W X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfXx2R5fLAy7QTW aFPmGzyXyNdSd9xDl8cI840y+UynjU/uPdLU4tDRos8uG/K8gE/OeYQcP1k3jGbSTp5R/Qro0yG Fkc+fgAy092aXU0TG4Jk7mh9IxF2tQkjoUFa6TWEcTEpea4sW8dqsqvNGBCgNhWooU0Lg/6K22p XpRdAdSvvbCPbBp0WxELOMbe/AOWBTKqa97/rEKpZpv7n85vQFRpEVGpIdMAsgTmgUYWfrtmK5w YEXO8dhCCG7jFdpVqMnhr765Ei4R8dBFX2bUGtUcJ8HpcVLIW1PocwKFFArZJvvD/chTHlyzwvG YNcdrfJvBzyHEpDNJv2EGBNGNW/H6b6u2C/xjRxQ21BYNKpemWRwsHxgYyNOd/JatKgA/2/wgv9 9ir6YTXAtC6qk7LCMa0Bd/VBVP+kxmUkevo0ikpksuLopu/LXgnooE2qB/U8TQLSXe8tvYPOGaV /1cWBRCDQnYDlQ6fHOg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020135 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The TCGCPUOps.do_interrupt handler is a target-specific callback installed for use by target-agnostic TCG core methods. Target-specific code should not dispatch through this indirection; call the ARM implementation directly instead. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-irq.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-irq.c b/target/arm/cpu-irq.c index 883e8a176c3..e8a6520e5ca 100644 --- a/target/arm/cpu-irq.c +++ b/target/arm/cpu-irq.c @@ -270,7 +270,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) found: cs->exception_index = excp_idx; env->exception.target_el = target_el; - cs->cc->tcg_ops->do_interrupt(cs); + arm_cpu_do_interrupt(cs); return true; } #endif /* CONFIG_TCG */ diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 48b31d5eac8..502998dbd1c 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -34,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index = EXCP_IRQ; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/s390x/s390x-internal.h | 5 ++--- target/s390x/tcg/excp_helper.c | 5 ----- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 81da207a5f4..d302187c21d 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -261,9 +261,6 @@ ObjectClass *s390_cpu_class_by_name(const char *name); /* excp_helper.c */ -void s390_cpu_do_interrupt(CPUState *cpu); -bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); - #ifdef CONFIG_USER_ONLY void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, @@ -271,6 +268,8 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, void s390_cpu_record_sigbus(CPUState *cs, vaddr address, MMUAccessType access_type, uintptr_t retaddr); #else +void s390_cpu_do_interrupt(CPUState *cpu); +bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce58da3acsm127559305e9.0.2026.09.02.08.21.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 08:21:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , Pierrick Bouvier , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 03/11] target/i386: Rename fake_do_interrupt to fake_user_exception Date: Wed, 2 Sep 2026 17:20:34 +0200 Message-ID: <20260902152044.31291-4-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: eSSOjztxfKwokjNGF47KuFIX0UsTM-5k X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfXwhw5bJCrWStX q7jJEnsqduXFiMmdvFeka6qO9dx6L0yEg8KhDU+/dIDv3uDPZfgKVYZdLc520rxZq4+sPyNBx6X MuiPAuojrAXxmXE+M8aysLEshhqKrgsEWRWOqw8ll2HdesAG7ABS1Dr3yWR02LHIb8ozlXWenHK zDJXrlO9bbEZ9LcrSwukr2uyyjE63Dh71RagP2/nR0cSnO9j3fsoaZ8d/DNZ5VbVn9wbPW2pjuj mUwGixTI4Y9SiZMo+hv/tmXYs3sL/pbePs0ptMbJwDE+K3RNndmJtPfGNV4Knp9kzsy6gAq8K6u kKWBzt78ikLTy6HDIFxW1I/jVIW5EQ54b/0+FZog95lzuOtW451LDyGnAYO0OGB35onIXg7JpCb P7nY8gY37DUFa8+66jq9+GMJjpFFXe/alI3+CcBpGKDAtppFX0hrpv5RXvftZKzV6QW3JxCOqow LrWObenVgFEg9+FW+Tw== X-Proofpoint-GUID: eSSOjztxfKwokjNGF47KuFIX0UsTM-5k X-Authority-Analysis: v=2.4 cv=AufeGu9P c=1 sm=1 tr=0 ts=6a983ee9 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=QvbPrhRjooIPkqPMRvUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfXw5EpC/KehFqd uQrNbjZPsfLHXTXv7fTubXhl9v8VU5rBoHx2aDHwe464Ji/ttyvXJOP7bt1aIBdNU2pmUl/pibO Hc8/twr+xT8oQvASrrHRn/wPdIoUf7c= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 spamscore=0 adultscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020135 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The fake_user_exception hook handles exceptions in the outer exception loop (cpu_handle_exception), not inner loop interrupts (cpu_handle_interrupt). Rename to clarify the scope and intent. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 4 ++-- target/i386/tcg/helper-tcg.h | 4 +++- accel/tcg/cpu-exec.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 2 +- target/i386/tcg/user/seg_helper.c | 6 +++--- 5 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 3ff6e6810e0..ded7cc700df 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -106,12 +106,12 @@ struct TCGCPUOps { #ifdef CONFIG_USER_ONLY /** - * @fake_user_interrupt: Callback for 'fake exception' handling. + * @fake_user_exception: Callback for 'fake exception' handling. * * Simulate 'fake exception' which will be handled outside the * cpu execution loop (hack for x86 user mode). */ - void (*fake_user_interrupt)(CPUState *cpu); + void (*fake_user_exception)(CPUState *cpu); /** * record_sigsegv: diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index f4b2ff740d5..5349ab71be9 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -35,11 +35,13 @@ * x86_cpu_do_interrupt: * @cpu: vCPU the interrupt is to be handled by. */ -void x86_cpu_do_interrupt(CPUState *cpu); #ifndef CONFIG_USER_ONLY +void x86_cpu_do_interrupt(CPUState *cpu); bool x86_cpu_exec_halt(CPUState *cpu); bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); +#else +void x86_cpu_fake_user_exception(CPUState *cs); #endif void breakpoint_handler(CPUState *cs); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 257211235db..609931a0d6e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -717,8 +717,8 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) * handled outside the cpu execution loop. */ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - if (tcg_ops->fake_user_interrupt) { - tcg_ops->fake_user_interrupt(cpu); + if (tcg_ops->fake_user_exception) { + tcg_ops->fake_user_exception(cpu); } *ret = cpu->exception_index; cpu->exception_index = -1; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6f5dc06b3b9..7a4d73e7fee 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -173,7 +173,7 @@ const TCGCPUOps x86_tcg_ops = { .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, #ifdef CONFIG_USER_ONLY - .fake_user_interrupt = x86_cpu_do_interrupt, + .fake_user_exception = x86_cpu_fake_user_exception, .record_sigsegv = x86_cpu_record_sigsegv, .record_sigbus = x86_cpu_record_sigbus, #else diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_helper.c index 3a4a6d5a745..019a781458b 100644 --- a/target/i386/tcg/user/seg_helper.c +++ b/target/i386/tcg/user/seg_helper.c @@ -42,7 +42,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) * instruction. It is only relevant if is_int is TRUE or if intno * is EXCP_SYSCALL. */ -static void do_interrupt_user(CPUX86State *env, int intno, int is_int, +static void do_exception_user(CPUX86State *env, int intno, int is_int, int error_code, target_ulong next_eip) { if (is_int) { @@ -76,7 +76,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int, } } -void x86_cpu_do_interrupt(CPUState *cs) +void x86_cpu_fake_user_exception(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; @@ -84,7 +84,7 @@ void x86_cpu_do_interrupt(CPUState *cs) /* if user mode only, we simulate a fake exception which will be handled outside the cpu execution loop */ - do_interrupt_user(env, cs->exception_index, + do_exception_user(env, cs->exception_index, env->exception_is_int, env->error_code, env->exception_next_eip); From patchwork Wed Sep 2 15:20:35 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 2296785 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Fix typo in arm_cpu_exec_interrupt() documentation (s/inrerrupt/interrupt). Signed-off-by: Philippe Mathieu-Daudé --- include/accel/tcg/cpu-ops.h | 15 ++++++++++++++- target/arm/internals.h | 2 +- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index ded7cc700df..87850402203 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -171,8 +171,21 @@ struct TCGCPUOps { #else /** @do_interrupt: Callback for interrupt handling. */ void (*do_interrupt)(CPUState *cpu); - /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ + + /** + * @cpu_exec_interrupt: Callback for processing target-specific interrupts + * @cpu: cpu context + * @interrupt_request: Bitmask of pending interrupts + * + * Called from cpu_handle_interrupt() with the BQL held. Process the + * pending interrupt according to the target specific @interrupt_request + * masking rules. + * + * Returns: %true if an interrupt was processed and the next TB should + * be restarted, %false to continue normal execution. + */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @cpu_exec_reset: Callback for reset in cpu_exec. */ void (*cpu_exec_reset)(CPUState *cpu); /** diff --git a/target/arm/internals.h b/target/arm/internals.h index 1775835ad50..551a6b4a872 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1248,7 +1248,7 @@ static inline const char *aarch32_mode_name(uint32_t psr) } /** - * arm_cpu_exec_interrupt(): Implementation of the cpu_exec_inrerrupt hook. + * arm_cpu_exec_interrupt(): Implementation of the cpu_exec_interrupt hook. */ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request); From patchwork Wed Sep 2 15:20:36 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 2296796 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448e7f8f9sm7097056f8f.9.2026.09.02.08.21.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 08:21:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , Pierrick Bouvier , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 05/11] accel/tcg: Document do_interrupt() callback contract Date: Wed, 2 Sep 2026 17:20:36 +0200 Message-ID: <20260902152044.31291-6-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfXzwK8VfqhANX6 Ftch0W82acgInzQmbsAtVcniMkCRlgOKCPkGOgpsP2TdJCtGRZBt3r+w/DMvu19MlBeu7kxd4Yy DkN7tk9Rv7VfCGO9SstjCL8Z1YXKhls= X-Authority-Analysis: v=2.4 cv=G+ss1dk5 c=1 sm=1 tr=0 ts=6a983ef8 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=knkeNUhTHSQ0ZtdBXmcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: 8hQTQNlZTsIAohDAfPNeXAYQVrdZ6EiJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfXyBy1NX5fo6cA vB2F+pnv2+yR2lcrUnqZ2w6qAqEIfjWrRlNGQ7icU2md1MfJ7pxAnrl4Ce/ArAGFbG/6jt9FEhC IE3NPZIqRdzy5OZF7kHvlXuDiQW+B1LyCGXG9u7S2cbeJNCjNFAZoPmYU1cF2u5KlcavWaySzdA PdfX+NeKkmFluoax9qOfTC5Cmjq/yrR2mMltVnOd7xhksZ4tcXNGFrvkc9TOTRl2c+n0zfe0Cag I3xi/Z4n5jQboR4v1P7icDCFFtteR86p6zZMQWhN4qtclB5d2LKSAOfJ93GEa6WjwRX/gaV+s6W wEZQCRAGwwlJ/77xnzWYgknV8zuPEOuENPBWZ9jbjucyVM9SRJ69N97gyMlOqsyV2GsNaHfOTUk z1eiaaLR+Kqqzk9KsOU2++HGsxYEFyzNmcEyKAjIp9k2/Qd2Fbn8Tv+O8ORGnpa1yhlXNxvE0+5 o8c9fDmqf1KBsaz/5rA== X-Proofpoint-ORIG-GUID: 8hQTQNlZTsIAohDAfPNeXAYQVrdZ6EiJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020135 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Expand docstring to clarify the handler is called with BQL held. Add assertion that this callback is mandatory and never NULL, since all targets must implement interrupt handling. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 11 ++++++++++- accel/tcg/cpu-exec.c | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 87850402203..13df70eaa9f 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -169,7 +169,16 @@ struct TCGCPUOps { */ vaddr (*untagged_addr)(CPUState *cs, vaddr addr); #else - /** @do_interrupt: Callback for interrupt handling. */ + /** + * @do_interrupt: Deliver a pending exception/interrupt to the CPU + * @cpu: cpu context + * + * Called when cs->exception_index contains an exception code to deliver. + * Updates CPU architectural state (usually before executing a guest + * exception handler). + * + * Called from cpu_handle_exception() with BQL held. + */ void (*do_interrupt)(CPUState *cpu); /** diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 609931a0d6e..2fae2c024b8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1059,6 +1059,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); assert(tcg_ops->cpu_exec_reset); + assert(tcg_ops->do_interrupt); assert(tcg_ops->pointer_wrap); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); From patchwork Wed Sep 2 15:20:37 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 2296790 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=H6YrUhHj; dkim=pass (2048-bit key; unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=Ld2qXcYY; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce0b456sm178993705e9.2.2026.09.02.08.21.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 08:21:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , Pierrick Bouvier , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Robert Foley , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Michael Rolnik , Brian Cain , Helge Deller , Song Gao <17746591750@163.com>, Bibo Mao , Xianglai Li , Laurent Vivier , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Cornelia Huck , Eric Farman , Matthew Rosato , Ilya Leoshkevich , David Hildenbrand , Artyom Tarasenko , Max Filippov Subject: [PATCH v3 06/11] accel/tcg: Rename do_interrupt() to do_interrupt_locked() Date: Wed, 2 Sep 2026 17:20:37 +0200 Message-ID: <20260902152044.31291-7-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=H4/rBeYi c=1 sm=1 tr=0 ts=6a983f01 cx=c_pps a=KB4UBwrhAZV1kjiGHFQexw==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=KKAkSRfTAAAA:8 a=20KFwNOVAAAA:8 a=EUspDBNiAAAA:8 a=2r7OHPqeXRgJTkdu1hoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=o1xkdb1NAhiiM49bd1HK:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: oPfXHD4eYQ4_Le4EtfLdgkpZtkVZ2kNP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfXzAllyP//j8QA STJZ6IX8Ra4IGpWGcSaYLzzdgFoQtUifyObIViBKfOoW81cU3ud3Kl8i4OoQ5eEgIkf/ogOr3Vs 77hmiFiRc3aA5fvgkufsCCecupY1kxEUJKTaZXsgaOi0MIT+gChZPrykHDUhIfY/4XvqvLGMYe8 ZYdL9kArPxtwRz/oDt/n4loZ+ukLZCkgD9TGHel4yd2ChTL1edJ2NTeuwn6wqR6t7QnxJeTxPG+ LnYUjRN06PN1l2P3Aqf8U++CDyGukunWya99+6b+rB+8Qc3QtR1pIbOww9nrh/czALjC/QvCfxw JfJ2ok3UbRTzxrm0yyH5FgV1GGRs6uVmnWsNvRdjn5a8S9kZCFv2IVpIuWD1D1S/qKhOJYB9+st 1CGD27bwLZwPuXuQvGiyR0EvjobeMP91sciz5ynD3J06Ez0DRs2tVSb51kA1JAwlvkimALFE8Ph nVJTcozbcxoUlznWgnw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNSBTYWx0ZWRfXxgDVSTb6RImc 5EQq+Bc0OII41x5iw1BG/lmSvFB8WeWeYCbLQtH2NXrNmRtW6hsa9Vk+Ftm5M9WicS7XWKmLfPQ Jab23Dj/QUynTdNJUmag/kHjOVG4dIQ= X-Proofpoint-ORIG-GUID: oPfXHD4eYQ4_Le4EtfLdgkpZtkVZ2kNP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 clxscore=1015 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020135 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Robert Foley Prepare for pushing BQL locking down to per-target implementations. The old do_interrupt() name will later be reused for a wrapper that acquires BQL and calls do_interrupt_locked(), enabling targets to eventually remove BQL from the cpu_handle_interrupt/exception paths. Suggested-by: Paolo Bonzini Signed-off-by: Robert Foley [PMD: Rebased and reworded description] Signed-off-by: Philippe Mathieu-Daudé --- include/accel/tcg/cpu-ops.h | 4 ++-- accel/tcg/cpu-exec.c | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/tcg/tcg_cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/or1k/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 21 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 13df70eaa9f..2e97f79a373 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -170,7 +170,7 @@ struct TCGCPUOps { vaddr (*untagged_addr)(CPUState *cs, vaddr addr); #else /** - * @do_interrupt: Deliver a pending exception/interrupt to the CPU + * @do_interrupt_locked: Deliver a pending exception/interrupt to the CPU * @cpu: cpu context * * Called when cs->exception_index contains an exception code to deliver. @@ -179,7 +179,7 @@ struct TCGCPUOps { * * Called from cpu_handle_exception() with BQL held. */ - void (*do_interrupt)(CPUState *cpu); + void (*do_interrupt_locked)(CPUState *cpu); /** * @cpu_exec_interrupt: Callback for processing target-specific interrupts diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2fae2c024b8..8d9c203f222 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -728,7 +728,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; bql_lock(); - tcg_ops->do_interrupt(cpu); + tcg_ops->do_interrupt_locked(cpu); bql_unlock(); cpu->exception_index = -1; @@ -1059,7 +1059,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); assert(tcg_ops->cpu_exec_reset); - assert(tcg_ops->do_interrupt); + assert(tcg_ops->do_interrupt_locked); assert(tcg_ops->pointer_wrap); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 12e86021663..aca9e82bfb2 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -267,7 +267,7 @@ static const TCGCPUOps alpha_tcg_ops = { .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .cpu_exec_halt = alpha_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = alpha_cpu_do_interrupt, + .do_interrupt_locked = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, .do_unaligned_access = alpha_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 77aa78f00e2..0d0555b7ad4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2606,7 +2606,7 @@ static const TCGCPUOps arm_tcg_ops = { .cpu_exec_interrupt = arm_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .cpu_exec_reset = cpu_reset, - .do_interrupt = arm_cpu_do_interrupt, + .do_interrupt_locked = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, .adjust_watchpoint_address = arm_adjust_watchpoint_address, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 502998dbd1c..1f698b70283 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -304,7 +304,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .cpu_exec_reset = cpu_reset, - .do_interrupt = arm_v7m_cpu_do_interrupt, + .do_interrupt_locked = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, .adjust_watchpoint_address = arm_adjust_watchpoint_address, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f8409f32ab9..bc7639031b8 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -249,7 +249,7 @@ static const TCGCPUOps avr_tcg_ops = { .cpu_exec_halt = avr_cpu_has_work, .cpu_exec_reset = cpu_reset, .tlb_fill = avr_cpu_tlb_fill, - .do_interrupt = avr_cpu_do_interrupt, + .do_interrupt_locked = avr_cpu_do_interrupt, /* * TODO: code and data wrapping are different, but for the most part * AVR only references bytes or aligned code fetches. But we use diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 7067e5b70f7..b5dcbfc99db 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -769,7 +769,7 @@ static const TCGCPUOps hexagon_tcg_ops = { .tlb_fill = hexagon_tlb_fill, .do_unaligned_access = hexagon_cpu_do_unaligned_access, .cpu_exec_halt = hexagon_cpu_has_work, - .do_interrupt = hexagon_cpu_do_interrupt, + .do_interrupt_locked = hexagon_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 07b49e51326..c6d915d314f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -272,7 +272,7 @@ static const TCGCPUOps hppa_tcg_ops = { .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .cpu_exec_halt = hppa_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = hppa_cpu_do_interrupt, + .do_interrupt_locked = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, .do_transaction_failed = hppa_cpu_do_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 7a4d73e7fee..ff65641654d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -179,7 +179,7 @@ const TCGCPUOps x86_tcg_ops = { #else .tlb_fill = x86_cpu_tlb_fill, .pointer_wrap = x86_pointer_wrap, - .do_interrupt = x86_cpu_do_interrupt, + .do_interrupt_locked = x86_cpu_do_interrupt, .cpu_exec_halt = x86_cpu_exec_halt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .cpu_exec_reset = x86_cpu_exec_reset, diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 4b1d44a1644..6455ae0c99a 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -329,7 +329,7 @@ const TCGCPUOps loongarch_tcg_ops = { .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, .cpu_exec_halt = loongarch_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = loongarch_cpu_do_interrupt, + .do_interrupt_locked = loongarch_cpu_do_interrupt, .do_transaction_failed = loongarch_cpu_do_transaction_failed, #endif }; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 9b52ad5fc23..85496deff67 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -712,7 +712,7 @@ static const TCGCPUOps m68k_tcg_ops = { .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .cpu_exec_halt = m68k_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = m68k_cpu_do_interrupt, + .do_interrupt_locked = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 389a5124b12..649bcebf703 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -450,7 +450,7 @@ static const TCGCPUOps mb_tcg_ops = { .cpu_exec_interrupt = mb_cpu_exec_interrupt, .cpu_exec_halt = mb_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = mb_cpu_do_interrupt, + .do_interrupt_locked = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, .do_unaligned_access = mb_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0fead20d651..073e466b713 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -718,7 +718,7 @@ static const TCGCPUOps mips_tcg_ops = { .cpu_exec_interrupt = mips_cpu_exec_interrupt, .cpu_exec_halt = mips_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = mips_cpu_do_interrupt, + .do_interrupt_locked = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, .do_unaligned_access = mips_cpu_do_unaligned_access, .io_recompile_replay_branch = mips_io_recompile_replay_branch, diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 66c00c0930c..83dc071c180 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -268,7 +268,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .cpu_exec_halt = openrisc_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = openrisc_cpu_do_interrupt, + .do_interrupt_locked = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6c626843c93..2676562b2f1 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7498,7 +7498,7 @@ static const TCGCPUOps ppc_tcg_ops = { .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .cpu_exec_halt = ppc_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = ppc_cpu_do_interrupt, + .do_interrupt_locked = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, .cpu_exec_exit = ppc_cpu_exec_exit, .do_unaligned_access = ppc_cpu_do_unaligned_access, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 9e3cc87f8a3..ea3189ab3d2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -289,7 +289,7 @@ const TCGCPUOps riscv_tcg_ops = { .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .cpu_exec_halt = riscv_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = riscv_cpu_do_interrupt, + .do_interrupt_locked = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, .debug_excp_handler = riscv_cpu_debug_excp_handler, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 9b8473d71cf..ea58a804154 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -229,7 +229,7 @@ static const TCGCPUOps rx_tcg_ops = { .cpu_exec_interrupt = rx_cpu_exec_interrupt, .cpu_exec_halt = rx_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = rx_cpu_do_interrupt, + .do_interrupt_locked = rx_cpu_do_interrupt, }; static void rx_cpu_class_init(ObjectClass *klass, const void *data) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7c725b8a4a4..053eafaa842 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -386,7 +386,7 @@ static const TCGCPUOps s390_tcg_ops = { .cpu_exec_interrupt = s390_cpu_exec_interrupt, .cpu_exec_halt = s390_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = s390_cpu_do_interrupt, + .do_interrupt_locked = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, .do_unaligned_access = s390x_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3bbdee301d5..fdab5106b27 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -314,7 +314,7 @@ static const TCGCPUOps superh_tcg_ops = { .cpu_exec_interrupt = superh_cpu_exec_interrupt, .cpu_exec_halt = superh_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = superh_cpu_do_interrupt, + .do_interrupt_locked = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, .io_recompile_replay_branch = superh_io_recompile_replay_branch, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ae9bdca9df8..23fd0a5e3fe 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1076,7 +1076,7 @@ static const TCGCPUOps sparc_tcg_ops = { .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .cpu_exec_halt = sparc_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = sparc_cpu_do_interrupt, + .do_interrupt_locked = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, .do_unaligned_access = sparc_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7c25b9ab707..e980a13eadd 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -327,7 +327,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .cpu_exec_halt = xtensa_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt = xtensa_cpu_do_interrupt, + .do_interrupt_locked = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, .do_unaligned_access = xtensa_cpu_do_unaligned_access, .debug_check_breakpoint = xtensa_debug_check_breakpoint, From patchwork Wed Sep 2 15:20:38 2026 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce47885b1sm76527705e9.14.2026.09.02.08.21.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 08:21:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , Pierrick Bouvier , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/11] accel/tcg: Add do_interrupt() wrapper for targets to manage BQL Date: Wed, 2 Sep 2026 17:20:38 +0200 Message-ID: <20260902152044.31291-8-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=H4/rBeYi c=1 sm=1 tr=0 ts=6a983f08 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=2yN2iZOksrgf2_ncbZYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-GUID: 93e-nsCJh1EabAYQxjcuD2mWjAW5NbjT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfXyeiK74pUEZu0 o8M48m7oq7IOs1c8pzdItP27XLebBnZzdRLMa9waoikk8yroK/ixgpKCzrSO7JXziaurnbQtIjF 15/3c2aSv7etrUftaUnCWdIdsguvs91m//Cc3NrOXXyiS01THAvmjoSUyPO+9uQ75hSGX2O3EKL 8wWCXvmpiBctajqcTp/pBPuGEVpYNiw6Ur3SsAizpngZP4oKLn9Aa7zX2uIplcG5DBv7PJmRaei CwldfwbL8G07jUtGLfH78U6EUlH77/Qo4BzouWmE5/vjF1W5MpmbQ3Gg/65yDWAhs9AxJRV+cwj RJq6PFPySQAGJrV4POPa37FB9ma001KGiAtAmQACBL/nUvJPracsP7+IUooVP98NYZ5YTqpYG7t wgW4KV/LQjGVAXWIHXu/MYsSqqvCumdFdXXqqVPUgUm4PKch3i1WWAmwKTSGt2ghBFa8UIrfYX9 Tk5Fk4L7+7SuFMMQL6w== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfX+CpBILZ724xQ ZdSM9RnyN0Gx1g/pXzafhUS7fuYRcb1+WcLZrfenIhzypAE/qut2+gC8ouo636zIgDOBiW7CIZ8 k6W0BzJ8Pz28jS8zBGZiTu1r5fExcrU= X-Proofpoint-ORIG-GUID: 93e-nsCJh1EabAYQxjcuD2mWjAW5NbjT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 clxscore=1015 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020136 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add TCGCPUOps::do_interrupt() as a wrapper that targets can implement to control BQL locking independently. The existing do_interrupt_locked() callback remains for BQL-held contexts. This allows each target to decide when to acquire the BQL. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 14 ++++++++++++++ accel/tcg/cpu-exec.c | 12 ++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 2e97f79a373..e2e67f796f6 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -169,6 +169,20 @@ struct TCGCPUOps { */ vaddr (*untagged_addr)(CPUState *cs, vaddr addr); #else + /** + * @do_interrupt: Deliver a pending exception/interrupt to the CPU + * + * Called when cs->exception_index contains the exception code to deliver. + * Updates CPU architectural state (usually before executing a guest + * exception handler). + * + * Called from cpu_handle_exception(). Implementations must acquire the + * BQL before modifying CPU state and hold it for the duration of the + * handler (this ensures safe access to shared CPU and device state during + * exception delivery, which may be cross-vCPU). + */ + void (*do_interrupt)(CPUState *cpu); + /** * @do_interrupt_locked: Deliver a pending exception/interrupt to the CPU * @cpu: cpu context diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8d9c203f222..4deb7e00571 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -727,9 +727,13 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (replay_exception()) { const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - bql_lock(); - tcg_ops->do_interrupt_locked(cpu); - bql_unlock(); + if (tcg_ops->do_interrupt) { + tcg_ops->do_interrupt(cpu); + } else { + bql_lock(); + tcg_ops->do_interrupt_locked(cpu); + bql_unlock(); + } cpu->exception_index = -1; if (unlikely(cpu_single_stepping(cpu))) { @@ -1059,7 +1063,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); assert(tcg_ops->cpu_exec_reset); - assert(tcg_ops->do_interrupt_locked); + assert(tcg_ops->do_interrupt || tcg_ops->do_interrupt_locked); assert(tcg_ops->pointer_wrap); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); From patchwork Wed Sep 2 15:20:39 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 2296805 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=OfJqEvtg; dkim=pass (2048-bit key; unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=eaTyyzKr; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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This reflects the actual locking model used by the target. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Brian Cain --- target/hexagon/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b5dcbfc99db..7067e5b70f7 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -769,7 +769,7 @@ static const TCGCPUOps hexagon_tcg_ops = { .tlb_fill = hexagon_tlb_fill, .do_unaligned_access = hexagon_cpu_do_unaligned_access, .cpu_exec_halt = hexagon_cpu_has_work, - .do_interrupt_locked = hexagon_cpu_do_interrupt, + .do_interrupt = hexagon_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; From patchwork Wed Sep 2 15:20:40 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 2296800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Iglesias" , Stafford Horne Subject: [RFC PATCH v3 09/11] targets: Move interrupt handlers to do_interrupt() Date: Wed, 2 Sep 2026 17:20:40 +0200 Message-ID: <20260902152044.31291-10-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfXyZILziiJCHZD DyguprMfCodD/BM73m/hqwGRuwJhsucLXu55Mt10wkPiPk6FTSMdbx6sNAZm503wDBKpx5NPDRb 73LVUu1/WWVLVdlEvoPytI1K1cNY5qlFlKL+v34X151JyyeZC+MqrUIgh+j4fJzPYlafjrGTn8e 3TL8012X3JXDxwd6l8W4QkqQZ45HwIVkEiDZHYb4qtBgH0PSYwGOiAXYVv+HJnvfk6MtovjePTD oufS39socib0X+eH33zCrfsVwvWgvroTRGbYIwfOK98Gm3sJioyUNzPFYLvwB6/5dqkKhx0hj7m 9TJ3ApY3SFIjfDa/BKXD8X/jfo8cVPcbiPWUYBdAIwS80EautIe5ELxtslDALrH1twY/0359UR8 eIV3ZbB3ztvfIMbjqQRgMZXKYSHpHo9iWFt+w1AHc1n3Frzp7AP7eAB5pWOEGat33H7qq3289xQ 9afY4hWyy5IvNFppKuA== X-Proofpoint-GUID: pXf4FMqk3Z69wmEfA8lJqyYvEERRFTEZ X-Authority-Analysis: v=2.4 cv=D8N37PRj c=1 sm=1 tr=0 ts=6a983f16 cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=-wU1GuQjd2BOtWieTlsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-ORIG-GUID: pXf4FMqk3Z69wmEfA8lJqyYvEERRFTEZ X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfX/PydMMm2n4fi f83p5g1Qao7fRJxAH/gEfhwVQL6j+Y4itqDE6kg+tmdU4vIiDoZUpgEmTo3MMC5v4AAS7i0VRHU T9HJj46eCRvLn9Im2Uh+uXtwn277Kac= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020136 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org LoongArch, M68K, MicroBlaze, and OpenRISC interrupt handlers don't require external BQL protection, so move them from do_interrupt_locked() to do_interrupt(). Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/tcg/tcg_cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/or1k/cpu.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 6455ae0c99a..4b1d44a1644 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -329,7 +329,7 @@ const TCGCPUOps loongarch_tcg_ops = { .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, .cpu_exec_halt = loongarch_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = loongarch_cpu_do_interrupt, + .do_interrupt = loongarch_cpu_do_interrupt, .do_transaction_failed = loongarch_cpu_do_transaction_failed, #endif }; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 85496deff67..9b52ad5fc23 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -712,7 +712,7 @@ static const TCGCPUOps m68k_tcg_ops = { .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .cpu_exec_halt = m68k_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = m68k_cpu_do_interrupt, + .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 649bcebf703..389a5124b12 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -450,7 +450,7 @@ static const TCGCPUOps mb_tcg_ops = { .cpu_exec_interrupt = mb_cpu_exec_interrupt, .cpu_exec_halt = mb_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = mb_cpu_do_interrupt, + .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, .do_unaligned_access = mb_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 83dc071c180..66c00c0930c 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -268,7 +268,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .cpu_exec_halt = openrisc_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = openrisc_cpu_do_interrupt, + .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; From patchwork Wed Sep 2 15:20:41 2026 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce7d04c69sm42533125e9.8.2026.09.02.08.22.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 08:22:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , Pierrick Bouvier , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Rolnik , Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Artyom Tarasenko , Max Filippov Subject: [RFC PATCH v3 10/11] targets: Move BQL locking into do_interrupt() handlers Date: Wed, 2 Sep 2026 17:20:41 +0200 Message-ID: <20260902152044.31291-11-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfXzE4DWiLYeEi9 +yYkAiJiaJiQYTp2LAHLyHek96LTEaflDaktL1vb0gU2ySWb3rsABQYJhx4JN8oKwVdx6AuDjU5 xN5YrHLVSts4966yE0ngBkp+GfgDlBdRtMi/0ac3/z6pn9vp+mWapfJPxxZk7+ftOkzMxQL++ll FFGGQEmq3c/HFSTk+xpQCqGBmsXSgfDfIp/Mb3QO63kXWNda8/qpNYyuS1kpXh0fpaVuc1UUfNN 5lgMl2peWA/oo+2wRmk4ZnJlN++MtT/eciApi8HlDKFmhCszm1CUuNrDvsePsYeXxVDqVzaBMIA B4YMcwY1CH/AUTmee9xIc2xr1YLNBxs/jqFApNMwY+WjqKBSZ+GsgQ+3uBgyvm7+Ib87iZ8nzMH /Wle7kzylluI8PotveJjqrh3QybNjRDUdbDVWMm1Mw6iaGzA7zTpSWu7Feadef6Xpeo+EqOlyEY oOtCigzfnrUGUKXGnTQ== X-Proofpoint-ORIG-GUID: 3lkK9wavVwE5fHfAdrX9dLXPYA83CeTE X-Authority-Analysis: v=2.4 cv=QfpWeMbv c=1 sm=1 tr=0 ts=6a983f28 cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=u4KzQEefR3bvkf7lQMoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-GUID: 3lkK9wavVwE5fHfAdrX9dLXPYA83CeTE X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfX4I4qjrmIxbm3 3X85HXdPgS09liZioKbUnPFrbw/S03CZElSgUhn4hPybUQBnKS1NFk3FtfOUoN7M65SduD3duTW owvjEIbSXhNrjgpS3i8tHRGKQG3y0aI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020136 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Migrate 13 targets to acquire the BQL explicitly within their do_interrupt() implementations instead of relying on the TCG core to hold it. This allows per-target control over locking granularity and paves the way for fine-grained BQL optimization. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 3 +++ target/arm/cpu.c | 2 +- target/arm/helper.c | 1 + target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/m_helper.c | 2 ++ target/avr/cpu.c | 2 +- target/avr/helper.c | 3 +++ target/hppa/cpu.c | 2 +- target/hppa/int_helper.c | 2 ++ target/i386/tcg/system/seg_helper.c | 2 ++ target/i386/tcg/tcg-cpu.c | 2 +- target/mips/cpu.c | 2 +- target/mips/tcg/system/tlb_helper.c | 3 +++ target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/rx/helper.c | 3 +++ target/s390x/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 3 +++ target/sh4/cpu.c | 2 +- target/sh4/helper.c | 3 +++ target/sparc/cpu.c | 2 +- target/sparc/int32_helper.c | 2 ++ target/sparc/int64_helper.c | 2 ++ target/xtensa/cpu.c | 2 +- target/xtensa/exc_helper.c | 2 ++ 28 files changed, 47 insertions(+), 14 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index aca9e82bfb2..12e86021663 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -267,7 +267,7 @@ static const TCGCPUOps alpha_tcg_ops = { .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .cpu_exec_halt = alpha_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = alpha_cpu_do_interrupt, + .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, .do_unaligned_access = alpha_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/alpha/helper.c b/target/alpha/helper.c index c3614ecafda..e21cd8e2b44 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -26,6 +26,7 @@ #include "fpu/softfloat-types.h" #include "fpu/softfloat-helpers.h" #include "exec/helper-proto.h" +#include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "system/memory.h" #include "accel/tcg/cpu-loop.h" @@ -341,6 +342,8 @@ void alpha_cpu_do_interrupt(CPUState *cs) int i = cs->exception_index; uint64_t last_pc = env->pc; + BQL_LOCK_GUARD(); + if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; const char *name = ""; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0d0555b7ad4..77aa78f00e2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2606,7 +2606,7 @@ static const TCGCPUOps arm_tcg_ops = { .cpu_exec_interrupt = arm_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = arm_cpu_do_interrupt, + .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, .adjust_watchpoint_address = arm_adjust_watchpoint_address, diff --git a/target/arm/helper.c b/target/arm/helper.c index c3f607e6d6b..fbedb3fa39c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9714,6 +9714,7 @@ void arm_cpu_do_interrupt(CPUState *cs) uint64_t last_pc = cs->cc->get_pc(cs); assert(!arm_feature(env, ARM_FEATURE_M)); + BQL_LOCK_GUARD(); arm_log_exception(cs); qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 1f698b70283..502998dbd1c 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -304,7 +304,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = arm_v7m_cpu_do_interrupt, + .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, .adjust_watchpoint_address = arm_adjust_watchpoint_address, diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 33c9e7c55bc..9e15781f08d 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2214,6 +2214,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) bool ignore_stackfaults; uint64_t last_pc = env->regs[15]; + BQL_LOCK_GUARD(); + arm_log_exception(cs); /* diff --git a/target/avr/cpu.c b/target/avr/cpu.c index bc7639031b8..f8409f32ab9 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -249,7 +249,7 @@ static const TCGCPUOps avr_tcg_ops = { .cpu_exec_halt = avr_cpu_has_work, .cpu_exec_reset = cpu_reset, .tlb_fill = avr_cpu_tlb_fill, - .do_interrupt_locked = avr_cpu_do_interrupt, + .do_interrupt = avr_cpu_do_interrupt, /* * TODO: code and data wrapping are different, but for the most part * AVR only references bytes or aligned code fetches. But we use diff --git a/target/avr/helper.c b/target/avr/helper.c index f452c9d9040..ed839b6db31 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/cpu-loop.h" @@ -89,6 +90,8 @@ void avr_cpu_do_interrupt(CPUState *cs) vector = ctz64(env->intsrc) + 1; } + BQL_LOCK_GUARD(); + if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { do_stb(env, env->sp--, ret, 0); do_stb(env, env->sp--, ret >> 8, 0); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c6d915d314f..07b49e51326 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -272,7 +272,7 @@ static const TCGCPUOps hppa_tcg_ops = { .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .cpu_exec_halt = hppa_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = hppa_cpu_do_interrupt, + .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, .do_transaction_failed = hppa_cpu_do_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 3e87b9a0011..852d0649d84 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -98,6 +98,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) uint64_t old_psw, old_gva_offset_mask; uint64_t last_pc = cs->cc->get_pc(cs); + BQL_LOCK_GUARD(); + /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); diff --git a/target/i386/tcg/system/seg_helper.c b/target/i386/tcg/system/seg_helper.c index 8c7856be81e..8eaeb746128 100644 --- a/target/i386/tcg/system/seg_helper.c +++ b/target/i386/tcg/system/seg_helper.c @@ -115,6 +115,8 @@ void x86_cpu_do_interrupt(CPUState *cs) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + BQL_LOCK_GUARD(); + if (cs->exception_index == EXCP_VMEXIT) { assert(env->old_exception == -1); do_vmexit(env); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index ff65641654d..7a4d73e7fee 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -179,7 +179,7 @@ const TCGCPUOps x86_tcg_ops = { #else .tlb_fill = x86_cpu_tlb_fill, .pointer_wrap = x86_pointer_wrap, - .do_interrupt_locked = x86_cpu_do_interrupt, + .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_halt = x86_cpu_exec_halt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .cpu_exec_reset = x86_cpu_exec_reset, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 073e466b713..0fead20d651 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -718,7 +718,7 @@ static const TCGCPUOps mips_tcg_ops = { .cpu_exec_interrupt = mips_cpu_exec_interrupt, .cpu_exec_halt = mips_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = mips_cpu_do_interrupt, + .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, .do_unaligned_access = mips_cpu_do_unaligned_access, .io_recompile_replay_branch = mips_io_recompile_replay_branch, diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index 4398c6f80b4..2b8478f9a9d 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/bitops.h" +#include "qemu/main-loop.h" #include "qemu/plugin.h" #include "cpu.h" @@ -1045,6 +1046,8 @@ void mips_cpu_do_interrupt(CPUState *cs) int cause = -1; uint64_t last_pc = env->active_tc.PC; + BQL_LOCK_GUARD(); + if (qemu_loglevel_mask(CPU_LOG_INT) && cs->exception_index != EXCP_EXT_INTERRUPT) { qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 2676562b2f1..6c626843c93 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7498,7 +7498,7 @@ static const TCGCPUOps ppc_tcg_ops = { .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .cpu_exec_halt = ppc_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = ppc_cpu_do_interrupt, + .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, .cpu_exec_exit = ppc_cpu_exec_exit, .do_unaligned_access = ppc_cpu_do_unaligned_access, diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 6d05b865058..6352a4fcaf3 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1761,6 +1761,8 @@ void ppc_cpu_do_interrupt(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); + BQL_LOCK_GUARD(); + powerpc_excp(cpu, cs->exception_index); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ea3189ab3d2..9e3cc87f8a3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -289,7 +289,7 @@ const TCGCPUOps riscv_tcg_ops = { .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .cpu_exec_halt = riscv_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = riscv_cpu_do_interrupt, + .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, .debug_excp_handler = riscv_cpu_debug_excp_handler, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index ea58a804154..9b8473d71cf 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -229,7 +229,7 @@ static const TCGCPUOps rx_tcg_ops = { .cpu_exec_interrupt = rx_cpu_exec_interrupt, .cpu_exec_halt = rx_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = rx_cpu_do_interrupt, + .do_interrupt = rx_cpu_do_interrupt, }; static void rx_cpu_class_init(ObjectClass *klass, const void *data) diff --git a/target/rx/helper.c b/target/rx/helper.c index 0f99279bbaa..784193ebd40 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/log.h" #include "accel/tcg/cpu-ldst.h" @@ -47,6 +48,8 @@ void rx_cpu_do_interrupt(CPUState *cs) uint32_t save_psw; uint64_t last_pc = env->pc; + BQL_LOCK_GUARD(); + env->in_sleep = 0; if (env->psw_u) { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 053eafaa842..7c725b8a4a4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -386,7 +386,7 @@ static const TCGCPUOps s390_tcg_ops = { .cpu_exec_interrupt = s390_cpu_exec_interrupt, .cpu_exec_halt = s390_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = s390_cpu_do_interrupt, + .do_interrupt = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, .do_unaligned_access = s390x_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 01c0d77b13b..d39d41bfcf3 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -28,6 +28,7 @@ #include "s390x-internal.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY +#include "qemu/main-loop.h" #include "qemu/timer.h" #include "system/address-spaces.h" #include "system/memory.h" @@ -503,6 +504,8 @@ void s390_cpu_do_interrupt(CPUState *cs) bool stopped = false; uint64_t last_pc = cpu->env.psw.addr; + BQL_LOCK_GUARD(); + qemu_log_mask(CPU_LOG_INT, "%s: %d at psw=%" PRIx64 ":%" PRIx64 "\n", __func__, cs->exception_index, env->psw.mask, env->psw.addr); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index fdab5106b27..3bbdee301d5 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -314,7 +314,7 @@ static const TCGCPUOps superh_tcg_ops = { .cpu_exec_interrupt = superh_cpu_exec_interrupt, .cpu_exec_halt = superh_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = superh_cpu_do_interrupt, + .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, .io_recompile_replay_branch = superh_io_recompile_replay_branch, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b6b057f104b..1d854262d13 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -28,6 +28,7 @@ #include "qemu/plugin.h" #if !defined(CONFIG_USER_ONLY) +#include "qemu/main-loop.h" #include "hw/sh4/sh_intc.h" #include "system/runstate.h" #endif @@ -64,6 +65,8 @@ void superh_cpu_do_interrupt(CPUState *cs) int do_exp, irq_vector = cs->exception_index; uint64_t last_pc = env->pc; + BQL_LOCK_GUARD(); + /* prioritize exceptions over interrupts */ do_exp = cs->exception_index != -1; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 23fd0a5e3fe..ae9bdca9df8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1076,7 +1076,7 @@ static const TCGCPUOps sparc_tcg_ops = { .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .cpu_exec_halt = sparc_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = sparc_cpu_do_interrupt, + .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, .do_unaligned_access = sparc_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index d6bb3fa1e54..3eea824c9a3 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -105,6 +105,8 @@ void sparc_cpu_do_interrupt(CPUState *cs) CPUSPARCState *env = cpu_env(cs); int cwp, intno = cs->exception_index; + BQL_LOCK_GUARD(); + if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; const char *name; diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 60ab0478fc6..e26d3ac5142 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -138,6 +138,8 @@ void sparc_cpu_do_interrupt(CPUState *cs) int intno = cs->exception_index; trap_state *tsptr; + BQL_LOCK_GUARD(); + #ifdef DEBUG_PCALL if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e980a13eadd..7c25b9ab707 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -327,7 +327,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .cpu_exec_halt = xtensa_cpu_has_work, .cpu_exec_reset = cpu_reset, - .do_interrupt_locked = xtensa_cpu_do_interrupt, + .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, .do_unaligned_access = xtensa_cpu_do_unaligned_access, .debug_check_breakpoint = xtensa_debug_check_breakpoint, diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 7cb67d179a8..81b303a35f3 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -208,6 +208,8 @@ void xtensa_cpu_do_interrupt(CPUState *cs) { CPUXtensaState *env = cpu_env(cs); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448e72d2asm6668125f8f.8.2026.09.02.08.22.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 08:22:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , Pierrick Bouvier , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 11/11] accel/tcg: Remove do_interrupt_locked() callback Date: Wed, 2 Sep 2026 17:20:42 +0200 Message-ID: <20260902152044.31291-12-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902152044.31291-1-philmd@oss.qualcomm.com> References: <20260902152044.31291-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-GUID: YrRX2dPyMZi39bteqURdakzllqDg8hL8 X-Proofpoint-ORIG-GUID: YrRX2dPyMZi39bteqURdakzllqDg8hL8 X-Authority-Analysis: v=2.4 cv=YKuvDxGx c=1 sm=1 tr=0 ts=6a983f2c cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=tCPwWEVRRVLTMAjpPnAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfX4xuy0hbC3zdk 3FDDn3dJ9DPWvDqgfw9tReJFP9vxr/9XOaL2alrE4wU6NNnHKOMlPUmmhXlGtRVY3RNT8jWimKd BxByRrYbAOdJ+z6cv/exWVYcuNw0bk8bS1NRpQcyiym0yK1DPSdaP5VvCRChOhFUAExf7Z777SW 6AlcVSaiIChSng5zRo/gFprPnwuq1xkg8o2nTVhbTS/qzEEAGmXoSY/XS9XUbsg5yoKx2Sw7wL2 8FoxoH1xA4DKQTWYWNdFaiC+KuWXLdX83nG26cmtQ11Ajps64V2HHBPL5H0LUetdxIAtIJESMfU tBkLGY5CrFHxhrGQph0hXmB8Q1WJKxfzoxYmVI9r9Vf+YLMAJ9Hk1wIz9XRoVhORp+dMzgVHwH7 8R5c3zWXJhbs04DX3aCEk5fKv/30e9Fd7GfS5yZCrGP2eN5+9g/LgKxMK387K30BxW1liBi5HrY 2Ra1C7UOoWscHtr+c6A== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDEzNiBTYWx0ZWRfX5e38gocznCHb yEr4lYjIvLC30XqDJQOq9G8/PbP4OOd7vKwnMqDZ3Jn4+SbgCTQt1NiY11r8uC9j0ek5vJm9Fd6 whha7+VQIACHz3jMyBjMJTHH9Hlwbss= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_03,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020136 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org All targets now manage their own BQL locking via do_interrupt(), making the do_interrupt_locked() hook unnecessary. Remove it to simplify the TCGCPUOps interface. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 12 ------------ accel/tcg/cpu-exec.c | 10 ++-------- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index e2e67f796f6..89b3a11fd6a 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -183,18 +183,6 @@ struct TCGCPUOps { */ void (*do_interrupt)(CPUState *cpu); - /** - * @do_interrupt_locked: Deliver a pending exception/interrupt to the CPU - * @cpu: cpu context - * - * Called when cs->exception_index contains an exception code to deliver. - * Updates CPU architectural state (usually before executing a guest - * exception handler). - * - * Called from cpu_handle_exception() with BQL held. - */ - void (*do_interrupt_locked)(CPUState *cpu); - /** * @cpu_exec_interrupt: Callback for processing target-specific interrupts * @cpu: cpu context diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4deb7e00571..5d4b26357ff 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -727,13 +727,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (replay_exception()) { const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - if (tcg_ops->do_interrupt) { - tcg_ops->do_interrupt(cpu); - } else { - bql_lock(); - tcg_ops->do_interrupt_locked(cpu); - bql_unlock(); - } + tcg_ops->do_interrupt(cpu); cpu->exception_index = -1; if (unlikely(cpu_single_stepping(cpu))) { @@ -1063,7 +1057,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); assert(tcg_ops->cpu_exec_reset); - assert(tcg_ops->do_interrupt || tcg_ops->do_interrupt_locked); + assert(tcg_ops->do_interrupt); assert(tcg_ops->pointer_wrap); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code);