From patchwork Wed Sep 2 14:15:51 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296688 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=zs6c15w6; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=VXKwdNq4; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCF4ZPXz1xwg for ; Thu, 03 Sep 2026 00:16:25 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id E4483808C6; Wed, 2 Sep 2026 14:16:23 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id QgAonar_JuFc; Wed, 2 Sep 2026 14:16:23 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358583; bh=A3CCZhmC6ul9Johiq9Y4kJEC4x78uyGlzeDkVBgJG7w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=zs6c15w6Tp8vnWWuQzrEROgxvcBZrZTy4ghnTfJAyFeCadlGOg2MfRLNsEH8qVxpf nTrwcxzVOYKPNQfRyZomhgGXb71lBW2Q390QOsDEzLaGPSjiZS47oPkrFouUj87F/y r0e+1XrhMepx9Hk2yLRepDI2lXkKMPru/Mr64W+t2bI4XcnfQy/TzofcMiKi/ZwJ4U Al+ljIZ0hdwbjIct/bM9FTjD3pvx0TPc1k6Bhx+8cMp8OYa3CcjZylf+m3OWtv28At wSGux2pUuWDBwZ5YkxRFnXenZRc9Q9TNHWuRdYJ7zkhRtStDR05ifT0PvNJzIEbtW6 BV6pH3bOl3tJA== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 067FD80EC2; Wed, 2 Sep 2026 14:16:23 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [IPv6:2605:bc80:3010::136]) by lists1.osuosl.org (Postfix) with ESMTP id 93641363 for ; Wed, 2 Sep 2026 14:16:21 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 78972606CF for ; Wed, 2 Sep 2026 14:16:21 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id MWzDpcFwOEOF for ; Wed, 2 Sep 2026 14:16:20 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::52d; helo=mail-ed1-x52d.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp3.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=VXKwdNq4 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by smtp3.osuosl.org (Postfix) with ESMTPS id A086E606B4 for ; Wed, 2 Sep 2026 14:16:18 +0000 (UTC) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-6a6108734d5so1846800a12.3 for ; Wed, 02 Sep 2026 07:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358577; x=1788963377; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=A3CCZhmC6ul9Johiq9Y4kJEC4x78uyGlzeDkVBgJG7w=; b=VXKwdNq4YsNbWh28oAqfMamsoVLsiOWw+6jEH4mqxQBXuYPeiTcXFUr7R8uNnKV8Qv AiaEcHj6YrEAb+iFnrfi151XI2zgMs6rJXxaZerzLmxKeCh3nypZkdMG5usW3QQ2Mlao GDGlKWMn7Rtzt+eSTSS1lZexW9aU6X6JVEe9xHd7iR2ulhFitnGu7cVImnH2OIauRnet CNWEhgKd9zKP56SPLHWeKxVTOrYYauoyMygdBtqQ5MpJt/NnYyy1vAQIRT4S0QJLzGoN a8GHoM7oWHJS1U9WlW46zEAVjRoChB1UGQjgjeAxW+b79PGfcJjLmhQ/iaN/HqNKjI90 0BOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358577; x=1788963377; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=A3CCZhmC6ul9Johiq9Y4kJEC4x78uyGlzeDkVBgJG7w=; b=ULjUiJxWZJ6oSHLmm+++2dHEBWtm4qdOGIX1wI+2R9/DSV0/pJsfsy43XAg7xfJVpc UoWD+0fAdJhgysqShmY23+5PHKfvMjeYTU2tbdeM3SKj8zLIYde9SM1WDwWERZAO5Zh3 WVP8D+Y+moYm2Zfj0ouwVcnvcekxU0XDNlyZw4fQ75+gTOtN8aqPHtTbPjHwWw2J571c SQ2qdsLulfCUz0t/8kE4iCMWIeHFAl1WqZfie7ctqNMsilLtKBoesdHMH1Rn+RcNvzs5 09WVMUjxEHwcgS5W0VryljHR9yABrT7VvKmLpqctY51j3X1QohIX46/k6D0WEAQQYROz eYhA== X-Gm-Message-State: AFuF++mvtdDN4r0ooWbRv5Q/daagqDQHivgcqMmJqG7NND8pwZR/vAt2 BPBV13oUlTe9avsBQHpzPFbISZ5/n7rgMZQW6Zk1gjPISuJRzhie/kbC6S2HWJDlHwA= X-Gm-Gg: AYBFou0UxgiNW+8Ri0aj8pZqW/9oDVE2SLZPro5sX8gFIaBgBhqVNRVuiGUFDcd1VQG QQSADIJY/94R3nCA2pomUM8wd2RhrbjwxFkW4u/LqHbx+8bcbNVT+TMCOoA61rbXiSNxYO96gAd fJBQLp0P7Z3EX7A965sXm4UO898RjfeXJP6HIUTPM8W/XvtgMpig7VIEZzo4f3xlx+vX95DX5DP xJLVg1Zh761KRs0MTRGNLICilQghaHiE3oA5dvOOJzR27A9/WhhdGPUCow66MpvXKI1E8DP/wqy Ik3kItH01k5s16OTnqcTpWtTFBZW2bH8tMyQKTOZ0LJHcU9cVBKFha4kid7AFfXhLArrITQNmHA FbyezbbaCaZf9zloq3KgvJ34bq1jyly57jEbfXAl5+DiB4u8jhl2AbJ2Tk1cOBo7apA4qT6hKmk 1vg/YOdt9eRsIcg+Q+WJq92cFViwIB8s7N1W1KN7u/wAP8wVDFFptLGIuPHg3gv8573NrjH29j7 88SwSrH4tRToa9dv2KucsJDAJ6gD4CXoFyE+LmT/gYyGSAkvChZcmp4F9sCeRSum9rUkG5AQWzj VRuLp/Erdf++de6eZAjJSrFM5djncPYbXQY6z0FhdgN6Tw== X-Received: by 2002:a05:6402:5417:b0:6a3:95bd:143c with SMTP id 4fb4d7f45d1cf-6a6825665e4mr3119027a12.5.1788358576642; Wed, 02 Sep 2026 07:16:16 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:12 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:51 +0200 Subject: [PATCH v4 01/14] video: mediatek: add display pipeline component helpers MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-1-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Most of the simple display pipeline components share the same probe and enable sequence: remap the register window and enable a bulk of clocks. Add the mtk_disp_comp helpers holding this boilerplate so each component driver only has to provide its own component-specific programming. Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_disp_comp.c | 78 ++++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_disp_comp.h | 32 ++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/drivers/video/mediatek/mtk_disp_comp.c b/drivers/video/mediatek/mtk_disp_comp.c new file mode 100644 index 00000000000..07ba29e3393 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_comp.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MediaTek display pipeline component helpers + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include +#include +#include +#include +#include + +#include "mtk_disp_comp.h" + +void mtk_disp_comp_write(struct udevice *dev, u32 offset, u32 val) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + + writel(val, priv->base + offset); +} + +int mtk_disp_comp_enable(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + /* ungate the feeding SMI larb first, if any */ + if (priv->larb) { + ret = mtk_disp_comp_enable(priv->larb); + if (ret) + return ret; + } + + ret = clk_enable_bulk(&priv->clk_bulk); + if (ret) { + dev_err(dev, "failed to enable clocks: %d\n", ret); + if (priv->larb) + mtk_disp_comp_disable(priv->larb); + return ret; + } + + return 0; +} + +int mtk_disp_comp_disable(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_disable_bulk(&priv->clk_bulk); + if (ret) + dev_err(dev, "failed to disable clocks: %d\n", ret); + + if (priv->larb) + mtk_disp_comp_disable(priv->larb); + + return ret; +} + +int mtk_disp_comp_probe(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_bulk(dev, &priv->clk_bulk); + if (ret) { + dev_err(dev, "failed to get clocks: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/drivers/video/mediatek/mtk_disp_comp.h b/drivers/video/mediatek/mtk_disp_comp.h new file mode 100644 index 00000000000..9012dda3918 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_comp.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MediaTek display pipeline component helpers + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#ifndef _MTK_DISP_COMP_H +#define _MTK_DISP_COMP_H + +#include + +struct udevice; + +/* + * Common state shared by all the simple display pipeline components: + * a register window and a bulk of clocks. @larb is an optional SMI larb + * enabled and disabled together with the component (used by the RDMAs). + */ +struct mtk_disp_comp_priv { + void __iomem *base; + struct clk_bulk clk_bulk; + struct udevice *larb; +}; + +int mtk_disp_comp_probe(struct udevice *dev); +int mtk_disp_comp_enable(struct udevice *dev); +int mtk_disp_comp_disable(struct udevice *dev); +void mtk_disp_comp_write(struct udevice *dev, u32 offset, u32 val); + +#endif /* _MTK_DISP_COMP_H */ From patchwork Wed Sep 2 14:15:52 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296689 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=NEnFaV6a; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=QoQVVT91; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCL5Zqsz1xwg for ; Thu, 03 Sep 2026 00:16:30 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 0F88980D3D; Wed, 2 Sep 2026 14:16:26 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id byTwQtwz5v0V; Wed, 2 Sep 2026 14:16:25 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358585; bh=1I1vuQxV/Z8i2qDECVlVnDlM3x/aUj5wxWYD6+XB4d8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=NEnFaV6av6lo9Hdsm7OtC0wRNfUCbacwlggCeZeu5bQwEP4XuBQJ+yW4G4CYze232 eTtA8g+v/ENWmuXBPOXz9Xkejb0g1rJx4rrRxpN+LjB33un2Q7nufIiQUQYKyk7SKL cAWznWV//v1Hw6l34GAeRl1iRPpAE8y33bRGc04TRvBhT1Y3z6cI/tfj4ZToJritvq PyoOsxKDzVV52IR7yRyCKs/L9oVr4F5RAym/jT6xsfeHkeM1bIjzp+0Dv/KytObwCu +VSVB3Mc5AxkyY/ha2kxXFTZUefCcgY1lMCdzWuTLsOBn6NBufI+ecFACNFNXr94LU dGn+G8S3ceiKQ== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 7E2E480EFB; Wed, 2 Sep 2026 14:16:24 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists1.osuosl.org (Postfix) with ESMTP id 698FB230 for ; Wed, 2 Sep 2026 14:16:22 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 5B2B7606B4 for ; Wed, 2 Sep 2026 14:16:22 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 1Id7Cz2w2DP5 for ; Wed, 2 Sep 2026 14:16:21 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::433; helo=mail-wr1-x433.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp3.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=QoQVVT91 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by smtp3.osuosl.org (Postfix) with ESMTPS id 4FE1F606C4 for ; Wed, 2 Sep 2026 14:16:20 +0000 (UTC) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-48436251906so1214294f8f.0 for ; Wed, 02 Sep 2026 07:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358579; x=1788963379; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=1I1vuQxV/Z8i2qDECVlVnDlM3x/aUj5wxWYD6+XB4d8=; b=QoQVVT91yFxN95hOIBLV4PrxbBNNDMvfKVdFJj32Zk/uVxQ5pXR12p8+PJJNhvJYzw bA/KUZt8RDBm5mmNavYLQsrY2HY+0Mm33mrP7hq5AC9cKdgmIChnktzrPLpsLpLc3B9r lBwJr2EGbHzIkWquL6qB38cuxtQ91P+q3T/59B6DBBTtMXCrZa4bN7qNGF2saIDZSOP4 0jDCJFDa1L/x+IfApy7oIS4dwwCLXC4RtdWBZFuFs8ncyusun0K0RA+89qEMM3fZbGHx 3CwEwu9HxybwB2JEYcyMGzDw0vIkZDwEcujvcfOHUyMwT83e2ejVzP7ttt1SqzBIG9aV 08GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358579; x=1788963379; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=1I1vuQxV/Z8i2qDECVlVnDlM3x/aUj5wxWYD6+XB4d8=; b=cRH+QKz+UIiaetV9lekGLQBuXaRMFlPQ1r+pQeEwHLwuMj0abc1cTWrm2mNyrvq5yW VD/v7AUEm5h7RTQDBA4rbVG17Pwea8bXM5FobrtzNEI96oDee2pHXvkp4uSiPMbD8nzV gQTg863gQHZgaOb36r31DJZO1zmdO3yZsRJ528VDvqHYrM3EoLGDvT7U+wfKEZ1emIke HVzELRHaR28NW5657D7X82WJlsS1zTEH/fwQLnorM46OJIkNypBbntW5cnG7H66KYvR3 FLvuNsmwGve2HyimH1Pea2MmS84QDZOA7qEVB2OmBIS8hY+BW5/jSE4q61z7+e9YGoLY UzAQ== X-Gm-Message-State: AFuF++kBnOaLGUQNRw5oiT0sVPj1QxciabAEILUCo39yW7XJo6IPIKbT rVxy1Kt5eJtI9VrWY4P7fe/ne5m8TYn9Ud7925UyHMf9jZCIkiF/cZHMRXNErHJ5JjE= X-Gm-Gg: AYBFou3Eckm2bwTBmVpwIZ4e/Uvy3bbBrprh1NAllbyelEVchjRRd1gQdZsdfoNvdZ+ ZTLRtoy/27IveLd2NQGMawid8HF/FqpHJcK2QSEewkcF6EaIZnIlhf9X8VoCH2kmIY0aCIJ4Xkj YE37KTncvjO7Qmkox6BcoFBlh66ydQgZODgojHOizrsZacWFTBLUHUTeo6CsdH+omBWpsJyudal 0fzpYyR1tSu68Wpi6VJgy5WtYG/oCBF9CHnAyUQ7TOeNxxeaeOWhEqY2B3Bt880eRBXuJz6A/U2 ZpZ15U4IOgmhwRzFaLWD2KzjsNYUTooMUC+XZ++UM8V9w1XESRj/nbyFidpuayicfL9AthVjVZ6 nW7o+aovXBE3LXP9IJtWnoNXdh2Tnifrt/6asxZU8kV+BiDfbALwwnUJ29IBUJ/6Z6gUnbpsYn4 kNNn4N3o5eQxp4eFQEsu602C64+qWrg0WqKu8GP4IpEDDGqfbqxADg8KAtc5zXFY/xwpfEQsiyD HiyXeZ5hI6Mu4qrOmDX4FksTnbnxhE5FYmDiC3VGytdYyVwQq6qD9l6mdpRQ1TVPjp97S+d3wEG qm2nWQvNnM6TikePpSK5iE1hFIIYjPSQ7Z7gqiRa7fX1 X-Received: by 2002:a05:6000:2209:b0:47f:6f9e:1e82 with SMTP id ffacd0b85a97d-48488e045bdmr9108845f8f.9.1788358578773; Wed, 02 Sep 2026 07:16:18 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:17 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:52 +0200 Subject: [PATCH v4 02/14] video: mediatek: add ethdr component MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-2-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The ETHDR is one of the components of the video pipeline on some MediaTek SoCs, such as the MT8188. Only its mixer sub-block is used, which is the block's first register window. Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_ethdr.c | 72 ++++++++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_ethdr.h | 16 +++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/video/mediatek/mtk_ethdr.c b/drivers/video/mediatek/mtk_ethdr.c new file mode 100644 index 00000000000..7584fd565f5 --- /dev/null +++ b/drivers/video/mediatek/mtk_ethdr.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Mediatek Video ETHDR support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include + +#include "mtk_disp_comp.h" +#include "mtk_ethdr.h" + +#define MIX_EN 0xc +#define MIX_ROI_SIZE 0x18 +#define MIX_DATAPATH_CON 0x1c +#define OUTPUT_NO_RND BIT(3) +#define SOURCE_RGB_SEL BIT(7) +#define BACKGROUND_RELAY (4 << 9) +#define MIX_ROI_BGCLR 0x20 +#define BGCLR_BLACK 0xff000000 +#define MIX_SRC_CON 0x24 +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) +#define NON_PREMULTI_SOURCE (2 << 12) +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) +#define MIX_FUNC_DCM0 0x120 +#define MIX_FUNC_DCM1 0x124 +#define MIX_FUNC_DCM_ENABLE 0xffffffff + +/* Fields used by this driver but not present in the upstream driver */ +#define MIX_SRC_L2_EN BIT(2) +#define L2_SRC_SEL (2 << 20) +#define L2_OUT_SEL (2 << 22) + +void mtk_ethdr_config(struct udevice *dev, u16 width, u16 height) +{ + /* enable internal clocks */ + mtk_disp_comp_write(dev, MIX_FUNC_DCM0, MIX_FUNC_DCM_ENABLE); + mtk_disp_comp_write(dev, MIX_FUNC_DCM1, MIX_FUNC_DCM_ENABLE); + + /* enable mixer */ + mtk_disp_comp_write(dev, MIX_EN, 0x1); + + mtk_disp_comp_write(dev, MIX_ROI_SIZE, (height << 16) | width); + mtk_disp_comp_write(dev, MIX_DATAPATH_CON, + OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY); + mtk_disp_comp_write(dev, MIX_L_SRC_SIZE(2), (height << 16) | width); + mtk_disp_comp_write(dev, MIX_ROI_BGCLR, BGCLR_BLACK); + + /* only configure L2 since only rdma4 and rdma5 are used */ + mtk_disp_comp_write(dev, MIX_L_SRC_CON(2), NON_PREMULTI_SOURCE); + mtk_disp_comp_write(dev, MIX_SRC_CON, + MIX_SRC_L2_EN | L2_SRC_SEL | L2_OUT_SEL); +} + +static const struct udevice_id mtk_ethdr_ids[] = { + { .compatible = "mediatek,mt8195-disp-ethdr" }, + { } +}; + +/* + * The mixer is the first register window ("mixer" in reg-names) of the + * ethdr block, so binding the ethdr node with default register index 0 + * gives the mixer registers. + */ +U_BOOT_DRIVER(mtk_ethdr) = { + .name = "mtk_ethdr", + .id = UCLASS_MISC, + .of_match = mtk_ethdr_ids, + .probe = mtk_disp_comp_probe, + .priv_auto = sizeof(struct mtk_disp_comp_priv), +}; diff --git a/drivers/video/mediatek/mtk_ethdr.h b/drivers/video/mediatek/mtk_ethdr.h new file mode 100644 index 00000000000..5242b362268 --- /dev/null +++ b/drivers/video/mediatek/mtk_ethdr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Mediatek Video ETHDR support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#ifndef _MTK_ETHDR_H +#define _MTK_ETHDR_H + +struct udevice; + +void mtk_ethdr_config(struct udevice *dev, u16 width, u16 height); + +#endif From patchwork Wed Sep 2 14:15:53 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296690 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=aUEvIG/p; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=eZESqUHo; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCX6nxFz1xwg for ; Thu, 03 Sep 2026 00:16:40 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 90A3780EC2; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id GO2x4_ANWaPN; Wed, 2 Sep 2026 14:16:38 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358592; bh=PNL0Lp04gkvpttoC8BhHvFIA9qr1DH9v6KBKWhl1L9U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=aUEvIG/pVT9GEq3nCsRrMXvj8R71yn/wxtkIPbKNBemGeA1pxK1nicT29xjM8GqgF 9KKfnWNbcR7Orr5LnAgA46BBTwMaKhKE9J2cf8QOTOj7Zgp7SuDMW31FFJqGhk2Cxl 9oNVIDoojDVaHnTzCSmmTGDNfTqhoY8dOTkA3qiel0Ow4tQS0mpvoaioDAzkO1PsYY qsg54Fcn9Hf9DAClfnwr4QB0R677o3Ex15WQNJdDg8XxH8SgkcW2NNjZyUmtTutglW rdPL7E1Fo+8EaPEl/9i8t157iEDjj2GC6coPVinN2cpITUs/Qy60bnmy1/dgmt+D9Z L6jhQ3dBSXkJQ== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 6988080F58; Wed, 2 Sep 2026 14:16:31 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp4.osuosl.org (smtp4.osuosl.org [IPv6:2605:bc80:3010::137]) by lists1.osuosl.org (Postfix) with ESMTP id 2B5492FD for ; Wed, 2 Sep 2026 14:16:24 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp4.osuosl.org (Postfix) with ESMTP id 1D10240839 for ; Wed, 2 Sep 2026 14:16:24 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp4.osuosl.org ([127.0.0.1]) by localhost (smtp4.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id lAEqi_H-6W0F for ; Wed, 2 Sep 2026 14:16:23 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::42b; helo=mail-wr1-x42b.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp4.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp4.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=eZESqUHo Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by smtp4.osuosl.org (Postfix) with ESMTPS id 11523406FA for ; Wed, 2 Sep 2026 14:16:22 +0000 (UTC) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-482f2ee53e7so715716f8f.1 for ; Wed, 02 Sep 2026 07:16:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358580; x=1788963380; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=PNL0Lp04gkvpttoC8BhHvFIA9qr1DH9v6KBKWhl1L9U=; b=eZESqUHobRIZk6h4L3Hl8sOaWJHhX+Xvb4f5WqmpeCFuFxys0Y/SsSvbVN+gv8TEgu t8LtlgQMrrQf/0SLLInFJN9dZp37pIXw9qI7wUqGUuU7nTzJeXXk9PxBQA3AzAEFodxh 5RLYmiAXr5kKWRDvrRtAMkI3Re4HO4UFOLHv0xXsUff2QL4GP2hFT+d2zdKcuNgIvEiR kp/1wAn5vY5Dd0CQSVQ69kOVbQbqzLtzwAb4ITFU0L/2qI7zODIilQoFobB5MvLJV3c4 ZNaRrbyXfHzcxCxGvz3WoH20PoesWZ9X3Niwi+7INLmGPh87ryOcuW6M9D131oFHHVBv Cjkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358580; x=1788963380; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=PNL0Lp04gkvpttoC8BhHvFIA9qr1DH9v6KBKWhl1L9U=; b=cb+2iczsVZwEJtlQBRx/U5xd+DwnhVmDClgGu937uQXBHT09UMVuIhdkwpwSfgv1Id BTsYamXk00K1XnJ6PyGdUHwZX/h572NnrXyq3dzxAg5Ci0+Qf08823l47IBMRVHdq+Pa xWDo2xAAYt5zKy0NzghKwzoSUTV9irGD7GV1kOEtdEpK0JmrYk0HdMeGVN561WLfpXs4 ZGwPPHYjSIO/mVCaDmkKg9tBAp7V2ag0xJC3SCMxvUL9DbCGq8QzWQrG1hnwfRETiFMl B+8d283WASjZhEtGnNiLERh9RPNoKsOYML5iIHw1oyfXRmOuBauvJS947LQ2jsX0kbix wzlA== X-Gm-Message-State: AFuF++kNUDJLgV7ZdjRYiIMshn7NRfX/QzmgqqVaCSnxp2bzV3RrI6qb a/PsIjW9JFkWoOU14aZasnQi7FgB6LiFxJO4MBc336HYLgbppEtwEKnt1AUhOhcVfOI= X-Gm-Gg: AYBFou30TEdqIRO5M29TDEydfOVHXY6eyqlNLuYmndRuempyFbQ8npniAEpwetpkZ0E vldZrBfSyArMTm4bx1ubcVDlHhfbI99A6cqbg8j8sb1TIeOy9Hn4HN48tZtoxjaEETelT0JW+SE 2GmKy2uI01g6YDyEVT2omEFGB1Jn7RJkTdacgHhOMkXa8vu+crmugVpRcJ4z5EKZ3ctPbfzEMmM +JRqlEThrJ4LE1Z2HdY8bwHbEMVH0S99H1+XcjutX6bqvFTs0lWlXHK1qjROK/K5zXmBdViJQ3u 7HvnRmfEFpQERQg7soMKE5A3eNKKYQ8pnbc8rHeROYVXaq3ThI5m30qVevd7+WA/0oBIty/Dl3Q 0smWh+CJHVKZh0fBoVCdr706Ewl4CrNnEWH2k1dr6YzBaOyFRruJkKZTxb/QpRT6klzh/JXmGLA LEpkPjO2cCKBhcdYLGvTebkBB6K6leByfkb+scu5nTH0cTqhXTGkdCHAKxig2mozkGhTkI2mHbg Ehvz5/ByGtBg/eVgI0fnFqxox6P7bp/N0kVGSg2O6Fn9+SVtjn7dGDZ46Upy8STCrDTWOAEBYBb OVCA9O9wEQZBOIrhsWmPT0UvY4+atop8ze7o2U3SDn/e X-Received: by 2002:a5d:5f54:0:b0:482:e658:bb8e with SMTP id ffacd0b85a97d-48488f0dba5mr9933640f8f.12.1788358580365; Wed, 02 Sep 2026 07:16:20 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:19 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:53 +0200 Subject: [PATCH v4 03/14] video: mediatek: add merge component MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-3-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The merge block is one of the components of the video pipeline on some MediaTek SoCs, such as the MT8188. It combines two half-width inputs into one output. Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_disp_merge.c | 108 ++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_disp_merge.h | 19 ++++++ 2 files changed, 127 insertions(+) diff --git a/drivers/video/mediatek/mtk_disp_merge.c b/drivers/video/mediatek/mtk_disp_merge.c new file mode 100644 index 00000000000..487d6df6f0d --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_merge.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Mediatek Video Disp Merge Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include + +#include "mtk_disp_comp.h" +#include "mtk_disp_merge.h" + +#define DISP_REG_MERGE_CTRL 0x000 +#define MERGE_EN 1 +#define DISP_REG_MERGE_CFG_0 0x010 +#define DISP_REG_MERGE_CFG_1 0x014 +#define DISP_REG_MERGE_CFG_4 0x020 +#define DISP_REG_MERGE_CFG_10 0x038 +#define DISP_REG_MERGE_CFG_12 0x040 +#define CFG_10_10_2PI_2PO_BUF_MODE 8 +#define CFG_11_10_1PI_2PO_MERGE 18 +#define DISP_REG_MERGE_CFG_24 0x070 +#define DISP_REG_MERGE_CFG_25 0x074 +#define DISP_REG_MERGE_CFG_26 0x078 +#define DISP_REG_MERGE_CFG_27 0x07c +#define DISP_REG_MERGE_MUTE_0 0xf00 + +/* CFG_30 (0x088, "12 bit lsb off") is not present in the upstream driver */ +#define DISP_REG_MERGE_CFG_30 0x088 + +void mtk_disp_merge_config(struct udevice *dev, + u16 width1, u16 height1, + u16 width2, u16 height2, + u16 output_width, u16 output_height) +{ + bool dual_input = (width2 != 0 && height2 != 0); + + /* input 1 */ + if (width1 != 0 && height1 != 0) + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_0, + height1 << 16 | width1); + + /* input 2 */ + if (dual_input) + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_1, + height2 << 16 | width2); + + /* output */ + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_4, + output_height << 16 | output_width); + + /* no pixel/channel swap */ + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_10, 0x0); + + if (dual_input) + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_12, + CFG_11_10_1PI_2PO_MERGE); + else + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_12, + CFG_10_10_2PI_2PO_BUF_MODE); + + /* size in sram of inputs 0 and 1 */ + if (width1 != 0 && height1 != 0) + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_24, + height1 << 16 | width1); + + if (dual_input) + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_25, + height2 << 16 | width2); + else + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_25, + height1 << 16 | width1); + + /* merged size of inputs 0 and 1 */ + if (width1 != 0 && height1 != 0) + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_26, + height1 << 16 | width1); + + if (dual_input) + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_27, + height2 << 16 | width2); + else + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_27, + height1 << 16 | width1); + + /* 12 bit lsb off */ + mtk_disp_comp_write(dev, DISP_REG_MERGE_CFG_30, 0x0); + + /* unmute */ + mtk_disp_comp_write(dev, DISP_REG_MERGE_MUTE_0, 0x0); + + /* enable */ + mtk_disp_comp_write(dev, DISP_REG_MERGE_CTRL, MERGE_EN); +} + +static const struct udevice_id mtk_disp_merge_ids[] = { + { .compatible = "mediatek,mt8195-disp-merge" }, + {} +}; + +U_BOOT_DRIVER(mtk_disp_merge) = { + .name = "mtk_disp_merge", + .id = UCLASS_MISC, + .of_match = mtk_disp_merge_ids, + .probe = mtk_disp_comp_probe, + .priv_auto = sizeof(struct mtk_disp_comp_priv), +}; diff --git a/drivers/video/mediatek/mtk_disp_merge.h b/drivers/video/mediatek/mtk_disp_merge.h new file mode 100644 index 00000000000..4a91129711a --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_merge.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Mediatek Video Disp Merge Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#ifndef _MTK_DISP_MERGE_H +#define _MTK_DISP_MERGE_H + +struct udevice; + +void mtk_disp_merge_config(struct udevice *dev, + u16 width1, u16 height1, + u16 width2, u16 height2, + u16 output_width, u16 output_height); + +#endif From patchwork Wed Sep 2 14:15:54 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296691 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=GyqchZnS; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=AjzPlNTK; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCc1Zjzz1xwg for ; Thu, 03 Sep 2026 00:16:44 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id ADCEB80FFF; Wed, 2 Sep 2026 14:16:42 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id WaKOR6w6-ykf; Wed, 2 Sep 2026 14:16:41 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358593; bh=vPrPp/hOGE/dzlqVz9hrInXDQxvBE14zsaM8gFk/BNA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=GyqchZnS3WnNpFBnXxYYPq5/dD7Y4DxjW6+Tnz+8gC7a7Vjjk1RaTvXOtrVv012RW aDRqhR6CqeBeLG8TDTZf7omSm6PsK9ZrjCVFciieEno9fKxQlz65jqNmT+dxTczLo+ 6sJdnF3PlL5b3SxeR9kqJ7nOVCBZYOzX8yRM1mD5k9rceGSV8cMGsMhBpv4AOyUBI5 5zDbapF81NF0GRKoZNtFb02I6JVBdqKnZJcN1/V0iuvEvYI/aKbCxpIfv6So37Bcs1 qZSJ6ElWOjLyjks5PsanNOTWx0k00IShcDFSACz5fmtchlAuKsJzmDVS8KT2yujTP5 J86HLqENLWeyw== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 48B8480F62; Wed, 2 Sep 2026 14:16:33 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by lists1.osuosl.org (Postfix) with ESMTP id 71F70363 for ; Wed, 2 Sep 2026 14:16:26 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 3398C80EFB for ; Wed, 2 Sep 2026 14:16:26 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 1o0GF110dK39 for ; Wed, 2 Sep 2026 14:16:25 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::32c; helo=mail-wm1-x32c.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp1.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=AjzPlNTK Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by smtp1.osuosl.org (Postfix) with ESMTPS id 16F0480EF2 for ; Wed, 2 Sep 2026 14:16:24 +0000 (UTC) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-49b0dbfbf7bso7732775e9.2 for ; Wed, 02 Sep 2026 07:16:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358582; x=1788963382; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=vPrPp/hOGE/dzlqVz9hrInXDQxvBE14zsaM8gFk/BNA=; b=AjzPlNTKDXZeh9HRCgaJo462HMIHs3HBmlKXj1Dix66d1hjUWhwWyjjiPQ7OskyY/U 43/naVkwzH/S2Qxsx5PIazbwxeF71q+E9DZK9dQknIWPv1F3Vg+SboNnDRLvtyyFs3yD nSLvojpnS/0gbeaq+mzG/wu/F57TOP1pPBNFSPQXTLS3ZrUIRItywnwFoju7yD6joMvL dU1StozLDNTdaftARBqpGGDzGEbg7BiPhIv8uGkn4hsSr9fdy8ihF+gIuMq7CmdgTStI /Lt0tCAsryhcfez8EH7zJdSKQuL+tTzIAUrxXkmjYnbYYua88Gcy4emUSJR8fA8+RgcO ba6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358582; x=1788963382; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=vPrPp/hOGE/dzlqVz9hrInXDQxvBE14zsaM8gFk/BNA=; b=ZhhP+jVi7VNMizFe+Yn+YUb04ah06N7Jo/OcxcecNGv/zLFQf7Dm3QVgYZllZqoc+W U8y8dIdnyA97stbWpLWvzmaPcz5/MJyox7bAMegJqiwrCwzLYbJYipU5JCPOVCaXnoUx XukMj53buBFFhHezqXdWaq8uvV5Dz+ZrxtpZj5l8DsYC1Asn5H3oXriJtPqEGAiu7LEZ Q8nQvKX7d/aiy/Cy4sJE2rY1JZ6NwWMYDB+lkjvmit+yHyT4csZucD9dkbu8qY5zDA4Z TCbGh7yMwf/P6NWaBrq7ESGQD4ULwji4uDWEcn77nYfwzR0mAcCtnOO8R/M41kqZ5rGe XzeQ== X-Gm-Message-State: AFuF++lykAfew5BkAexET2gDsubm7nZOPd1HBeIWOMXjXj5mdjvTxiDX w7xXzypwin6Wrkm2zAwNhEIJCRQnNPSBw5ljLwdMrCWPPv0vF7kkJa/S2aBhrKOlqWU= X-Gm-Gg: AR+sD12Bi67/OmXk49e7gqEW0VJHZ2EH19l/QnKGbNV9LQthr37WoWC9KUvZOwLTTDI tlbaRIyHI0XtTuC/v2IGsqpkK5TuoDRSDoae2fuNuLEjnUc1PmsT7l5iw0SrMYbiva5KZE3rWHm 2EngFhGUgCRIuHfLJJgCc+lx5pxojAs6SVk8ST1d5L6FYJa3P2QLIw3wl1earCxC+zt6M8kOTe7 W+N02LoikZl8X0UfWDhImmI1GjlFpmE35B3krxWP0rv1LOneHpsI+880DKMEGGMCtjdJ+OMIKfi 6QI0u8uH72bU161NmMsDtbAyyqL4sibSv7lL1rglNzO7WzW/FzEvQBjTqK1axtVwxIezK7E3A9N cVXKzes5veIAvA3tpMpQiDeTSPYFjQtoGfqwLzzurugQVNu+K97pq5QP7J5KsLSfOn19CDLaXna kqfv4p4GzH89BzBWOVLDwQ9i+C8tbXAPsDXENOW9v6GluR1MeV+XakBI03Vde1nsDoSsAt4P18J SXbcVkHy+oJJm2p+7mUdCeXbgttCAWNlZsiasOeHgua95NXDcYnHYj1ZYdRpHZQ42ZLr9wpNWi1 H2WdTLhTDcNBT7LR6cj0gCs+smNEmYOcjhdb+7I9FYE+ X-Received: by 2002:a05:600c:4715:b0:49b:9161:db26 with SMTP id 5b1f17b1804b1-49ce5843bc0mr89487015e9.14.1788358582133; Wed, 02 Sep 2026 07:16:22 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:21 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:54 +0200 Subject: [PATCH v4 04/14] video: mediatek: add mutex component MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-4-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The display mutex synchronizes the components of the video pipeline on some MediaTek SoCs, such as the MT8188. Only the modules of the DPI1 pipeline are attached to mutex1; the module bit indices follow the Linux mtk-mutex driver (MT8188_MUTEX_MOD_DISP1_*). Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_disp_mutex.c | 67 +++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_disp_mutex.h | 14 +++++++ 2 files changed, 81 insertions(+) diff --git a/drivers/video/mediatek/mtk_disp_mutex.c b/drivers/video/mediatek/mtk_disp_mutex.c new file mode 100644 index 00000000000..d91d8472836 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_mutex.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Mediatek Video Disp Mutex Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include + +#include "mtk_disp_comp.h" +#include "mtk_disp_mutex.h" + +/* + * Register layout of one mutex instance @id (as in the Linux mtk-mutex + * driver): the block packs the per-mutex registers 0x20 apart. SOF holds + * the start/end-of-frame source, MOD0/MOD1 the attached modules 0-31 and + * 32-63. The offsets are index-based so a future DSI helper can drive a + * different instance/controller. + */ +#define DISP_MUTEX_EN(id) (0x20 + 0x20 * (id)) +#define DISP_MUTEX_SOF(id) (0x2c + 0x20 * (id)) +#define DISP_MUTEX_MOD0(id) (0x30 + 0x20 * (id)) +#define DISP_MUTEX_MOD1(id) (0x34 + 0x20 * (id)) + +/* + * The DPI1 -> HDMI pipeline uses mutex instance 1 of the vdosys1 mutex + * controller. Module bit indices are as in the Linux mtk-mutex driver + * (MT8188_MUTEX_MOD_DISP1_*). + */ +#define MUTEX_HDMI_ID 1 +#define MUTEX_SOF_DPI1 0x5 +#define MUTEX_EOF_DPI1 (MUTEX_SOF_DPI1 << 7) +#define MUTEX_MOD0_MDP_RDMA4 BIT(4) +#define MUTEX_MOD0_MDP_RDMA5 BIT(5) +#define MUTEX_MOD0_PADDING4 BIT(12) +#define MUTEX_MOD0_PADDING5 BIT(13) +#define MUTEX_MOD0_VPP_MERGE2 BIT(22) +#define MUTEX_MOD0_VPP_MERGE4 BIT(24) +#define MUTEX_MOD0_DISP_MIXER BIT(30) +#define MUTEX_MOD1_DPI1 BIT(38 - 32) + +void mtk_disp_mutex_config_hdmi(struct udevice *dev) +{ + mtk_disp_comp_write(dev, DISP_MUTEX_SOF(MUTEX_HDMI_ID), + MUTEX_EOF_DPI1 | MUTEX_SOF_DPI1); + mtk_disp_comp_write(dev, DISP_MUTEX_MOD0(MUTEX_HDMI_ID), + MUTEX_MOD0_MDP_RDMA4 | MUTEX_MOD0_MDP_RDMA5 | + MUTEX_MOD0_PADDING4 | MUTEX_MOD0_PADDING5 | + MUTEX_MOD0_VPP_MERGE2 | MUTEX_MOD0_VPP_MERGE4 | + MUTEX_MOD0_DISP_MIXER); + mtk_disp_comp_write(dev, DISP_MUTEX_MOD1(MUTEX_HDMI_ID), MUTEX_MOD1_DPI1); + mtk_disp_comp_write(dev, DISP_MUTEX_EN(MUTEX_HDMI_ID), 0x1); +} + +static const struct udevice_id mtk_disp_mutex_ids[] = { + { .compatible = "mediatek,mt8188-disp-mutex" }, + {} +}; + +U_BOOT_DRIVER(mtk_disp_mutex) = { + .name = "mtk_disp_mutex", + .id = UCLASS_MISC, + .of_match = mtk_disp_mutex_ids, + .probe = mtk_disp_comp_probe, + .priv_auto = sizeof(struct mtk_disp_comp_priv), +}; diff --git a/drivers/video/mediatek/mtk_disp_mutex.h b/drivers/video/mediatek/mtk_disp_mutex.h new file mode 100644 index 00000000000..78163e67df1 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_mutex.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#ifndef _MTK_DISP_MUTEX_H +#define _MTK_DISP_MUTEX_H + +struct udevice; + +void mtk_disp_mutex_config_hdmi(struct udevice *dev); + +#endif From patchwork Wed Sep 2 14:15:55 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296692 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=JuThQxko; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=i9/OCOUf; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=140.211.166.138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCg1gr2z1xwg for ; Thu, 03 Sep 2026 00:16:47 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 89B2B80F1F; Wed, 2 Sep 2026 14:16:45 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id dAOs_mnwFnKO; Wed, 2 Sep 2026 14:16:44 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358594; bh=hss58b9cl4NnfeSl8E9355QiZ+V5FZb1XDQvYAo2Vis=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=JuThQxkoqtffZuch+1a3RO0NSIJi3Vwf7eRLF8A+BfRcbTHT2Hp1FqTkdIwt/a+3O iKHM/SI7eSNa7Wa9K5xBmVP6CxYBrjwVYmDFjj/xqW2uKPtHEuH5R+zel8imQAJ+Sg 5YsKCMV4RYHvge3dG9H6HK46eECvs0PrdFH7o6+f+g5FthXd++mNlRTFQhnmZ8PofF 37e2mt6z8QzlFQv6J2jKasSxMOGVMA6e2OhCCt51FNGy+bOfYT9EY5D0JmrR+cXboy u7bf8tRGyft7ZFdC/stC4rxGfQWb7WG1unkwzDG55I/IsVXA9mF2rCPPGpwfkb17NS pKczAy63P3jUg== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 6192B80F6E; Wed, 2 Sep 2026 14:16:34 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists1.osuosl.org (Postfix) with ESMTP id 0F9E2230 for ; Wed, 2 Sep 2026 14:16:27 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id EA5B1606CF for ; Wed, 2 Sep 2026 14:16:26 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id zLNUyDqURfh9 for ; Wed, 2 Sep 2026 14:16:26 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::32e; helo=mail-wm1-x32e.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp3.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=i9/OCOUf Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by smtp3.osuosl.org (Postfix) with ESMTPS id 0C41D606B4 for ; Wed, 2 Sep 2026 14:16:25 +0000 (UTC) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-49cca4ffdcfso7756555e9.0 for ; Wed, 02 Sep 2026 07:16:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358584; x=1788963384; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=hss58b9cl4NnfeSl8E9355QiZ+V5FZb1XDQvYAo2Vis=; b=i9/OCOUfKwmWvJyCvLGi30cyBn/idrFa//XIDzdC1CTaCC3s6z7+RPWe/QrZVJ8gvZ tQVoC7lJTj+MBSg/AT5RxeuUxlEuvvHVtNbQuUCUu1XYYc+CcxrkE8yBEXaB0QzNEkLU JkTq+RMIDnx7EI/QCNuxBwQYUrsmcuXycVUS6VQFmS6a5Ck2DaNKX3qBgAOUPtY7ghp1 mBPGejTf9qGm39pvDw9KzOFl5EFMDkxK3zYLMJRhy0wMlbHvHRwmoPe93qapXrKJOZcP 5CMWBBj6olO+C8MCA++KOFk5da25eV0t0ZodQ2khdbWfukFxUWETzquw3xcOptFTt0kt 6RIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358584; x=1788963384; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=hss58b9cl4NnfeSl8E9355QiZ+V5FZb1XDQvYAo2Vis=; b=ZRMpIep/BIXamKa+1bI6ehzTQyQxEeZL/rEUL1C6c0017VwTqZUXF9nCO8W+ID82Pp A5KUhRzqO3qfQsun6vQv518U2XyAeh9Z1my5F5+rSfmrP50pyN2MaIqRZo4xjLPDHAj1 PF5DvoSsjgWm8CKpdKAUBKGnrRke/lT+g6FQ8m3iZjll+N8lXodqyqDZkNsXVeI3kYk5 BO/wBus2WDE8po2GtIac8dZyPqHR53vdJVkLz8uEU8eC9cYMiNqWK+/Q/OWeKVFrBIBy QtjOSWNu75fyvxSEm+LcVtwyN3c1VgdaUsNZj/PQe29AKvB4NYzVTye21sXRiiQgDrjT LQPw== X-Gm-Message-State: AFuF++mmzxW/CZ/bONqHK9GbR2Ulh0EXmPeLo5lIWF0jd7i+Rznykn5/ 7hQaT01jl0gU8KQPyUQ2bUMs8J1rPoJlhvCxWXxDeWDgpdPV9/IXMKJl5FN8By3N0bg= X-Gm-Gg: AR+sD12ooadBHKbdCId0dXzDwwPhI5SLExr+AkDKEVZRrWUfsjq8DRIaIZNmkpr0qHt 7eOlBBXSyKPoKwLmErsCreK7JmA24L4KNBLGHwtrynNNmRAOle1CGUXrlNDK4bde72m8zTUavjG 1Pl4axjkHNVJbF1ZR0ZPFSA99bq1a47Tb7ph4qRmfvV254qV6sPhJuaQPBq2uQsEeabERijaNTk CLqHKanIw7FPh90yfEcsyGBqzK9A/UMyngIGwAF/vUwGnJRFYmWNXA1ZIUQM5L6SmW7ppjzsUw/ vfwhlekB23VihPV+cWuCag+vwuG7kkI3IQRzE06jICGfOjJaazkiR9MWUcCySCr+6c+3KQH72Fm 2FKoB4XM+8QCp59o6fH51DtjK4MAUeoH0M/MFvbLoQinBfIwON8RdkMUGXluZcG/JWKPgoq5VWO 255nJWQRcxl3iP5EKx53S9K2mqLW1RQrxOwCO39UC1VPHcwavpaobKAA8dP6iLD8VoN8TBbKmdo Xcjto5mfc6VfsZRAuUW0dWks3CRxfKHx9TcFyOzeD7RtjhLapADAPdDToEh4Z6kf0bn/qwvzEEt GRTsFa6vgZVC1S/2/tg8aQ5oQXNn8Iavh8wV1Bif6zcG X-Received: by 2002:a05:600c:1f83:b0:499:dc34:bdc with SMTP id 5b1f17b1804b1-49ce580a5cbmr95416275e9.1.1788358583661; Wed, 02 Sep 2026 07:16:23 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:23 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:55 +0200 Subject: [PATCH v4 05/14] video: mediatek: add padding component MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-5-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The padding block is one of the components of the video pipeline on some MediaTek SoCs, such as the MT8188. It is configured in bypass mode. Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_disp_padding.c | 40 +++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_disp_padding.h | 16 +++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/video/mediatek/mtk_disp_padding.c b/drivers/video/mediatek/mtk_disp_padding.c new file mode 100644 index 00000000000..4a69670bff2 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_padding.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Mediatek Video Disp Padding Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include + +#include "mtk_disp_comp.h" +#include "mtk_disp_padding.h" + +#define PADDING_CONTROL_REG 0x00 +#define PADDING_BYPASS BIT(0) +#define PADDING_ENABLE BIT(1) +#define PADDING_PIC_SIZE_REG 0x04 +#define PADDING_H_REG 0x08 /* horizontal */ +#define PADDING_V_REG 0x0c /* vertical */ +#define PADDING_COLOR_REG 0x10 + +void mtk_disp_padding_config(struct udevice *dev) +{ + mtk_disp_comp_write(dev, PADDING_CONTROL_REG, + PADDING_ENABLE | PADDING_BYPASS); + mtk_disp_comp_write(dev, PADDING_PIC_SIZE_REG, 0x0); +} + +static const struct udevice_id mtk_disp_padding_ids[] = { + { .compatible = "mediatek,mt8188-disp-padding" }, + {} +}; + +U_BOOT_DRIVER(mtk_disp_padding) = { + .name = "mtk_disp_padding", + .id = UCLASS_MISC, + .of_match = mtk_disp_padding_ids, + .probe = mtk_disp_comp_probe, + .priv_auto = sizeof(struct mtk_disp_comp_priv), +}; diff --git a/drivers/video/mediatek/mtk_disp_padding.h b/drivers/video/mediatek/mtk_disp_padding.h new file mode 100644 index 00000000000..f3cdd363b12 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_padding.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Mediatek Video Disp Padding Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#ifndef _MTK_DISP_PADDING_H +#define _MTK_DISP_PADDING_H + +struct udevice; + +void mtk_disp_padding_config(struct udevice *dev); + +#endif From patchwork Wed Sep 2 14:15:56 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296694 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=fRl1vc71; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=e4wvVsxx; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCr26dlz1xwg for ; Thu, 03 Sep 2026 00:16:56 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id C476681091; Wed, 2 Sep 2026 14:16:54 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 3BZ8zRrrVGSc; Wed, 2 Sep 2026 14:16:51 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358596; bh=TYbH7Yvqx4Xzn3A6hWlADgx9tQ+OxPuD7z6Kbn9niMY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=fRl1vc71lH1KXVfML5hnXbBNDhrQMeIV+Z2AFNz5EW0xL6b31MyV0GNVUp0h+9Xi6 g5Ew9PUG84jk+PrYxHxzVlBk0P1n7G0otmWEcTpXjTYN7BWAW4cuMDBFI1WxGbPKhu B+5f/tqg8FZOD8t3QVZxjktkIaVHMhNBrQrqRjuvXKT5KEPX4OZsxfSEDLKIhVEmuY zw30mBzN7hcaIus2cbzIIJ3mh8SW1kb3xgqz1Ne7fXj9atUtRg8xZEksfe2nMJP339 6Zsnd/SDlNu53uJza848yMjCF5TFrenJXg5sklbRn5PUDd4M4bfFWJgiWuLUK8Cl9k AnjatLjM33Paw== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id AD53180F7C; Wed, 2 Sep 2026 14:16:36 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [IPv6:2605:bc80:3010::136]) by lists1.osuosl.org (Postfix) with ESMTP id A68121D9 for ; Wed, 2 Sep 2026 14:16:30 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 9857D606C4 for ; Wed, 2 Sep 2026 14:16:30 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id LbMPYuazL7B0 for ; Wed, 2 Sep 2026 14:16:30 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::32d; helo=mail-wm1-x32d.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp3.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=e4wvVsxx Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by smtp3.osuosl.org (Postfix) with ESMTPS id 7FDB3606B4 for ; Wed, 2 Sep 2026 14:16:28 +0000 (UTC) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4957eefd361so7401775e9.1 for ; Wed, 02 Sep 2026 07:16:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358586; x=1788963386; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=TYbH7Yvqx4Xzn3A6hWlADgx9tQ+OxPuD7z6Kbn9niMY=; b=e4wvVsxxsIpW8CEd9IQ2Bsnnn5kexiajI/5CNhJxzzrxneRkpl6En21fsQdQvhp8H2 MC2HJ+CrPaxQ/nyxNX4qaOI95uMqD3vdRdI07/T1AEShL+ZBZc4mR8DYrC79kRDwsNOa lnsICOqn5gjdjAhzeMezVEepA09bO0R0QGAwwZHpV+N79bEJZ1J8Hw+0anMknQy324O3 Y0SwPjaxIqffZcm0HK0Cb3RzJCS0YviARCZ3O5NkKLu0AUAXUZrOP9nrI9JqgwBltwy4 qK+0m4SKrbQ9irPRlNWHR/fCMv/QGR0NjmBtTwQDrZ2qV3Mg9sAT6HMzW4vOim2EWV/A djow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358586; x=1788963386; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=TYbH7Yvqx4Xzn3A6hWlADgx9tQ+OxPuD7z6Kbn9niMY=; b=I2lAVPEt2orF+ugFqnpdkdC/cOBIUNIUMd4TNEUHEUhEMdX+RJtaNSbtPtNS57VGsn zc4jRbEwQGEmVOoJWm7x8QtFAN422aoCXxUKklB05By9kWqCdsPMjd+PHdxJkOAGrLrT loSDcPV7IZqapUN3m5K8s0ohMSdyIws/DBDcnFRDuHc/haD2jckWOWHvWsppuO3MqSVW O4rWfP3GYyXf4pSIXib1BLH/L/m9dvXLVGXd2ABvFKqZs2ichhiIIwfT3p58ZJ0DzyCJ M0PezmQUfZoXxJAKZx0rn7SiCoWRgVcV0rKZHnqyFhD3CcRkeGdKplQN8JIb+F4A4Mph xUbw== X-Gm-Message-State: AFuF++l68kknCWhEhyoAqOWpsFM7NUQjLVGTVoXnA6CotP+aO+Jtrltm NCw/futxbKHlpoV3hIbCv+huvGrpV8pAi41IbgRkmJohRBj4A9DXCIJqr3giBrwLwVs= X-Gm-Gg: AR+sD12qThPeV8tSB6XmpUc40UUcj/CsEi37Lgxm4NqbGfIsx7vuab3ghqi8fsVV7Yt 90l0GuST6ljR0o9cMnS3bXG9OvtP3F/weclbnRzjvmGICu/jQzuqvssDpNEFqr8xZavHxhoKDmR L3e6H+qtuMiWRfjcUbbefnnZi0zHPxJs6LDRV0Q3a0bg/5JWA2uZ89ZrrwU8PWgWO31vYyaJjAD AB7F7XlXCI0nkHvGnW6vS0Fw1ixu9LqadvTUkeNQwyliTnSIEuEBQokQfd3v67xNOGIgehDIbQ3 Upyx/pZCKEN43flk8rXwKGOUBlEcIRb3clXgAi/vbwiJmQpOqLl7iMgLIvEasmfbLlPODHSxJmV CQfNj/UB7fh6pHKtBJfobUik5OvYT7KGflceNxp+BP0WXE+oyUU46khMOFAK/j1L8Hbg6fmcsfJ //Cc9Bo2E9DTrDN3bopqcNVNXir1H7l2x7Eh9dOniNiYNLt0B419BQPrnXltTCJYV+xzTZTImt0 yZRwdt59kuOYol2QSlmrcZhqb3VdZNX7pG/X+kH3raxY2Nkv8r7L3+y2H7Rsb4xZmfFWmZ35/Jy BxiFUD2QRw4Te8sGO25H5AG76B812TYM6OXIZ3lAQ95Y X-Received: by 2002:a05:600c:4f0b:b0:493:bd2a:93be with SMTP id 5b1f17b1804b1-49ce581316dmr74910075e9.6.1788358586459; Wed, 02 Sep 2026 07:16:26 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:24 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:56 +0200 Subject: [PATCH v4 06/14] video: mediatek: add rdma component MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-6-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The MDP RDMA is the DMA engine reading the framebuffer on some MediaTek SoCs, such as the MT8188. Two instances are used, each reading one half of the frame; the second one starts at the middle of the line (apply_offset). Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_mdp_rdma.c | 159 ++++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_mdp_rdma.h | 20 +++++ 2 files changed, 179 insertions(+) diff --git a/drivers/video/mediatek/mtk_mdp_rdma.c b/drivers/video/mediatek/mtk_mdp_rdma.c new file mode 100644 index 00000000000..f954f197985 --- /dev/null +++ b/drivers/video/mediatek/mtk_mdp_rdma.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Mediatek Video MDP RDMA Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_comp.h" +#include "mtk_mdp_rdma.h" + +/* MDP RDMA registers (see Linux drivers/gpu/drm/mediatek/mtk_mdp_rdma.c) */ +#define MDP_RDMA_EN 0x000 +#define FLD_ROT_ENABLE BIT(0) +#define MDP_RDMA_CON 0x020 +#define FLD_SIMPLE_MODE BIT(4) +#define MDP_RDMA_SRC_CON 0x030 +#define FLD_OUTPUT_ARGB BIT(25) +#define FLD_UNIFORM_CONFIG BIT(17) +#define FLD_SRC_FORMAT GENMASK(3, 0) +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 +#define MDP_RDMA_MF_SRC_SIZE 0x070 +#define FLD_MF_SRC_H GENMASK(30, 16) +#define FLD_MF_SRC_W GENMASK(14, 0) +#define MDP_RDMA_MF_CLIP_SIZE 0x078 +#define FLD_MF_CLIP_H GENMASK(30, 16) +#define FLD_MF_CLIP_W GENMASK(14, 0) +#define MDP_RDMA_SRC_OFFSET_0 0x118 +#define MDP_RDMA_TRANSFORM_0 0x200 +#define MDP_RDMA_SRC_BASE_0 0xf00 + +/* Fields/values used by this driver but not present in the upstream driver */ +#define FLD_INTERNAL_DCM_EN GENMASK(23, 4) +#define MDP_RDMA_SRC_FORMAT_BGRA8888 2 +#define FLD_BITEXTEND_ZERO BIT(15) +#define FB_BYTES_PER_PIXEL 4 + +int mtk_mdp_rdma_config(struct udevice *dev, struct video_uc_plat *plat, + const struct display_timing *timing, + unsigned int pitch, bool apply_offset) +{ + u32 width = timing->hactive.typ; + u32 height = timing->vactive.typ; + int offset = apply_offset ? ((width / 2) * FB_BYTES_PER_PIXEL) : 0; + u32 fb; + + /* the RDMA source address register is 32-bit only */ + if (plat->base != (u32)plat->base) { + dev_err(dev, "framebuffer base %pa is above 4GB\n", &plat->base); + return -EINVAL; + } + fb = plat->base; + + mtk_disp_comp_write(dev, MDP_RDMA_EN, FLD_INTERNAL_DCM_EN); + + /* set source format and output bit depth */ + mtk_disp_comp_write(dev, MDP_RDMA_SRC_CON, + FIELD_PREP(FLD_SRC_FORMAT, MDP_RDMA_SRC_FORMAT_BGRA8888) | + FLD_OUTPUT_ARGB | + FLD_UNIFORM_CONFIG); + + /* set base address */ + mtk_disp_comp_write(dev, MDP_RDMA_SRC_BASE_0, fb); + + /* stride comes from the framebuffer line length */ + mtk_disp_comp_write(dev, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, pitch); + + /* + * each of the two RDMAs reads one half of the frame: size and + * clip cover half the width, and the second RDMA (apply_offset) + * starts at the middle of the line + */ + mtk_disp_comp_write(dev, MDP_RDMA_MF_SRC_SIZE, + FIELD_PREP(FLD_MF_SRC_H, height) | + FIELD_PREP(FLD_MF_SRC_W, width / 2)); + mtk_disp_comp_write(dev, MDP_RDMA_MF_CLIP_SIZE, + FIELD_PREP(FLD_MF_CLIP_H, height) | + FIELD_PREP(FLD_MF_CLIP_W, width / 2)); + mtk_disp_comp_write(dev, MDP_RDMA_SRC_OFFSET_0, offset); + + /* simple mode + zero bit extension for 8bit -> 10bit */ + mtk_disp_comp_write(dev, MDP_RDMA_CON, FLD_SIMPLE_MODE); + mtk_disp_comp_write(dev, MDP_RDMA_TRANSFORM_0, FLD_BITEXTEND_ZERO); + + /* enable engine */ + mtk_disp_comp_write(dev, MDP_RDMA_EN, + FLD_INTERNAL_DCM_EN | FLD_ROT_ENABLE); + + return 0; +} + +/* + * The RDMA is the DMA master, so the SMI larb feeding it must be ungated for + * its DRAM access. The RDMA points at its IOMMU (M4U) port through "iommus"; + * MTK_M4U_TO_LARB() extracts the larb id from that port. Resolve the matching + * larb in the IOMMU's "mediatek,larbs" list by its "mediatek,larb-id"; the + * component helper then enables and disables it together with the RDMA. + */ +static int mtk_mdp_rdma_get_larb(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + ofnode iommu, node; + u32 larb_id, id; + int i, ret; + + ret = dev_read_phandle_with_args(dev, "iommus", "#iommu-cells", 0, 0, + &args); + if (ret) { + dev_err(dev, "cannot parse iommus: %d\n", ret); + return ret; + } + iommu = args.node; + larb_id = MTK_M4U_TO_LARB(args.args[0]); + + for (i = 0; ; i++) { + node = ofnode_parse_phandle(iommu, "mediatek,larbs", i); + if (!ofnode_valid(node)) { + dev_err(dev, "no larb %u in iommu\n", larb_id); + return -ENODEV; + } + if (!ofnode_read_u32(node, "mediatek,larb-id", &id) && + id == larb_id) + break; + } + + return uclass_get_device_by_ofnode(UCLASS_MISC, node, &priv->larb); +} + +static int mtk_mdp_rdma_probe(struct udevice *dev) +{ + int ret; + + ret = mtk_disp_comp_probe(dev); + if (ret) + return ret; + + return mtk_mdp_rdma_get_larb(dev); +} + +static const struct udevice_id mtk_mdp_rdma_ids[] = { + { .compatible = "mediatek,mt8195-vdo1-rdma" }, + {} +}; + +U_BOOT_DRIVER(mtk_mdp_rdma) = { + .name = "mtk_mdp_rdma", + .id = UCLASS_MISC, + .of_match = mtk_mdp_rdma_ids, + .probe = mtk_mdp_rdma_probe, + .priv_auto = sizeof(struct mtk_disp_comp_priv), +}; diff --git a/drivers/video/mediatek/mtk_mdp_rdma.h b/drivers/video/mediatek/mtk_mdp_rdma.h new file mode 100644 index 00000000000..86297e42341 --- /dev/null +++ b/drivers/video/mediatek/mtk_mdp_rdma.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Mediatek Video MDP RDMA Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#ifndef _MTK_MDP_RDMA_H +#define _MTK_MDP_RDMA_H + +struct udevice; +struct video_uc_plat; +struct display_timing; + +int mtk_mdp_rdma_config(struct udevice *dev, struct video_uc_plat *plat, + const struct display_timing *timing, + unsigned int pitch, bool apply_offset); + +#endif From patchwork Wed Sep 2 14:15:57 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296697 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=FHGjBjAo; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=NyU2hqdn; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=140.211.166.138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlD051Y3z1xwg for ; Thu, 03 Sep 2026 00:17:04 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 563FE80F33; Wed, 2 Sep 2026 14:17:03 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id k5u9QF79737i; Wed, 2 Sep 2026 14:17:02 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358606; bh=E/0zfH+b/PORYmHDK+GsBzrZ+B993FwrMyo2sncncqU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=FHGjBjAokbFF8v3rjGN1Z+jbwCJNbO8HkCMzEn59TF0zpxkvgZ+rucNU1GtyUNo4/ pJ1n10mSUEmRKvr6s5F0GCF7rB6gFDiu3I1S6AErkQ2g6aYMLb8r2QGB/SwB8bV7dl 8CTOIgf3OFLnYeP/xETnkaUjXUXfTddooayJZC9ryJTIwZ/ZahawxP5BHWacXc/pmN KdoHS8/lnAwhpb5AaQW0b0kYFYjDT3e0aHHrqf2UfOjnUqv8bktrcdTTECXcz6yGIT g9+wF83wb4nAPfm2BzofVjTx3Gz+DpM3gg1md4vuV61MxH90dyzuJsEYyWA1q/qK0L HNIJ9T/I5whhg== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 981E680F6B; Wed, 2 Sep 2026 14:16:45 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by lists1.osuosl.org (Postfix) with ESMTP id EF7BB465 for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id D3DFE80FA9 for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id KdPUKpvvwdsT for ; Wed, 2 Sep 2026 14:16:38 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::436; helo=mail-wr1-x436.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp1.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=NyU2hqdn Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by smtp1.osuosl.org (Postfix) with ESMTPS id 395CD80F59 for ; Wed, 2 Sep 2026 14:16:31 +0000 (UTC) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-482f9309813so1115928f8f.1 for ; Wed, 02 Sep 2026 07:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358590; x=1788963390; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=E/0zfH+b/PORYmHDK+GsBzrZ+B993FwrMyo2sncncqU=; b=NyU2hqdn8N9GzLQoHX4X8iBHMKXYzsxR130OxFzcJVpKnv2ZqfEjH0LnQiE1dD40kZ IVdlfpTMcrqsX2WHOLO82zJR2DZWBEAEwf6AVNT+jrkj46B61nLYmi0CuELBth9osn19 quVTNl/saihKcvEBzWqjM58ZzH3IGksYxWMaWQxfKodPVDSHkHdovLKy9w0FksRREibC QgMMmBSn8ax+WJLlfZC6LWTLwD+d5n39HoGdk2sBgCsBt9UeFM+qV6oiBVaxfPoXKe41 6vJgHTvSynXm0d8I/DZkVVwsaEGvU1f6gJVJme6g0KTvI64uG8/17I1zftCYJYTS3vLR tE5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358590; x=1788963390; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=E/0zfH+b/PORYmHDK+GsBzrZ+B993FwrMyo2sncncqU=; b=UDWrV730YZSXYeFpUice7YJhHgl1a8wpLggpKWh0a6KUiyAxpuRnEbZ7X3jOWSWkER aqgzACfrV6bboN/Y2rH/X9Gg/PUR1tAqbvAGlW/sFG/LOKJeVRys0PcyHKRL261l61ms xbLs8lHCCHKD85DypfOnVhJVuQvH6llh9YHSn9Ez/ZZ8CwUNuTwnnQt3z79wZJdnEvtt dkzbwYCzwN6unnujXD8GAUfdMP4yVQmm5sNIqui2yND6iNqjukRRMT4eOSbJU12+f5F/ WtCdFG2rX3txHvP/3WMIWZv26I32ShPcjZFv5pgFhtZ3phvWogPv4Pd6UzZc4ryfRGu8 BM0Q== X-Gm-Message-State: AFuF++luOeh45Mjq3sTUZq8YtV5I+5IKQ/uysQMtKW64fSQe12D8WYWV a+1XWi8qDjqhK250qQniWRq7Fi9FO8lUfcs5X0F184vj1QEZs1xGSw0kx//Lskq8r6o= X-Gm-Gg: AYBFou2KYyto55Oqr1KoEgJgQ4dUvUsNxatZAwPbC1B9b9/gGtJnm8bVfHSIJSfXmkb 9xkCxeFlj3E0h2xeuB8QPX9uQ9Xe9sA3ISAuwnwTeCT8rDmSTaneYvLXaIr89bEy0ITcDlyMx94 SmCbMRysz8fgx3z1JqGkFQzX/4WxaQyhOKWRuG9D7HRxuDkOW89/ZtYesALx0gUeQz4Tq+blrbD /8mGGfKG2CYKS3hgDutPm+/Hko703HNsAxtn0poD1bIAd+d+jdaJr2dNwIBeUYZfygFP+76q006 qRnhTZJSXVRweWMzZUBQUzrIM16KPOGDikuZLshCT9gtRkKNIAUZtZueHjBwNvBHvN5bnO9GVCU AiHr0q7mz2Q+CoJ/rzogbOt1XvkJ66hW5a504prSrmoPO1PSbK4O6X7owptTWkUmNuLz2x63Gu0 IAktrnc0PEKCKbrLhYDqivgdS2LyHJLx1kRKWqwhiVw06CgM9ELBfCgX0YXBLfzl2ADOVMEZt3S +/5tHcMpAAf+IlK/lD7aEx6PInEVlJfBMPZiO7uIhyZ6k2uBg6p8tquOug0+/gtrxpQoKf4TzJU oqT+6OAVxalzVOhtib1QJaQJi9o7ZRiHjUaL8N2AsdvY3g== X-Received: by 2002:a5d:5f45:0:b0:47f:c648:e280 with SMTP id ffacd0b85a97d-484913b8052mr9121610f8f.18.1788358589840; Wed, 02 Sep 2026 07:16:29 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:27 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:57 +0200 Subject: [PATCH v4 07/14] video: mediatek: add smi larb driver MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-7-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The SMI local arbiters (larbs) gate a subsystem's access to DRAM. On the MT8188 the display data path feeds through the VDO1 larbs (larb2 and larb3), whose clocks must be ungated for the HDMI pipeline to reach the framebuffer. There is no dedicated SMI larb driver upstream, as Linux handles the larbs through its SMI/IOMMU framework. Add a minimal U-Boot driver that binds the "mediatek,mt8188-smi-larb" nodes and ungates their clocks, reusing the display pipeline component helpers for the register window and clock bulk. Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_smi_larb.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/video/mediatek/mtk_smi_larb.c b/drivers/video/mediatek/mtk_smi_larb.c new file mode 100644 index 00000000000..9e4440ce294 --- /dev/null +++ b/drivers/video/mediatek/mtk_smi_larb.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MediaTek SMI local arbiter (larb) driver + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include + +#include "mtk_disp_comp.h" + +/* + * The SMI larbs gate a subsystem's access to DRAM. They have no dedicated + * driver upstream (the SMI/IOMMU framework handles them), so bind a minimal + * driver that just ungates their clocks, reusing the display component + * helpers for the register window and clock bulk. + */ +static const struct udevice_id mtk_smi_larb_ids[] = { + { .compatible = "mediatek,mt8188-smi-larb" }, + {} +}; + +U_BOOT_DRIVER(mtk_smi_larb) = { + .name = "mtk_smi_larb", + .id = UCLASS_MISC, + .of_match = mtk_smi_larb_ids, + .probe = mtk_disp_comp_probe, + .priv_auto = sizeof(struct mtk_disp_comp_priv), +}; From patchwork Wed Sep 2 14:15:58 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296702 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=by0m87KQ; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=OxPTlOUj; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlDF0Nxmz1xwg for ; Thu, 03 Sep 2026 00:17:16 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 0DDAB810C9; Wed, 2 Sep 2026 14:17:15 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id JdsqCn7UbLYq; Wed, 2 Sep 2026 14:17:10 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358613; bh=vtJ+uzQL91WeRZPB5zvm+3QfYldiJZ8oazhnz7Ck+OY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=by0m87KQ+kEzH9dnVCcpFPWe7sKROHwW0zoSHJHuuwX1lbjQ4NBH7IbubbuZgbSuX L/rP/soA3wqFmSzJt+fxSXH42fAdNYf9RUMdkQjPGHNxWT9rcT99rlJAzY0961hMJG jd5X0Ccx2o+ZEzuPBfzBMXllMlFmdA3MWwMZGAapf/cp132pnAkIsMMNXGMsNkNDbB GJ+DdEEHerbSeBHnasSgBf6wm5IG7C59OVkDWN3ZZReQp6TYd2WO/jIp0fVac1j/qc sEUc8dWkzh1FklUiwa+OS1TuNspphy23SWHQ0cHrJPAkmXSKuzvvlSzzBfEAfBZUyB e/BhG+Aw97dNg== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 6100581090; Wed, 2 Sep 2026 14:16:53 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) by lists1.osuosl.org (Postfix) with ESMTP id E1C011D9 for ; Wed, 2 Sep 2026 14:16:48 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id D21D78104F for ; Wed, 2 Sep 2026 14:16:48 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 2KYoBl41esxF for ; Wed, 2 Sep 2026 14:16:44 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::429; helo=mail-wr1-x429.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp1.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=OxPTlOUj Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by smtp1.osuosl.org (Postfix) with ESMTPS id 2C02080F6A for ; Wed, 2 Sep 2026 14:16:33 +0000 (UTC) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-4843efcbdb2so744831f8f.2 for ; Wed, 02 Sep 2026 07:16:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358591; x=1788963391; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=vtJ+uzQL91WeRZPB5zvm+3QfYldiJZ8oazhnz7Ck+OY=; b=OxPTlOUjrjFv5UKTXBBoqGbUFeZUiDQppW2Q3lKEEu+q5zCE9twDLLvq7DlU8EqkCn pQKUW9Qp6jjn2ytKRkXGYNrQOBDVXTP0yupwekvwdzz50e4Dciibh+jy7k7V0TPaSlgG Cmb4C5mg3WFCjHvfQdZMYcqyrjLWk5V/r9v8161/KmU+4bFwTUsHTTrFUbSAcz44SgJ0 6cxIMlvgemNW9f+k8Esa2e9fteGapvLlchTBlBQzvGD0sR394jn+FJP8uhzQzeKnt0nm rkVswNgME7mQSRU2RocJ7Rv/AgK0TTVfONd3cgSn0OZfqlG3j29OhA/KSJoXCj1477oc pvpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358591; x=1788963391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=vtJ+uzQL91WeRZPB5zvm+3QfYldiJZ8oazhnz7Ck+OY=; b=Uqm1H7WL6rGRulegCEF824woHkuR1XhK3lOR0n9d2Hi2G7IC/ShpnTjnVNQbhYAB0r 27fhJmR47ukk6+zb9nniRfu717dYHaVltGC1apMwRiK7toqUYo3rXOs3bTuO2LUpqp09 NmXZb+u90FoGH5jVE6b2Qe6ibDkwmiNUvZfQOpVgUspdaJu7XunnfI9GpiTicqhaQ3y1 ivEUb+wvjD7+HRgRm3SLKD9+Kp10YjDwNQdL4/IYCCrj9jzuM4058Kb8DnLCXQoSBcz5 0BXGnM2/zo6LLLF44XRYtek/hdH2KvUPuDlsRQzngxGwZIWaLHWLCxfrsNmhjJsM5OAW JPNw== X-Gm-Message-State: AFuF++lLZWMSwAJceX/bipdogurU/y9BQinwG3dowY39aIKQU4frZUvU cExu20IZVEcXpSi2Y6Lnn6Fv1AeWdGLfrwN5UaxqLazvbXbCgQRpPFK/lcwanTKX4KU= X-Gm-Gg: AYBFou0ZNrCZA4zhoGb3Sr5TXhej9HN/tTbMB+78KDbbwl6yiZh0sZ12HUHAwqSUDll NxBKy9Ub5jTwcVHa9vhyrT3FpUks38TzJ8A2SuP/kkLONgv+54t41xFGL7wTJpaD/fJ/DNjXKi8 PmBMfPYnCrGWYR7EiXAsKo8/8PIlcysgkaFF4/uVRJr5Rd14uV3/wNUcsKpsQVtd06Ds6ym0Owg CPNGXviIDrYKwtIHWWN762QueP+Pk4288/p/ywDapjSP4DMm3KLskyNNNuGqT+6KY87Yiyz8gni w1vazNjwdKuR+kGchUvmiLM+gcI0L3mCmGT+5/fJUjsbzmg/2nF+XAYIrQMJVuD9MIk5+LppLXD /1lPQMVKKWBM43cEHoh6dX4c5YmGX5s2TUY7BGEBmF1L4awhMT5hBx7ib4vZNxzVVFrRtWqWRGi Ck+jj0CBuZ6zdQruhLynTDZ4+MdiR7BVmDggkUVsFn7YJfpOQ/OZyb3gyEz6DgEUwzAE8lc46He tNyeIuLJWfoMNOjl1EopkEBj/jXdpb/VLmFA0JWBfLo54yrM1lu4x6CoOx7oVuga3Gp6Rmk1dlh NsMzlawiPzvAgNsRvoiC9yOpkJfWNWH+c4tCKhxEEFCD X-Received: by 2002:a05:6000:268a:b0:481:5b58:c589 with SMTP id ffacd0b85a97d-48488f0e30emr9584821f8f.10.1788358591028; Wed, 02 Sep 2026 07:16:31 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:30 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:58 +0200 Subject: [PATCH v4 08/14] video: mediatek: add dpi1 component MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-8-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org DPI is one of the components of the video pipeline on some MediaTek SoCs, such as the MT8188: it is the timing generator interface feeding the HDMI TX. Sync polarities, porches and the interlace mode are taken from the struct display_timing selected from the EDID. Signed-off-by: Julien Stephan --- drivers/video/mediatek/mtk_dpi.c | 383 ++++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_dpi.h | 20 ++ drivers/video/mediatek/mtk_dpi_regs.h | 247 ++++++++++++++++++++++ 3 files changed, 650 insertions(+) diff --git a/drivers/video/mediatek/mtk_dpi.c b/drivers/video/mediatek/mtk_dpi.c new file mode 100644 index 00000000000..49930a1f104 --- /dev/null +++ b/drivers/video/mediatek/mtk_dpi.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Mediatek MT8188 DPI support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include +#include +#include + +#include "mtk_disp_comp.h" +#include "mtk_dpi.h" +#include "mtk_dpi_regs.h" + +/* INT_MATRIX_SEL value not present in the upstream register header */ +#define MATRIX_SEL_RGB_TO_BT709 3 + +enum mtk_dpintf_out_bit_num { + MTK_DPINTF_OUT_BIT_NUM_8BITS, + MTK_DPINTF_OUT_BIT_NUM_10BITS, + MTK_DPINTF_OUT_BIT_NUM_12BITS, + MTK_DPINTF_OUT_BIT_NUM_16BITS +}; + +enum mtk_dpintf_out_yc_map { + MTK_DPINTF_OUT_YC_MAP_RGB, + MTK_DPINTF_OUT_YC_MAP_CYCY, + MTK_DPINTF_OUT_YC_MAP_YCYC, + MTK_DPINTF_OUT_YC_MAP_CY, + MTK_DPINTF_OUT_YC_MAP_YC +}; + +enum mtk_dpintf_out_channel_swap { + MTK_DPINTF_OUT_CHANNEL_SWAP_RGB, + MTK_DPINTF_OUT_CHANNEL_SWAP_GBR, + MTK_DPINTF_OUT_CHANNEL_SWAP_BRG, + MTK_DPINTF_OUT_CHANNEL_SWAP_RBG, + MTK_DPINTF_OUT_CHANNEL_SWAP_GRB, + MTK_DPINTF_OUT_CHANNEL_SWAP_BGR +}; + +enum mtk_dpintf_polarity { + MTK_DPINTF_POLARITY_RISING, + MTK_DPINTF_POLARITY_FALLING, +}; + +struct mtk_dpintf_polarities { + enum mtk_dpintf_polarity de_pol; + enum mtk_dpintf_polarity ck_pol; + enum mtk_dpintf_polarity hsync_pol; + enum mtk_dpintf_polarity vsync_pol; +}; + +struct mtk_dpintf_sync_param { + u32 sync_width; + u32 front_porch; + u32 back_porch; + bool shift_half_line; +}; + +struct mtk_dpintf_yc_limit { + u16 y_top; + u16 y_bottom; + u16 c_top; + u16 c_bottom; +}; + +static void mtk_dpi_mask(struct udevice *dev, u32 offset, u32 val, u32 mask) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + void __iomem *addr = priv->base + offset; + u32 tmp = readl(addr) & ~mask; + + tmp |= (val & mask); + writel(tmp, addr); +} + +static void mtk_dpi_sw_reset(struct udevice *dev, bool reset) +{ + mtk_dpi_mask(dev, DPI_RET, reset ? RST : 0, RST); +} + +static void mtk_dpi_config_hsync(struct udevice *dev, + struct mtk_dpintf_sync_param *sync) +{ + mtk_dpi_mask(dev, DPI_TGEN_HWIDTH, sync->sync_width << HPW, HPW_MASK); + mtk_dpi_mask(dev, DPI_TGEN_HPORCH, sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dev, DPI_TGEN_HPORCH, sync->front_porch << HFP, HFP_MASK); +} + +static void mtk_dpi_config_vsync(struct udevice *dev, + struct mtk_dpintf_sync_param *sync, + u32 width_addr, u32 porch_addr) +{ + mtk_dpi_mask(dev, width_addr, sync->sync_width << VSYNC_WIDTH_SHIFT, + VSYNC_WIDTH_MASK); + mtk_dpi_mask(dev, width_addr, + sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, + VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dev, porch_addr, + sync->back_porch << VSYNC_BACK_PORCH_SHIFT, + VSYNC_BACK_PORCH_MASK); + mtk_dpi_mask(dev, porch_addr, + sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, + VSYNC_FRONT_PORCH_MASK); +} + +static void mtk_dpi_config_vsync_lodd(struct udevice *dev, + struct mtk_dpintf_sync_param *sync) +{ + mtk_dpi_config_vsync(dev, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); +} + +static void mtk_dpi_config_vsync_leven(struct udevice *dev, + struct mtk_dpintf_sync_param *sync) +{ + mtk_dpi_config_vsync(dev, sync, DPI_TGEN_VWIDTH_LEVEN, + DPI_TGEN_VPORCH_LEVEN); +} + +static void mtk_dpi_config_vsync_rodd(struct udevice *dev, + struct mtk_dpintf_sync_param *sync) +{ + mtk_dpi_config_vsync(dev, sync, DPI_TGEN_VWIDTH_RODD, + DPI_TGEN_VPORCH_RODD); +} + +static void mtk_dpi_config_vsync_reven(struct udevice *dev, + struct mtk_dpintf_sync_param *sync) +{ + mtk_dpi_config_vsync(dev, sync, DPI_TGEN_VWIDTH_REVEN, + DPI_TGEN_VPORCH_REVEN); +} + +static void mtk_dpi_config_pol(struct udevice *dev, + struct mtk_dpintf_polarities *dpi_pol) +{ + unsigned int pol; + + pol = (dpi_pol->ck_pol == MTK_DPINTF_POLARITY_RISING ? 0 : CK_POL) | + (dpi_pol->de_pol == MTK_DPINTF_POLARITY_RISING ? 0 : DE_POL) | + (dpi_pol->hsync_pol == MTK_DPINTF_POLARITY_RISING ? + 0 : HSYNC_POL) | + (dpi_pol->vsync_pol == MTK_DPINTF_POLARITY_RISING ? + 0 : VSYNC_POL); + mtk_dpi_mask(dev, DPI_OUTPUT_SETTING, pol, + CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); +} + +static void mtk_dpi_config_interface(struct udevice *dev, bool inter) +{ + mtk_dpi_mask(dev, DPI_CON, inter ? INTL_EN : 0, INTL_EN); +} + +static void mtk_dpi_config_input_2p(struct udevice *dev, bool input_2p) +{ + mtk_dpi_mask(dev, DPI_CON, input_2p ? DPI_INPUT_2P_EN : 0, + DPI_INPUT_2P_EN); +} + +static void mtk_dpi_config_output_1t1p(struct udevice *dev, bool output_1t1p) +{ + mtk_dpi_mask(dev, DPI_CON, output_1t1p ? DPI_OUTPUT_1T1P_EN : 0, + DPI_OUTPUT_1T1P_EN); +} + +static void mtk_dpi_config_fb_size(struct udevice *dev, u32 width, u32 height) +{ + mtk_dpi_mask(dev, DPI_SIZE, width << HSIZE, HSIZE_MASK); + mtk_dpi_mask(dev, DPI_SIZE, height << VSIZE, VSIZE_MASK); +} + +static void mtk_dpi_config_channel_limit(struct udevice *dev, + struct mtk_dpintf_yc_limit *limit) +{ + mtk_dpi_mask(dev, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, + Y_LIMINT_BOT_MASK); + mtk_dpi_mask(dev, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, + Y_LIMINT_TOP_MASK); + mtk_dpi_mask(dev, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, + C_LIMIT_BOT_MASK); + mtk_dpi_mask(dev, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, + C_LIMIT_TOP_MASK); +} + +static void mtk_dpi_config_bit_num(struct udevice *dev, + enum mtk_dpintf_out_bit_num num) +{ + u32 val; + + switch (num) { + case MTK_DPINTF_OUT_BIT_NUM_8BITS: + val = OUT_BIT_8; + break; + case MTK_DPINTF_OUT_BIT_NUM_10BITS: + val = OUT_BIT_10; + break; + case MTK_DPINTF_OUT_BIT_NUM_12BITS: + val = OUT_BIT_12; + break; + case MTK_DPINTF_OUT_BIT_NUM_16BITS: + val = OUT_BIT_16; + break; + default: + val = OUT_BIT_8; + break; + } + + mtk_dpi_mask(dev, DPI_OUTPUT_SETTING, val << OUT_BIT, OUT_BIT_MASK); +} + +static void mtk_dpi_config_yc_map(struct udevice *dev, + enum mtk_dpintf_out_yc_map map) +{ + u32 val; + + switch (map) { + case MTK_DPINTF_OUT_YC_MAP_RGB: + val = YC_MAP_RGB; + break; + case MTK_DPINTF_OUT_YC_MAP_CYCY: + val = YC_MAP_CYCY; + break; + case MTK_DPINTF_OUT_YC_MAP_YCYC: + val = YC_MAP_YCYC; + break; + case MTK_DPINTF_OUT_YC_MAP_CY: + val = YC_MAP_CY; + break; + case MTK_DPINTF_OUT_YC_MAP_YC: + val = YC_MAP_YC; + break; + default: + val = YC_MAP_RGB; + break; + } + + mtk_dpi_mask(dev, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); +} + +static void mtk_dpi_config_channel_swap(struct udevice *dev, + enum mtk_dpintf_out_channel_swap swap) +{ + u32 val; + + switch (swap) { + case MTK_DPINTF_OUT_CHANNEL_SWAP_RGB: + val = SWAP_RGB; + break; + case MTK_DPINTF_OUT_CHANNEL_SWAP_GBR: + val = SWAP_GBR; + break; + case MTK_DPINTF_OUT_CHANNEL_SWAP_BRG: + val = SWAP_BRG; + break; + case MTK_DPINTF_OUT_CHANNEL_SWAP_RBG: + val = SWAP_RBG; + break; + case MTK_DPINTF_OUT_CHANNEL_SWAP_GRB: + val = SWAP_GRB; + break; + case MTK_DPINTF_OUT_CHANNEL_SWAP_BGR: + val = SWAP_BGR; + break; + default: + val = SWAP_RGB; + break; + } + + mtk_dpi_mask(dev, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); +} + +static void mtk_dpi_config_csc_enable(struct udevice *dev, bool enable) +{ + mtk_dpi_mask(dev, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); +} + +static void mtk_dpi_config_swap_input(struct udevice *dev, bool enable) +{ + mtk_dpi_mask(dev, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); +} + +static void mtk_dpi_internal_matrix_sel(struct udevice *dev, bool enable) +{ + mtk_dpi_config_csc_enable(dev, enable); + if (enable) + mtk_dpi_mask(dev, DPI_MATRIX_SET, MATRIX_SEL_RGB_TO_BT709, + INT_MATRIX_SEL_MASK); +} + +void mtk_dpi_hw_enable(struct udevice *dev) +{ + mtk_dpi_mask(dev, DPI_EN, EN, EN); +} + +void mtk_dpi_hw_disable(struct udevice *dev) +{ + mtk_dpi_mask(dev, DPI_EN, 0, EN); +} + +void mtk_dpi_config(struct udevice *dev, const struct display_timing *timing, + bool rgb) +{ + struct mtk_dpintf_yc_limit limit; + struct mtk_dpintf_polarities dpi_pol; + struct mtk_dpintf_sync_param hsync; + struct mtk_dpintf_sync_param vsync_lodd = {}; + struct mtk_dpintf_sync_param vsync_leven = {}; + struct mtk_dpintf_sync_param vsync_rodd = {}; + struct mtk_dpintf_sync_param vsync_reven = {}; + bool interlaced = timing->flags & DISPLAY_FLAGS_INTERLACED; + + limit.c_bottom = 0x0010; + limit.c_top = 0x0FE0; + limit.y_bottom = 0x0010; + limit.y_top = 0x0FE0; + + dpi_pol.ck_pol = MTK_DPINTF_POLARITY_FALLING; + dpi_pol.de_pol = MTK_DPINTF_POLARITY_RISING; + dpi_pol.hsync_pol = timing->flags & DISPLAY_FLAGS_HSYNC_HIGH ? + MTK_DPINTF_POLARITY_RISING : + MTK_DPINTF_POLARITY_FALLING; + dpi_pol.vsync_pol = timing->flags & DISPLAY_FLAGS_VSYNC_HIGH ? + MTK_DPINTF_POLARITY_RISING : + MTK_DPINTF_POLARITY_FALLING; + + hsync.sync_width = timing->hsync_len.typ; + hsync.back_porch = timing->hback_porch.typ; + hsync.front_porch = timing->hfront_porch.typ; + hsync.shift_half_line = false; + + vsync_lodd.sync_width = timing->vsync_len.typ; + vsync_lodd.back_porch = timing->vback_porch.typ; + vsync_lodd.front_porch = timing->vfront_porch.typ; + vsync_lodd.shift_half_line = false; + + if (interlaced) { + vsync_leven = vsync_lodd; + vsync_leven.shift_half_line = true; + } + + mtk_dpi_sw_reset(dev, true); + mtk_dpi_config_pol(dev, &dpi_pol); + + mtk_dpi_config_hsync(dev, &hsync); + mtk_dpi_config_vsync_lodd(dev, &vsync_lodd); + mtk_dpi_config_vsync_rodd(dev, &vsync_rodd); + mtk_dpi_config_vsync_leven(dev, &vsync_leven); + mtk_dpi_config_vsync_reven(dev, &vsync_reven); + + mtk_dpi_config_interface(dev, interlaced); + if (interlaced) + mtk_dpi_config_fb_size(dev, timing->hactive.typ, + timing->vactive.typ / 2); + else + mtk_dpi_config_fb_size(dev, timing->hactive.typ, + timing->vactive.typ); + + mtk_dpi_config_input_2p(dev, true); + mtk_dpi_config_output_1t1p(dev, true); + mtk_dpi_config_channel_limit(dev, &limit); + mtk_dpi_config_bit_num(dev, MTK_DPINTF_OUT_BIT_NUM_8BITS); + mtk_dpi_config_channel_swap(dev, MTK_DPINTF_OUT_CHANNEL_SWAP_RGB); + mtk_dpi_internal_matrix_sel(dev, !rgb); + mtk_dpi_config_yc_map(dev, MTK_DPINTF_OUT_YC_MAP_RGB); + mtk_dpi_config_swap_input(dev, false); + mtk_dpi_sw_reset(dev, false); +} + +static const struct udevice_id mtk_dpi_ids[] = { + { .compatible = "mediatek,mt8195-dpi" }, + {} +}; + +U_BOOT_DRIVER(mtk_dpi) = { + .name = "mtk_dpi", + .id = UCLASS_MISC, + .of_match = mtk_dpi_ids, + .probe = mtk_disp_comp_probe, + .priv_auto = sizeof(struct mtk_disp_comp_priv), +}; diff --git a/drivers/video/mediatek/mtk_dpi.h b/drivers/video/mediatek/mtk_dpi.h new file mode 100644 index 00000000000..2712ea05500 --- /dev/null +++ b/drivers/video/mediatek/mtk_dpi.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Mediatek MT8188 DPI Support + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#ifndef _MTK_DPI_H +#define _MTK_DPI_H + +struct display_timing; +struct udevice; + +void mtk_dpi_hw_enable(struct udevice *dev); +void mtk_dpi_hw_disable(struct udevice *dev); +void mtk_dpi_config(struct udevice *dev, const struct display_timing *timing, + bool rgb); + +#endif diff --git a/drivers/video/mediatek/mtk_dpi_regs.h b/drivers/video/mediatek/mtk_dpi_regs.h new file mode 100644 index 00000000000..23eeefce8fd --- /dev/null +++ b/drivers/video/mediatek/mtk_dpi_regs.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Jie Qiu + */ +#ifndef __MTK_DPI_REGS_H +#define __MTK_DPI_REGS_H + +#define DPI_EN 0x00 +#define EN BIT(0) + +#define DPI_RET 0x04 +#define RST BIT(0) + +#define DPI_INTEN 0x08 +#define INT_VSYNC_EN BIT(0) +#define INT_VDE_EN BIT(1) +#define INT_UNDERFLOW_EN BIT(2) + +#define DPI_INTSTA 0x0C +#define INT_VSYNC_STA BIT(0) +#define INT_VDE_STA BIT(1) +#define INT_UNDERFLOW_STA BIT(2) + +#define DPI_CON 0x10 +#define BG_ENABLE BIT(0) +#define IN_RB_SWAP BIT(1) +#define INTL_EN BIT(2) +#define TDFP_EN BIT(3) +#define CLPF_EN BIT(4) +#define YUV422_EN BIT(5) +#define CSC_ENABLE BIT(6) +#define R601_SEL BIT(7) +#define EMBSYNC_EN BIT(8) +#define VS_LODD_EN BIT(16) +#define VS_LEVEN_EN BIT(17) +#define VS_RODD_EN BIT(18) +#define VS_REVEN BIT(19) +#define FAKE_DE_LODD BIT(20) +#define FAKE_DE_LEVEN BIT(21) +#define FAKE_DE_RODD BIT(22) +#define FAKE_DE_REVEN BIT(23) + +/* DPI_CON: DPI instances */ +#define DPI_OUTPUT_1T1P_EN BIT(24) +#define DPI_INPUT_2P_EN BIT(25) +/* DPI_CON: DPINTF instances */ +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) + +#define DPI_OUTPUT_SETTING 0x14 +#define CH_SWAP 0 +#define DPINTF_CH_SWAP 1 +#define CH_SWAP_MASK (0x7 << 0) +#define SWAP_RGB 0x00 +#define SWAP_GBR 0x01 +#define SWAP_BRG 0x02 +#define SWAP_RBG 0x03 +#define SWAP_GRB 0x04 +#define SWAP_BGR 0x05 +#define BIT_SWAP BIT(3) +#define B_MASK BIT(4) +#define G_MASK BIT(5) +#define R_MASK BIT(6) +#define DE_MASK BIT(8) +#define HS_MASK BIT(9) +#define VS_MASK BIT(10) +#define DE_POL BIT(12) +#define HSYNC_POL BIT(13) +#define VSYNC_POL BIT(14) +#define CK_POL BIT(15) +#define OEN_OFF BIT(16) +#define EDGE_SEL BIT(17) +#define OUT_BIT 18 +#define OUT_BIT_MASK (0x3 << 18) +#define OUT_BIT_8 0x00 +#define OUT_BIT_10 0x01 +#define OUT_BIT_12 0x02 +#define OUT_BIT_16 0x03 +#define YC_MAP 20 +#define YC_MAP_MASK (0x7 << 20) +#define YC_MAP_RGB 0x00 +#define YC_MAP_CYCY 0x04 +#define YC_MAP_YCYC 0x05 +#define YC_MAP_CY 0x06 +#define YC_MAP_YC 0x07 + +#define DPI_SIZE 0x18 +#define HSIZE 0 +#define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) +#define VSIZE 16 +#define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) + +#define DPI_DDR_SETTING 0x1C +#define DDR_EN BIT(0) +#define DDDR_SEL BIT(1) +#define DDR_4PHASE BIT(2) +#define DDR_WIDTH (0x3 << 4) +#define DDR_PAD_MODE (0x1 << 8) + +#define DPI_TGEN_HWIDTH 0x20 +#define HPW 0 +#define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) + +#define DPI_TGEN_HPORCH 0x24 +#define HBP 0 +#define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) +#define HFP 16 +#define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) + +#define DPI_TGEN_VWIDTH 0x28 +#define DPI_TGEN_VPORCH 0x2C + +#define VSYNC_WIDTH_SHIFT 0 +#define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) +#define VSYNC_HALF_LINE_SHIFT 16 +#define VSYNC_HALF_LINE_MASK BIT(16) +#define VSYNC_BACK_PORCH_SHIFT 0 +#define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) +#define VSYNC_FRONT_PORCH_SHIFT 16 +#define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) + +#define DPI_BG_HCNTL 0x30 +#define BG_RIGHT (0x1FFF << 0) +#define BG_LEFT (0x1FFF << 16) + +#define DPI_BG_VCNTL 0x34 +#define BG_BOT (0x1FFF << 0) +#define BG_TOP (0x1FFF << 16) + +#define DPI_BG_COLOR 0x38 +#define BG_B (0xF << 0) +#define BG_G (0xF << 8) +#define BG_R (0xF << 16) + +#define DPI_FIFO_CTL 0x3C +#define FIFO_VALID_SET (0x1F << 0) +#define FIFO_RST_SEL (0x1 << 8) + +#define DPI_STATUS 0x40 +#define VCOUNTER (0x1FFF << 0) +#define DPI_BUSY BIT(16) +#define OUTEN BIT(17) +#define FIELD BIT(20) +#define TDLR BIT(21) + +#define DPI_TMODE 0x44 +#define DPI_OEN_ON BIT(0) + +#define DPI_CHECKSUM 0x48 +#define DPI_CHECKSUM_MASK (0xFFFFFF << 0) +#define DPI_CHECKSUM_READY BIT(30) +#define DPI_CHECKSUM_EN BIT(31) + +#define DPI_DUMMY 0x50 +#define DPI_DUMMY_MASK (0xFFFFFFFF << 0) + +#define DPI_TGEN_VWIDTH_LEVEN 0x68 +#define DPI_TGEN_VPORCH_LEVEN 0x6C +#define DPI_TGEN_VWIDTH_RODD 0x70 +#define DPI_TGEN_VPORCH_RODD 0x74 +#define DPI_TGEN_VWIDTH_REVEN 0x78 +#define DPI_TGEN_VPORCH_REVEN 0x7C + +#define DPI_ESAV_VTIMING_LODD 0x80 +#define ESAV_VOFST_LODD (0xFFF << 0) +#define ESAV_VWID_LODD (0xFFF << 16) + +#define DPI_ESAV_VTIMING_LEVEN 0x84 +#define ESAV_VOFST_LEVEN (0xFFF << 0) +#define ESAV_VWID_LEVEN (0xFFF << 16) + +#define DPI_ESAV_VTIMING_RODD 0x88 +#define ESAV_VOFST_RODD (0xFFF << 0) +#define ESAV_VWID_RODD (0xFFF << 16) + +#define DPI_ESAV_VTIMING_REVEN 0x8C +#define ESAV_VOFST_REVEN (0xFFF << 0) +#define ESAV_VWID_REVEN (0xFFF << 16) + +#define DPI_ESAV_FTIMING 0x90 +#define ESAV_FOFST_ODD (0xFFF << 0) +#define ESAV_FOFST_EVEN (0xFFF << 16) + +#define DPI_CLPF_SETTING 0x94 +#define CLPF_TYPE (0x3 << 0) +#define ROUND_EN BIT(4) + +#define DPI_Y_LIMIT 0x98 +#define Y_LIMINT_BOT 0 +#define Y_LIMINT_BOT_MASK (0xFFF << 0) +#define Y_LIMINT_TOP 16 +#define Y_LIMINT_TOP_MASK (0xFFF << 16) + +#define DPI_C_LIMIT 0x9C +#define C_LIMIT_BOT 0 +#define C_LIMIT_BOT_MASK (0xFFF << 0) +#define C_LIMIT_TOP 16 +#define C_LIMIT_TOP_MASK (0xFFF << 16) + +#define DPI_YUV422_SETTING 0xA0 +#define UV_SWAP BIT(0) +#define CR_DELSEL BIT(4) +#define CB_DELSEL BIT(5) +#define Y_DELSEL BIT(6) +#define DE_DELSEL BIT(7) + +#define DPI_EMBSYNC_SETTING 0xA4 +#define EMBSYNC_R_CR_EN BIT(0) +#define EMPSYNC_G_Y_EN BIT(1) +#define EMPSYNC_B_CB_EN BIT(2) +#define ESAV_F_INV BIT(4) +#define ESAV_V_INV BIT(5) +#define ESAV_H_INV BIT(6) +#define ESAV_CODE_MAN BIT(8) +#define VS_OUT_SEL (0x7 << 12) + +#define DPI_ESAV_CODE_SET0 0xA8 +#define ESAV_CODE0 (0xFFF << 0) +#define ESAV_CODE1 (0xFFF << 16) + +#define DPI_ESAV_CODE_SET1 0xAC +#define ESAV_CODE2 (0xFFF << 0) +#define ESAV_CODE3_MSB BIT(16) + +#define EDGE_SEL_EN BIT(5) +#define H_FRE_2N BIT(25) + +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK GENMASK(4, 0) +#define MATRIX_SEL_RGB_TO_JPEG 0 +#define MATRIX_SEL_RGB_TO_BT601 2 + +#define DPI_PATTERN0 0xf00 +#define DPI_PAT_EN BIT(0) +#define DPI_PAT_SEL GENMASK(6, 4) + +#endif /* __MTK_DPI_REGS_H */ From patchwork Wed Sep 2 14:15:59 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296701 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=sK+zo2vO; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=nOGNBYhZ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlD96YRxz1xwg for ; Thu, 03 Sep 2026 00:17:13 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 73A9E810BE; Wed, 2 Sep 2026 14:17:10 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id m_6-w5VeJGbP; Wed, 2 Sep 2026 14:17:09 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358612; bh=zaHoEUwRGmt16iqJfruLbjPP94O5Km04ZeciuPhYI+E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=sK+zo2vOnjtO7Myv7zJ+uCFz9LyGFVViqLiLkiRjwqnPZzQhTO53V5rAxEaIYmFSF ABhrBjiDynZ4h8lm8pH0KMnVr46xZ7JKNEheBIFhSx3N046F+7cbGxrtwlyE7LJymL kG2+IYMec9W6H3o/jm8SSnl9pt5t4TLxfZGY7bb3oJfw84rHhxrMpJB6SFPgwcA8OF OozTh7r/nDsEVElJhZ64d+RntzmTkd4gc8ISutIB6KpE528JxIjSwx+oixUOz1zsiN KubQcWxQhepGEducH2vL8/w3GaVxxsgj/wDnd2pg4YMWhHWDLYOt5PqvELwiyTgyb+ 2FlpEMOcCHdDA== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id A423E80F73; Wed, 2 Sep 2026 14:16:51 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by lists1.osuosl.org (Postfix) with ESMTP id 8F242363 for ; Wed, 2 Sep 2026 14:16:45 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 6B37081010 for ; Wed, 2 Sep 2026 14:16:45 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id s8Vm_xQP9Syn for ; Wed, 2 Sep 2026 14:16:44 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::432; helo=mail-wr1-x432.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp1.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=nOGNBYhZ Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by smtp1.osuosl.org (Postfix) with ESMTPS id 7CB2780F1F for ; Wed, 2 Sep 2026 14:16:34 +0000 (UTC) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-47ddf7b09e5so1099870f8f.1 for ; Wed, 02 Sep 2026 07:16:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358592; x=1788963392; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=zaHoEUwRGmt16iqJfruLbjPP94O5Km04ZeciuPhYI+E=; b=nOGNBYhZlSeinQeGzh6C/ncnBAjcfD2t3wz6RnkGjQSaIHXWSRPeMY1WJJDq7GoeZq /qw0w9xu0lneaIxcNyQ2NsnfkCttvJRF0BLomueHY61vKSXKcJTt1UPzlVtCuwG6lHFj XKF1XMEu+BmwI5eUn6r1wUPDISu2Km5iyfp+ISoz2wyzuQT93hR8RzhmcU7YJqV75qfN QvI2IE2zLNIdP9S3qeoltRpu639An9cuGJm1+poGYSlQNuZUPU3J5WzGin72/XD7I4v5 xyjscbryqJZTyExbgew8XAd0T6bhbP8zLQpH5Ded9M+/8NRvZM7FRaCNAMtq1PAHWLne YHrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358592; x=1788963392; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=zaHoEUwRGmt16iqJfruLbjPP94O5Km04ZeciuPhYI+E=; b=cGGo3DO4Rg99g8gu6/afJy9FJ6FWV5T71khY3eFYWwWtuijZJltkOVGTT/jNkyuYK/ tsYtWkwTOr/WHTqZpmH52ZoDhUvqeEBOTJCssvXG021qavFf0kvETL+H+IcNu/mnf41q jVM7ZBeM18TASfmVJHZ6UIHSzo60JxsBLQK8T/S/DEfwetfWdoBzUUV2Y2cY/hMFNaff nTChkja7wWa/ZQ3KuWcqKWlY3vgSDSPzNIyQKjgGOl0tV3OSzwwwUxCRozLKSHr1sN2a uUa9Oh8XgK/rJyRcWl1Y9cVM190YpbCaP7yFOOGmlW0cmm2kyn6XSj+ZYGQxGfseHCrB L9tw== X-Gm-Message-State: AFuF++mINGHmsa/CZugqV/9hQhwTrPP8g6gUY9AQBwDUFr6bVMBORNv/ cNjPefchPOKqP8Wk9z6KwGOx8kX3+Stxsla/7JDCM+vxeCToxG6pGyxE5K4NxJVmuyU= X-Gm-Gg: AYBFou3sU2MmL071zACY4YyeINTr5RSOGvxcT0kFI5PtPXtGKVpNiCVgZyacc3z9X6g dLW/pxpRr7lB9TUVHwSFWZy+E81/mEFcs1ueg9jT6FxfHpWNbDSqe61IZcqbOX3WZWnmf3IPGg3 j3wCFDmP03ean96rWs1h7aIOFSBb1uSe1xuPOu3Ic5QPTqCVGsQx9pmT8LvCqjs2HEcqe2MbRKy eIjl2DSJ/FhrflyixXXsI4RMwQPVIw6Sab5Z/Jy/8oP+gXYNMZ8/pvSgN+6XafpkaZXtGYje6Y/ 8WRXT55CKr6+MYCL/iEFI56jp/2DLJPtYIHza4wvBKZz/r9LFkdKq1jdqJlmsmTDqxuFgHZvCjy hEM0tDzlhYuLlE5aC7taGroX1VPyrrPDTlO3wxooJOnU/Gc0d8ITOwGMk6yH/DQYvzYR5PbvcMQ v0cODbh299tEFvMLkDFSubzEu9JHBTGrRUJYFSl8aELvqHdeaDsAO48alRwvKPiqwwTAibMIEFm mvm1Igy6E9j0DzjOVbyFq9fOSWZD6IKw0t267CSzAGG/1zBT+3PwN+Y4TT0NAyhlx3i2S0I5iJb ktg1CkVmIv8pcpMMDyUQ1r6anmq7qpSaOFtcs7kkARjoQwL+I4/nLCg= X-Received: by 2002:a05:6000:1847:b0:484:3931:c698 with SMTP id ffacd0b85a97d-48488dee004mr9041047f8f.5.1788358592088; Wed, 02 Sep 2026 07:16:32 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:31 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:15:59 +0200 Subject: [PATCH v4 09/14] asm-generic: unaligned: add get_unaligned_le24() MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-9-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Add get_unaligned_le24(), mirroring the helper of the same name in Linux, to read a 24-bit little-endian value from a possibly unaligned buffer. The MediaTek HDMI driver uses it to pack InfoFrame bytes into the 24-bit little-endian controller register fields. Signed-off-by: Julien Stephan --- include/asm-generic/unaligned.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index 9e5d93ec304..8a181ba6682 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -32,6 +32,13 @@ static inline u64 get_unaligned_le64(const void *p) return le64_to_cpu(__get_unaligned_t(__le64, p)); } +static inline u32 get_unaligned_le24(const void *p) +{ + const u8 *_p = p; + + return _p[0] | _p[1] << 8 | _p[2] << 16; +} + static inline void put_unaligned_le16(u16 val, void *p) { __put_unaligned_t(__le16, cpu_to_le16(val), p); From patchwork Wed Sep 2 14:16:00 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296695 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=IYwKVXGa; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=i4xBblaO; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCt6Wsdz1xwg for ; Thu, 03 Sep 2026 00:16:58 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id D39FD80F88; Wed, 2 Sep 2026 14:16:56 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id vahLpAWa7hkg; Wed, 2 Sep 2026 14:16:54 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358597; bh=eS13Q7dxpUJOaeaBP6rTHcOYtUPH9t8nFE8VoufbCKg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=IYwKVXGag6IUvQY0Cz7eCzCduwP4bFMDYWhE7yORqrPos856KIB71PJehMZV13SQb VD2jIkdAJ2JiRT9bYnAr8gIQfS3il3KejF4k/B8LsYKbwvt9O5QyEzmMl99PxJiTai qMYmgGTU28WJAy39eQLiD49GW1MjQ8mOFNZYlRxAQsDZyqTi018sxqVK07YHWp+1F8 PcmCa/OcipkeLSZabsyOSdBmui7eL2Sv548hARJF7aUYFbKAnfL+rV4JD202hHYLBZ nr154rfKDBg5XgoIVjE4U0fSAxc4+DHHBaOAlRcv94i3XRTHDFUxVNPuTu9/+cohrq E6oSE802MWIKg== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id BEB4180F89; Wed, 2 Sep 2026 14:16:37 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists1.osuosl.org (Postfix) with ESMTP id 9066C465 for ; Wed, 2 Sep 2026 14:16:36 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 76310606CF for ; Wed, 2 Sep 2026 14:16:36 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id fQMo6eUwyRVg for ; Wed, 2 Sep 2026 14:16:36 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::42a; helo=mail-wr1-x42a.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp3.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=i4xBblaO Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by smtp3.osuosl.org (Postfix) with ESMTPS id 91E77606C4 for ; Wed, 2 Sep 2026 14:16:35 +0000 (UTC) Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-484362f5c4aso1185844f8f.3 for ; Wed, 02 Sep 2026 07:16:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358593; x=1788963393; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=eS13Q7dxpUJOaeaBP6rTHcOYtUPH9t8nFE8VoufbCKg=; b=i4xBblaOf3BeuYt7JwvthglK/ywGyvB555KrZl785U+xOGeTpBrIvoNa5ZlR7eEuMh PdDVLGsML0fM+ScpecvWFT5dlcCeZLopNWbYgT6ouf8mVoEK8wmmQLcrNVhSQ3KpXYcx +qdn3a5HU+OG9EqrsR6gHSe8Ssg236A5zUrdhRsyXZx012bUYRt49CDOSI+GoVvo+Afo wVldEXQeikdiq37N6QYuFTZs0HGdINwlYfR6Q8zjo8Uq0r+Xxmmx6/9ie+Ihc/nkSJgI 31Z82dqoSfChxJsCaFaD6LOkDcKcxdfIZzV0wszMAkkGEoLOV+eouhpkUclDpcSXPyuh dCwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358593; x=1788963393; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=eS13Q7dxpUJOaeaBP6rTHcOYtUPH9t8nFE8VoufbCKg=; b=rRyjbgRJBOWu4nZ4jqABYVUrv27/xtls16YCdLtCSknEQ5edFFzLxC5HsjAa+P/UYN fmdyBynRRls4fSuspJvcb8ouwS9DfoB+bPv6cFh/uWLXv+PLiLgkWBpeMC+clGjn/yQh z5C+ejXTQap+sr+eye5Qg/OXUbe0fVF/v3l55aVuXw+J0cY/K81kDFYQaFg7FoqGE2Z4 lUZS2AFizM7Wxzb8Gp/X9LYTiaeIHJUmDTKLkJuwSzOwp3h/lfRnETBU8CLm+kEct2t/ wfWe5pqF1eKEDZNIipljxTzUXX0yp6RFK+UWKFi8xzFdV4AgxWS1hipydWBZ1MO+/J3N 3Rng== X-Gm-Message-State: AFuF++lRAqH1O0fz2642ob9jCNbx6lXuYXUEBeBHwsykExELQc7YUyS2 ejnJ5rUBpGntj9NVoRdCTro39oaS7sV5T6nckkTyGTuTISCj6QPGt14fXz7AgiPg/H4= X-Gm-Gg: AYBFou0TsyxI4vNAVUYDCmDzdhgchkck9xt+66OGl9T3nPso8Jsm6482SxHqGaPEv7A /asq/VSd6CkZKUA8FWe/8U13d+fkyvTuzrI1CSmF2aA/APht79JXCtlclHnS0uL1v1Qm4TUCMDh 5vrrxXxe2uEAmawHu8j33DFM/ss73i1W0DeXGN+jth81Ulwq0SqW4VyzM9184y4rI0G/5D1tjkt QDGukIpIGW42fpe3752d+BIdwYJkmGLoEC92LDkDczZx61f3GNUD+7UatpFZRpM34nJHr/ekcx9 OMTsUc1ayfYWI/nrfiCBoXR3yB+q8hUFva+7G1UhSR9uQKXvOuTG618IYGuNaahp0niU7YTx1BR 0JaBQ+9dcSDfW/xxXwTrwCaq/i6BovbXyKQqcJHkrOUTyRYcBK7IqmUZNJgBnXrT1CX0yHoJ5ad AndopEmWkZPORF90FNJNc9JEcPZtCsAS6ikOFTwslNZOppLgE9as6ZHyZqpmsyj8MkIEdAGruad o1HrQIedmGlN9O70hb6g7Y0mNlPaaPSZEwuk30dCmvz+VCbPb+dSkVPkA08JTTsfUTBBd0zDLqk aaE3V6ESesFbTHakKi4uRmAHM0TZiCqK0obTd4eu4abH X-Received: by 2002:a05:6000:250c:b0:484:3310:c4fc with SMTP id ffacd0b85a97d-48488f24193mr9852157f8f.23.1788358593095; Wed, 02 Sep 2026 07:16:33 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:32 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:16:00 +0200 Subject: [PATCH v4 10/14] include: linux/hdmi.h: add HDMI colorspace and colorimetry enums MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-10-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Import the hdmi_colorspace and hdmi_colorimetry enumerations from Linux' include/linux/hdmi.h. These describe the AVI InfoFrame colorspace and colorimetry fields defined by the HDMI specification and are identical across HDMI transmitters, so keep them in a generic header rather than duplicating them in each driver. Signed-off-by: Julien Stephan --- include/linux/hdmi.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h new file mode 100644 index 00000000000..6e4828eb192 --- /dev/null +++ b/include/linux/hdmi.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Partial port of Linux' include/linux/hdmi.h, carrying the pieces of the + * HDMI specification that are common to all HDMI transmitters. + * + * Copyright (C) 2012 Avionic Design GmbH + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __LINUX_HDMI_H_ +#define __LINUX_HDMI_H_ + +enum hdmi_colorspace { + HDMI_COLORSPACE_RGB, + HDMI_COLORSPACE_YUV422, + HDMI_COLORSPACE_YUV444, + HDMI_COLORSPACE_YUV420, + HDMI_COLORSPACE_RESERVED4, + HDMI_COLORSPACE_RESERVED5, + HDMI_COLORSPACE_RESERVED6, + HDMI_COLORSPACE_IDO_DEFINED, +}; + +enum hdmi_colorimetry { + HDMI_COLORIMETRY_NONE, + HDMI_COLORIMETRY_ITU_601, + HDMI_COLORIMETRY_ITU_709, + HDMI_COLORIMETRY_EXTENDED, +}; + +#endif /* __LINUX_HDMI_H_ */ From patchwork Wed Sep 2 14:16:01 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296698 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=jRn4ENgy; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=N89+WOy7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlD23MFdz1xwg for ; Thu, 03 Sep 2026 00:17:06 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 0610F80299; Wed, 2 Sep 2026 14:17:05 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id HmT6k_QduiXW; Wed, 2 Sep 2026 14:16:58 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358602; bh=ZoNgazgE9WefsFig5zYorZy0UTQlanhYZfuo0SYXGLA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=jRn4ENgypcaHFsvVAlxr0xUPDjMRAzNhCgAe1OCrWqtcZWCqI48Slcvm4y5nz0o23 nodwP3Cgu7ukySfNH90334Bd2zzOo/PbVHAWt/zEsKQbiOUWCXFML2cZrtGwlYSHKc /ExDFrOBB47sTxb3CWKOrxZg0GZpXND9kKLx9vYYBciUA8FSQM1qd13DFhoKVnvZwQ 4veOAx9XY70Nsjth1AlH3Qgei8h28q25gUipVXZbtdP3dUMjF/r7YPCK3ORsqOtE+8 cE9/zfyiU5EGIfdh5JXu+K3m6cCwL9RZGkF+yV2N4baoU5m3xWVEOwNo2Rrygb/p/A XMsCUUZdFy8vA== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 5D34180FC6; Wed, 2 Sep 2026 14:16:42 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp2.osuosl.org (smtp2.osuosl.org [IPv6:2605:bc80:3010::133]) by lists1.osuosl.org (Postfix) with ESMTP id 724A64AD for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp2.osuosl.org (Postfix) with ESMTP id 667EA400A6 for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp2.osuosl.org ([127.0.0.1]) by localhost (smtp2.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 50iJGVV_-O5n for ; Wed, 2 Sep 2026 14:16:37 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::435; helo=mail-wr1-x435.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp2.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=N89+WOy7 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by smtp2.osuosl.org (Postfix) with ESMTPS id C222A4006F for ; Wed, 2 Sep 2026 14:16:36 +0000 (UTC) Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-482e4998d28so856220f8f.2 for ; Wed, 02 Sep 2026 07:16:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358595; x=1788963395; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ZoNgazgE9WefsFig5zYorZy0UTQlanhYZfuo0SYXGLA=; b=N89+WOy7F4pSweUHAn9nt4wY0pIWqog2t0C/JvHFdhztbzaav2ZUHjxGde466EXkUG FthRmspUZN55QhZObI0s40XFLIOrf2oG86MSJ3qqUwmDV0nPHqOD+qJXywwAiKIuXvqO VRBtSbuAHJBznJ9MauuVxW8Vi6pxX5SDOjip9OES4hYwAM5fuPJUslWhDd0AmvRcjLG4 nlH4OTF0UzcytnQvTMld2RKE3J1sGYjBpp5YLF6H1zSz8gpWm8qHLQx1GlmbRY7BgMuB 3Ka/tg/T8IaIbDPk+OT0xym5ln6mQzJZhz86fdyXK3bV90aBjFUeU9WewlmYVfhMuXRU MkUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358595; x=1788963395; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ZoNgazgE9WefsFig5zYorZy0UTQlanhYZfuo0SYXGLA=; b=PYoMcIPJUaN6saAryoWIAMHOhN/vrMAkkAtL2trojJJwCBlqQuIj2/Iy8wefAaJW3p Zb9PVP1D6LBx6TzGSv9s/8SkFlRYPVsyN1WqVOeEsGsYcJTD9D0+bjeh+h7UEC6HOee9 1Gl3YF0TcaQ8gyHqjxVsbBOP+fDfJERD5GZwlGEff2iI+IvWS6Jy+ADM1BwBjH9WaPhD ADemuJLsAf6kfyz7SSxwt10vgBM0deN1vdV4oKQz59jXaRkImbuNYOZxm5upvbcq0Dz5 KU9bGjt10AT8H3lVEkwZT3EOzjwVa1mb85D3pFyqmOw/Apf0slg6Fa0vtzC4Gii2NYhz VaKQ== X-Gm-Message-State: AFuF++n2W8JuzVL8c6u71UGHwh6aT+HFkoAzA/2qVa4y656NU5/VdBZU Q8UIhSQwX0raQWHnq9dbvqnAifoO2OeERsP3ryWohynBEDahssDhTieApCaE433rWFk= X-Gm-Gg: AYBFou2ZhAag9ceKL/Fegz3P5C6F0mk2XBHDLZ7pLRxyP9DPUrkCbcGgexcai852dag k/ptiUvOX2Iu3Y9gnbv1HlTMPAsWiSfJcSr2EJgZVRuSCwxBZ7N6OC0u0fuhMsQ+ZlxY0ICQf8U 4HIfr6gCSMvQO1kZHPVr4t+zq1NgBPd3oC0LXLSkFIrzAsg1aAOpXhl4AqppGveoZ9wU3dOZys0 KdZadBCsBiJ+Mc9UKRCWxtcCNk1/0oPpeGp++lZIAXnBL9s9m33KuO+lKs5SEb06ItmtQOXGoNX pDku60M4pb/waGAN9u39Z5QZ+5Vel1goxyxLu8Z0Edckx1OUvVi9+OO6I1WrUmmK3bTmtIwopVA NyQJgEml2CPdej023+ozSWqhL7cyol0MjpmvPHWRAxcKajIK0J/ZP/UAoW5EZyVD/djrkj5HfYA azYwtrNC9AUeo/9vEwxzqEaKi5gTlu+dLbjXAzYI4DrNTcJ0kyKchOx84KTWdnZjU4YnrfrQjBG ogPab3HXjbr3NeKpFJmbaWj7uy3IawWNs4YZvn6qrS8N0kNvc7nbcL0n4lNp8LDzXZQiDzq8ZU/ U1Lr8ck5vA/uufsWPtw89HleR5CRQxNI2FbyyZiebw6A X-Received: by 2002:a05:6000:2003:b0:484:3326:7528 with SMTP id ffacd0b85a97d-48488f224e7mr10001818f8f.25.1788358594260; Wed, 02 Sep 2026 07:16:34 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:33 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:16:01 +0200 Subject: [PATCH v4 11/14] video: mediatek: add new hdmi driver MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-11-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Add a UCLASS_VIDEO driver for the HDMI TX v2 IP found on the MT8188. On probe, the driver waits for a plugged and powered display, reads its EDID through the DDC bus to select the preferred mode, configures the HDMI controller and PHY accordingly, and then programs all the components of the vdosys1 pipeline (MDP RDMA, padding, VPP merge, ETHDR mixer, mutex, DPI1) to scan out the framebuffer. The framebuffer lives in a dedicated reserved-memory region referenced by the "memory-region" property of the hdmi node. Signed-off-by: Pavlo Yadvychuk Signed-off-by: Julien Stephan --- drivers/video/Kconfig | 1 + drivers/video/Makefile | 1 + drivers/video/mediatek/Kconfig | 21 + drivers/video/mediatek/Makefile | 16 + drivers/video/mediatek/mtk_hdmi.c | 894 ++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_hdmi_regs_v2.h | 267 +++++++++ 6 files changed, 1200 insertions(+) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 15000e21840..cb3ba6a6f63 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -770,6 +770,7 @@ config VIDEO_LCD_SPI_MISO option takes a string in the format understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. +source "drivers/video/mediatek/Kconfig" source "drivers/video/meson/Kconfig" config VIDEO_MVEBU diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 082b8967982..a20011b9b17 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -92,5 +92,6 @@ obj-$(CONFIG_VIDEO_SEPS525) += seps525.o obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp/ obj-y += bridge/ +obj-y += mediatek/ obj-y += sunxi/ obj-y += tegra/ diff --git a/drivers/video/mediatek/Kconfig b/drivers/video/mediatek/Kconfig new file mode 100644 index 00000000000..3e51e5e1a63 --- /dev/null +++ b/drivers/video/mediatek/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (c) 2026 BayLibre, SAS +# +# Author: Julien Stephan + +config VIDEO_MEDIATEK_HDMI + bool "Video HDMI Support for Mediatek SoCs" + depends on VIDEO && ARCH_MEDIATEK + depends on DM_I2C && PHY && POWER_DOMAIN + select I2C_EDID + select MISC + select PHY_MTK_HDMI + select MTK_POWER_DOMAIN + select SYS_I2C_DDC_MTK + help + Enable support for the HDMI TX output found on recent MediaTek + SoCs such as the MT8188. The driver reads the EDID of the + connected display, selects its preferred mode and drives the + vdosys1 display pipeline (MDP RDMA, padding, merge, ETHDR + mixer, DPI) to scan out the U-Boot framebuffer over HDMI. diff --git a/drivers/video/mediatek/Makefile b/drivers/video/mediatek/Makefile new file mode 100644 index 00000000000..9d728fbcc08 --- /dev/null +++ b/drivers/video/mediatek/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (c) 2026 BayLibre, SAS +# +# Author: Julien Stephan + +obj-$(CONFIG_VIDEO_MEDIATEK_HDMI) += \ + mtk_disp_comp.o \ + mtk_disp_merge.o \ + mtk_disp_mutex.o \ + mtk_disp_padding.o \ + mtk_dpi.o \ + mtk_ethdr.o \ + mtk_hdmi.o \ + mtk_mdp_rdma.o \ + mtk_smi_larb.o diff --git a/drivers/video/mediatek/mtk_hdmi.c b/drivers/video/mediatek/mtk_hdmi.c new file mode 100644 index 00000000000..976ec4d8079 --- /dev/null +++ b/drivers/video/mediatek/mtk_hdmi.c @@ -0,0 +1,894 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 BayLibre, SAS + * Author: Julien Stephan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_comp.h" +#include "mtk_disp_merge.h" +#include "mtk_ethdr.h" +#include "mtk_disp_mutex.h" +#include "mtk_disp_padding.h" +#include "mtk_dpi.h" +#include "mtk_hdmi_regs_v2.h" +#include "mtk_mdp_rdma.h" + +/* VDOSYS1 display routing (SEL_IN / SOUT mux) registers */ +#define SUBDISP_DISP_DPI1_SEL_IN 0xF10 +#define SUBDISP_DISP_MERGE4_MOUT_SEL 0xF18 +#define SUBDISP_MIXER_IN3_SEL_IN 0xF2C +#define SUBDISP_MIXER_OUT_SOUT_SEL 0xF34 +#define SUBDISP_MERGE2_ASYNC_SOUT_SEL 0xF48 +#define SUBDISP_MERGE4_ASYNC_SEL_IN 0xF50 +#define SUBDISP_MIXER_IN3_SOUT_SEL 0xF60 +#define SUBDISP_MIXER_SOUT_SEL_IN 0xF68 + +#define OUTPUT_TO_MIXER_IN3_SEL 0x1 +#define INPUT_FROM_MERGE2_ASYNC_SOUT 0x1 +#define OUTPUT_TO_DISP_MIXER 0x0 +#define INPUT_FROM_DISP_MIXER 0x0 +#define OUTPUT_TO_HDR_VDO_BE0 0x0 +#define INPUT_FROM_HDR_VDO_BE0 0x0 +#define OUTPUT_TO_DPI1_SEL 0x4 +#define INPUT_FROM_VPP_MERGE4_MOUT 0x0 + +#define MTK_HDMI_MAX_WIDTH 3840 +#define MTK_HDMI_MAX_HEIGHT 2160 + +#define MTK_HDMI_HPD_TIMEOUT_MS 100 + +/* 4 byte header + 13 byte payload */ +#define HDMI_AVI_INFOFRAME_SIZE 17 +/* 4 byte header + 25 byte payload */ +#define HDMI_SPD_INFOFRAME_SIZE 29 + +/* + * HDMI 2.0 requires TMDS clock scrambling and a 1/40 bit clock ratio for + * TMDS character rates above 340 MHz. + */ +#define HDMI_TMDS_CLOCK_SCRAMBLE_HZ 340000000 + +/* the driver only ever drives 8 bits per component (no deep color) */ +#define RGB444_8bit BIT(0) +#define YCBCR444_8bit BIT(4) +#define YCBCR420_8bit BIT(12) + +struct mtk_hdmi { + struct udevice *dev; + struct udevice *ddc_bus; + struct udevice *dpi1; + struct udevice *merge3; + struct udevice *merge5; + struct udevice *ethdr; + struct udevice *mutex; + struct udevice *padding4; + struct udevice *padding5; + struct udevice *rdma4; + struct udevice *rdma5; + struct phy phy; + fdt_addr_t regs; + struct clk_bulk clk_bulk; + u64 set_csp_depth; + enum hdmi_colorspace csp; + enum hdmi_colorimetry colorimetry; + struct display_timing mode; +}; + +enum hdmi_hpd_state { + HDMI_PLUG_OUT = 0, + HDMI_PLUG_IN_AND_SINK_POWER_ON, + HDMI_PLUG_IN_ONLY, +}; + +static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) +{ + return readl(hdmi->regs + offset); +} + +static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) +{ + writel(val, hdmi->regs + offset); +} + +static void mtk_hdmi_update(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) +{ + fdt_addr_t reg = hdmi->regs + offset; + u32 tmp; + + tmp = readl(reg); + tmp = (tmp & ~mask) | (val & mask); + writel(tmp, reg); +} + +static void mtk_hdmi_enable_hdmi_mode(struct mtk_hdmi *hdmi, bool enable) +{ + u32 value = enable ? HDMI_MODE_HDMI : 0; + + mtk_hdmi_update(hdmi, TOP_CFG00, value, HDMI_MODE_HDMI); +} + +static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) +{ + if (black) + mtk_hdmi_update(hdmi, TOP_VMUTE_CFG1, REG_VMUTE_EN, REG_VMUTE_EN); + else + mtk_hdmi_update(hdmi, TOP_VMUTE_CFG1, 0, REG_VMUTE_EN); +} + +static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) +{ + mtk_hdmi_update(hdmi, HDMITX_CONFIG_MT8188, 0, HDMITX_SW_RSTB); + udelay(5); + mtk_hdmi_update(hdmi, HDMITX_CONFIG_MT8188, HDMITX_SW_RSTB, HDMITX_SW_RSTB); +} + +static inline void mtk_hdmi_set_sw_hpd(struct mtk_hdmi *hdmi, bool high) +{ + u32 value = high ? HDMITX_SW_HPD : 0; + + mtk_hdmi_update(hdmi, HDMITX_CONFIG_MT8188, value, HDMITX_SW_HPD); +} + +/* + * The driver only ever outputs 8 bits per component, so force 8 bpp and + * disable the deep-color GCP and packets (TMDS_PACK_MODE_8BPP is 0). + */ +static void mtk_hdmi_set_8bit_color(struct mtk_hdmi *hdmi) +{ + mtk_hdmi_update(hdmi, TOP_CFG00, 0, TMDS_PACK_MODE); + mtk_hdmi_update(hdmi, TOP_CFG00, 0, DEEPCOLOR_PKT_EN); + mtk_hdmi_update(hdmi, TOP_MISC_CTLR, 0, DEEP_COLOR_ADD); +} + +static void mtk_hdmi_yuv420_downsample_enable(struct mtk_hdmi *hdmi) +{ + mtk_hdmi_update(hdmi, HDMITX_CONFIG_MT8188, HDMI_YUV420_MODE | HDMITX_SW_HPD, + HDMI_YUV420_MODE | HDMITX_SW_HPD); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, C444_C422_CONFIG_ENABLE, + C444_C422_CONFIG_ENABLE); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, C422_C420_CONFIG_ENABLE, + C422_C420_CONFIG_ENABLE); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, 0, C422_C420_CONFIG_BYPASS); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, + C422_C420_CONFIG_OUT_CB_OR_CR, + C422_C420_CONFIG_OUT_CB_OR_CR); + mtk_hdmi_update(hdmi, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE, + OUTPUT_FORMAT_DEMUX_420_ENABLE); +} + +static void mtk_hdmi_yuv420_downsample_disable(struct mtk_hdmi *hdmi) +{ + mtk_hdmi_update(hdmi, HDMITX_CONFIG_MT8188, HDMITX_SW_HPD, + HDMI_YUV420_MODE | HDMITX_SW_HPD); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, 0, C444_C422_CONFIG_ENABLE); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, 0, C422_C420_CONFIG_ENABLE); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, C422_C420_CONFIG_BYPASS, + C422_C420_CONFIG_BYPASS); + mtk_hdmi_update(hdmi, VID_DOWNSAMPLE_CONFIG, 0, + C422_C420_CONFIG_OUT_CB_OR_CR); + mtk_hdmi_update(hdmi, VID_OUT_FORMAT, 0, OUTPUT_FORMAT_DEMUX_420_ENABLE); +} + +static bool mtk_hdmi_tmds_over_340M(struct mtk_hdmi *hdmi) +{ + /* 8 bpc only, so the TMDS character rate equals the pixel clock */ + unsigned long tmds_clk = hdmi->mode.pixelclock.typ; + + return tmds_clk >= HDMI_TMDS_CLOCK_SCRAMBLE_HZ && + hdmi->csp != HDMI_COLORSPACE_YUV420; +} + +static inline void mtk_hdmi_enable_scrambling(struct mtk_hdmi *hdmi, + bool enable) +{ + udelay(150); + + if (enable) + mtk_hdmi_update(hdmi, TOP_CFG00, SCR_ON | HDMI2_ON, + SCR_ON | HDMI2_ON); + else + mtk_hdmi_update(hdmi, TOP_CFG00, 0, SCR_ON | HDMI2_ON); +} + +static void mtk_hdmi_disable_abist(struct mtk_hdmi *hdmi) +{ + mtk_hdmi_update(hdmi, TOP_CFG00, 0, HDMI_ABIST_ENABLE); +} + +static void mtk_hdmi_change_video_resolution(struct mtk_hdmi *hdmi) +{ + const bool is_hdmi_sink = true; + bool is_over_340M; + + mtk_hdmi_hw_reset(hdmi); + mtk_hdmi_set_sw_hpd(hdmi, true); + udelay(5); + + mtk_hdmi_write(hdmi, HDCP_TOP_CTRL, 0x0); + + mtk_hdmi_set_8bit_color(hdmi); + mtk_hdmi_enable_hdmi_mode(hdmi, is_hdmi_sink); + + udelay(10); + mtk_hdmi_hw_vid_black(hdmi, true); + + mtk_hdmi_update(hdmi, TOP_CFG01, NULL_PKT_VSYNC_HIGH_EN, + NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN); + + is_over_340M = mtk_hdmi_tmds_over_340M(hdmi); + dev_dbg(hdmi->dev, "is_over_340M: %d\n", is_over_340M); + + mtk_hdmi_enable_scrambling(hdmi, is_over_340M); + + if (hdmi->csp == HDMI_COLORSPACE_YUV420) + mtk_hdmi_yuv420_downsample_enable(hdmi); + else + mtk_hdmi_yuv420_downsample_disable(hdmi); +} + +static void mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, + struct display_timing *mode) +{ + unsigned long link_rate = mode->pixelclock.typ; + int ret; + + ret = generic_phy_configure(&hdmi->phy, &link_rate); + if (ret) + dev_err(hdmi->dev, "Setting clock=%u failed: %d\n", + mode->pixelclock.typ, ret); + + mtk_hdmi_change_video_resolution(hdmi); +} + +static void mtk_hdmi_convert_colorspace(struct mtk_hdmi *hdmi) +{ + switch (hdmi->set_csp_depth) { + case YCBCR444_8bit: + hdmi->csp = HDMI_COLORSPACE_YUV444; + break; + case YCBCR420_8bit: + hdmi->csp = HDMI_COLORSPACE_YUV420; + break; + case RGB444_8bit: + default: + hdmi->csp = HDMI_COLORSPACE_RGB; + break; + } + + dev_dbg(hdmi->dev, "color space: %d\n", hdmi->csp); +} + +/* + * Copy at most @dst_len bytes of @src into @dst and pad the remainder with + * spaces. Unlike strlcpy() this does not NUL-terminate, so the full field + * width can be used for the string. + */ +static void mtk_hdmi_pad_string(u8 *dst, size_t dst_len, const char *src) +{ + size_t src_len = strlen(src); + + if (src_len > dst_len) + src_len = dst_len; + + memcpy(dst, src, src_len); + memset(dst + src_len, ' ', dst_len - src_len); +} + +static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, u8 *buffer, + size_t bufsz, const char *vendor, + const char *product) +{ + u8 checksum; + int i; + + if (bufsz < HDMI_SPD_INFOFRAME_SIZE) + return -EINVAL; + + memset(buffer, 0, HDMI_SPD_INFOFRAME_SIZE); + + /* SPD InfoFrame header */ + buffer[0] = 0x83; /* SPD InfoFrame type */ + buffer[1] = 0x01; /* Version */ + buffer[2] = 0x19; /* Length (25 bytes) */ + + /* Vendor name (8 bytes) and product description (16 bytes) */ + mtk_hdmi_pad_string(&buffer[4], 8, vendor); + mtk_hdmi_pad_string(&buffer[12], 16, product); + + /* checksum over the full frame, so that the total sums to zero */ + for (checksum = 0, i = 0; i < HDMI_SPD_INFOFRAME_SIZE; i++) + checksum += buffer[i]; + buffer[3] = 0x100 - checksum; + + return 0; +} + +static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, u8 *buffer, + size_t bufsz, + struct display_timing *mode) +{ + u8 checksum; + int i; + + if (bufsz < HDMI_AVI_INFOFRAME_SIZE) + return -EINVAL; + + memset(buffer, 0, HDMI_AVI_INFOFRAME_SIZE); + + /* AVI InfoFrame header */ + buffer[0] = 0x82; /* AVI InfoFrame type */ + buffer[1] = 0x02; /* Version */ + buffer[2] = 0x0D; /* Length (13 bytes) */ + + /* Data byte 1: Scan info, bar info, active format info, RGB/YCC */ + switch (hdmi->csp) { + case HDMI_COLORSPACE_YUV422: + buffer[4] = 0x20; + break; + case HDMI_COLORSPACE_YUV444: + buffer[4] = 0x40; + break; + case HDMI_COLORSPACE_YUV420: + buffer[4] = 0x60; + break; + default: + buffer[4] = 0x00; + break; + } + + /* Data byte 4: Video Identification Code (VIC) */ + if (mode->hactive.typ == 1920 && mode->vactive.typ == 1080) + buffer[7] = 16; /* 1920x1080@60Hz */ + else if (mode->hactive.typ == 1280 && mode->vactive.typ == 720) + buffer[7] = 4; /* 1280x720@60Hz */ + else if (mode->hactive.typ == 720 && mode->vactive.typ == 480) + buffer[7] = 2; /* 720x480@60Hz */ + else + buffer[7] = 0; /* Unknown/unsupported timing */ + + /* + * Data byte 2: picture aspect ratio, active portion same as + * picture. VIC 2 is a 4:3 mode, the others are 16:9. + */ + buffer[5] = buffer[7] == 2 ? 0x18 : 0x28; + + /* Data byte 3: Colorimetry, picture scaling */ + switch (hdmi->colorimetry) { + case HDMI_COLORIMETRY_ITU_709: + buffer[6] = 0x80; + break; + case HDMI_COLORIMETRY_ITU_601: + buffer[6] = 0x40; + break; + default: + buffer[6] = 0x00; + break; + } + + /* Data byte 5: Pixel repetition */ + buffer[8] = 0x00; /* No pixel repetition */ + + /* checksum over the full frame, so that the total sums to zero */ + for (checksum = 0, i = 0; i < HDMI_AVI_INFOFRAME_SIZE; i++) + checksum += buffer[i]; + buffer[3] = 0x100 - checksum; + + return 0; +} + +static void mtk_hdmi_hw_avi_infoframe(struct mtk_hdmi *hdmi, u8 *buf) +{ + /* Disable AVI InfoFrame first */ + mtk_hdmi_update(hdmi, TOP_INFO_EN, 0, AVI_EN_WR | AVI_EN); + mtk_hdmi_update(hdmi, TOP_INFO_RPT, 0, AVI_RPT_EN); + + /* Write AVI InfoFrame header */ + mtk_hdmi_write(hdmi, TOP_AVI_HEADER, get_unaligned_le24(&buf[0])); + + /* Write AVI InfoFrame data packets */ + mtk_hdmi_write(hdmi, TOP_AVI_PKT00, get_unaligned_le32(&buf[3])); + mtk_hdmi_write(hdmi, TOP_AVI_PKT01, get_unaligned_le24(&buf[7])); + mtk_hdmi_write(hdmi, TOP_AVI_PKT02, get_unaligned_le32(&buf[10])); + mtk_hdmi_write(hdmi, TOP_AVI_PKT03, get_unaligned_le24(&buf[14])); + + /* Clear remaining packets */ + mtk_hdmi_write(hdmi, TOP_AVI_PKT04, 0); + mtk_hdmi_write(hdmi, TOP_AVI_PKT05, 0); + + /* Enable AVI InfoFrame */ + mtk_hdmi_update(hdmi, TOP_INFO_RPT, AVI_RPT_EN, AVI_RPT_EN); + mtk_hdmi_update(hdmi, TOP_INFO_EN, AVI_EN_WR | AVI_EN, + AVI_EN_WR | AVI_EN); +} + +static void mtk_hdmi_hw_spd_infoframe(struct mtk_hdmi *hdmi, u8 *buf) +{ + /* Disable SPD InfoFrame first */ + mtk_hdmi_update(hdmi, TOP_INFO_EN, 0, SPD_EN_WR | SPD_EN); + mtk_hdmi_update(hdmi, TOP_INFO_RPT, 0, SPD_RPT_EN); + + /* Write SPD InfoFrame header */ + mtk_hdmi_write(hdmi, TOP_SPDIF_HEADER, get_unaligned_le24(&buf[0])); + + /* Write SPD InfoFrame data packets */ + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT00, get_unaligned_le32(&buf[3])); + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT01, get_unaligned_le24(&buf[7])); + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT02, get_unaligned_le32(&buf[10])); + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT03, get_unaligned_le24(&buf[14])); + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT04, get_unaligned_le32(&buf[17])); + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT05, get_unaligned_le24(&buf[21])); + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT06, get_unaligned_le32(&buf[24])); + mtk_hdmi_write(hdmi, TOP_SPDIF_PKT07, buf[28]); + + /* Enable SPD InfoFrame */ + mtk_hdmi_update(hdmi, TOP_INFO_RPT, SPD_RPT_EN, SPD_RPT_EN); + mtk_hdmi_update(hdmi, TOP_INFO_EN, SPD_EN_WR | SPD_EN, + SPD_EN_WR | SPD_EN); +} + +static void mtk_hdmi_setup_infoframes(struct mtk_hdmi *hdmi, + struct display_timing *mode) +{ + u8 buffer_spd[HDMI_SPD_INFOFRAME_SIZE]; + u8 buffer_avi[HDMI_AVI_INFOFRAME_SIZE]; + int ret; + + ret = mtk_hdmi_setup_avi_infoframe(hdmi, buffer_avi, + sizeof(buffer_avi), mode); + if (ret) { + dev_warn(hdmi->dev, "Failed to setup AVI infoframe: %d\n", ret); + return; + } + + ret = mtk_hdmi_setup_spd_infoframe(hdmi, buffer_spd, + sizeof(buffer_spd), + "MediaTek", "On-chip HDMI"); + if (ret) { + dev_warn(hdmi->dev, "Failed to setup SPD infoframe: %d\n", ret); + return; + } + + /* Send the infoframes to hardware */ + mtk_hdmi_hw_avi_infoframe(hdmi, buffer_avi); + mtk_hdmi_hw_spd_infoframe(hdmi, buffer_spd); +} + +static void mtk_hdmi_controller_pre_enable(struct mtk_hdmi *hdmi, + struct display_timing *mode) +{ + mtk_hdmi_convert_colorspace(hdmi); + mtk_hdmi_output_set_display_mode(hdmi, mode); + mtk_hdmi_setup_infoframes(hdmi, mode); +} + +static void mtk_hdmi_controller_enable(struct mtk_hdmi *hdmi) +{ + generic_phy_power_on(&hdmi->phy); + mtk_hdmi_hw_vid_black(hdmi, false); +} + +static inline void mtk_hdmi_disable_all_int(struct mtk_hdmi *hdmi) +{ + /* disable all tx irq */ + mtk_hdmi_write(hdmi, TOP_INT_ENABLE00, 0); + mtk_hdmi_write(hdmi, TOP_INT_ENABLE01, 0); +} + +static int mtk_hdmi_read_edid(struct mtk_hdmi *hdmi, u8 *buf, int buf_size) +{ + struct udevice *chip; + int ret; + + if (!hdmi->ddc_bus || buf_size < EDID_SIZE) + return -EINVAL; + + ret = i2c_get_chip(hdmi->ddc_bus, EDID_ADDR, 1, &chip); + if (ret) + return ret; + + ret = dm_i2c_read(chip, 0, buf, EDID_SIZE); + if (ret) { + dev_err(hdmi->dev, "failed to read EDID: %d\n", ret); + return ret; + } + + /* read the extension block, if any */ + if (buf[0x7e] != 0 && buf_size >= EDID_EXT_SIZE) { + ret = dm_i2c_read(chip, EDID_SIZE, buf + EDID_SIZE, + buf_size - EDID_SIZE); + if (ret) + dev_warn(hdmi->dev, + "error reading extended EDID block\n"); + } + + return 0; +} + +static enum hdmi_hpd_state mtk_hdmi_hpd_pord_status(struct mtk_hdmi *hdmi) +{ + unsigned int hpd_status; + + hpd_status = mtk_hdmi_read(hdmi, HPD_DDC_STATUS); + if ((hpd_status & (HPD_PIN_STA | PORD_PIN_STA)) == + (HPD_PIN_STA | PORD_PIN_STA)) + return HDMI_PLUG_IN_AND_SINK_POWER_ON; + else if ((hpd_status & (HPD_PIN_STA | PORD_PIN_STA)) == HPD_PIN_STA) + return HDMI_PLUG_IN_ONLY; + else + return HDMI_PLUG_OUT; +} + +static int mtk_hdmi_wait_for_hpd(struct mtk_hdmi *hdmi) +{ + ulong start = get_timer(0); + + do { + if (mtk_hdmi_hpd_pord_status(hdmi) == + HDMI_PLUG_IN_AND_SINK_POWER_ON) + return 0; + + udelay(100); + } while (get_timer(start) < MTK_HDMI_HPD_TIMEOUT_MS); + + return -ETIMEDOUT; +} + +static bool mtk_hdmi_mode_valid(void *priv, const struct display_timing *timing) +{ + return timing->hactive.typ <= MTK_HDMI_MAX_WIDTH && + timing->vactive.typ <= MTK_HDMI_MAX_HEIGHT; +} + +static int mtk_hdmi_get_display_timing(struct mtk_hdmi *hdmi, + struct display_timing *timing) +{ + u8 edid[EDID_EXT_SIZE]; + int panel_bits_per_colour; + int ret; + + ret = mtk_hdmi_read_edid(hdmi, edid, EDID_EXT_SIZE); + if (ret) + return ret; + + ret = edid_get_timing_validate(edid, EDID_EXT_SIZE, + timing, &panel_bits_per_colour, + mtk_hdmi_mode_valid, NULL); + if (ret) + return ret; + + debug("Display timing:\n clock %u Hz\n", timing->pixelclock.typ); + debug(" hactive: %d,\thfront_p: %d,\thback_p: %d hsync:\t%d\n", + timing->hactive.typ, timing->hfront_porch.typ, + timing->hback_porch.typ, timing->hsync_len.typ); + debug(" vactive: %d,\tvfront_p: %d,\tvback_p: %d vsync:\t%d\n", + timing->vactive.typ, timing->vfront_porch.typ, + timing->vback_porch.typ, timing->vsync_len.typ); + debug(" flags: 0x%x\n", timing->flags); + + return 0; +} + +static void mtk_hdmi_controller_initialize(struct mtk_hdmi *hdmi, + struct display_timing *mode) +{ + mtk_hdmi_disable_all_int(hdmi); + + mtk_hdmi_disable_abist(hdmi); + + mtk_hdmi_controller_pre_enable(hdmi, mode); + + /* let the new configuration settle before unmuting the output */ + mdelay(50); + + mtk_hdmi_controller_enable(hdmi); +} + +static void mtk_hdmi_reset_colorspace_setting(struct mtk_hdmi *hdmi) +{ + hdmi->set_csp_depth = RGB444_8bit; + hdmi->csp = HDMI_COLORSPACE_RGB; + hdmi->colorimetry = HDMI_COLORIMETRY_NONE; +} + +static int mtk_hdmi_get_comp_by_alias(struct udevice *dev, const char *alias, + struct udevice **compp) +{ + struct udevice *comp; + ofnode node; + int ret; + + node = ofnode_get_aliases_node(alias); + if (!ofnode_valid(node)) { + dev_err(dev, "cannot find alias %s\n", alias); + return -ENODEV; + } + + ret = uclass_get_device_by_ofnode(UCLASS_MISC, node, &comp); + if (ret) { + dev_err(dev, "cannot get %s: %d\n", alias, ret); + return ret; + } + + ret = mtk_disp_comp_enable(comp); + if (ret) + return ret; + + /* only publish the handle once its clocks are on, so the error */ + /* unwind can rely on a non-NULL pointer meaning "enabled" */ + *compp = comp; + + return 0; +} + +/* disable the pipeline component clocks, in reverse acquisition order */ +static void mtk_hdmi_disable_components(struct mtk_hdmi *hdmi) +{ + struct udevice *comps[] = { + hdmi->padding5, hdmi->padding4, hdmi->mutex, hdmi->ethdr, + hdmi->merge5, hdmi->merge3, hdmi->rdma5, hdmi->rdma4, + hdmi->dpi1, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(comps); i++) + if (comps[i]) + mtk_disp_comp_disable(comps[i]); +} + +/* program the vdosys1 muxes to route the mixer output to the DPI1/HDMI path */ +static void mtk_hdmi_configure_vdosys1(void __iomem *base) +{ + /* MERGE2_ASYNC_SOUT --> MIXER_IN3_SEL */ + writel(OUTPUT_TO_MIXER_IN3_SEL, base + SUBDISP_MERGE2_ASYNC_SOUT_SEL); + writel(INPUT_FROM_MERGE2_ASYNC_SOUT, base + SUBDISP_MIXER_IN3_SEL_IN); + + /* MIXER_IN3_SOUT --> DISP_MIXER */ + writel(OUTPUT_TO_DISP_MIXER, base + SUBDISP_MIXER_IN3_SOUT_SEL); + + /* DISP_MIXER --> MIXER_SOUT_SEL */ + writel(INPUT_FROM_DISP_MIXER, base + SUBDISP_MIXER_SOUT_SEL_IN); + + /* MIXER_SOUT_SEL --> HDR_VDO_BE0 */ + writel(OUTPUT_TO_HDR_VDO_BE0, base + SUBDISP_MIXER_OUT_SOUT_SEL); + + /* HDR_VDO_BE0 --> MERGE4_ASYNC_SEL */ + writel(INPUT_FROM_HDR_VDO_BE0, base + SUBDISP_MERGE4_ASYNC_SEL_IN); + + /* MERGE4_MOUT_SEL --> DPI1_SEL */ + writel(OUTPUT_TO_DPI1_SEL, base + SUBDISP_DISP_MERGE4_MOUT_SEL); + writel(INPUT_FROM_VPP_MERGE4_MOUT, base + SUBDISP_DISP_DPI1_SEL_IN); +} + +static int mtk_hdmi_probe(struct udevice *dev) +{ + struct mtk_hdmi *hdmi = dev_get_priv(dev); + struct video_priv *priv = dev_get_uclass_priv(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct ofnode_phandle_args args; + struct display_timing timing; + fdt_size_t fb_region_size; + struct udevice *vdosys1; + void __iomem *vdosys1_base; + ofnode node; + int ret; + + hdmi->dev = dev; + + hdmi->regs = dev_read_addr(dev); + if (hdmi->regs == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = clk_get_bulk(dev, &hdmi->clk_bulk); + if (ret) { + dev_err(dev, "failed to get clocks: %d\n", ret); + return ret; + } + + ret = clk_enable_bulk(&hdmi->clk_bulk); + if (ret) { + dev_err(dev, "failed to enable clocks: %d\n", ret); + return ret; + } + + ret = generic_phy_get_by_name(dev, "hdmi", &hdmi->phy); + if (ret) { + dev_err(dev, "failed to get HDMI PHY: %d\n", ret); + goto err_disable_clk; + } + + ret = uclass_get_device_by_ofnode(UCLASS_I2C, + dev_read_subnode(dev, "i2c"), + &hdmi->ddc_bus); + if (ret) { + dev_err(dev, "failed to get DDC I2C bus: %d\n", ret); + goto err_disable_clk; + } + + mtk_hdmi_reset_colorspace_setting(hdmi); + + ret = mtk_hdmi_wait_for_hpd(hdmi); + if (ret) { + dev_err(dev, "display is not connected\n"); + goto err_disable_clk; + } + + ret = mtk_hdmi_get_display_timing(hdmi, &timing); + if (ret) { + dev_err(dev, "failed to get display timing from EDID: %d\n", + ret); + goto err_disable_clk; + } + + hdmi->mode = timing; + /* CEA-861: SD modes use ITU-601 colorimetry, HD modes ITU-709 */ + hdmi->colorimetry = timing.vactive.typ >= 720 ? + HDMI_COLORIMETRY_ITU_709 : HDMI_COLORIMETRY_ITU_601; + + /* this powers on the HDMI PHY */ + mtk_hdmi_controller_initialize(hdmi, &timing); + + /* Set up video private data based on the selected display timing */ + priv->bpix = VIDEO_BPP32; + priv->xsize = timing.hactive.typ; + priv->ysize = timing.vactive.typ; + priv->line_length = priv->xsize * VNBYTES(VIDEO_BPP32); + + plat->size = priv->ysize * priv->line_length; + + /* the framebuffer lives in a dedicated reserved-memory region */ + ret = dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, + &args); + if (ret) { + dev_err(dev, "no framebuffer memory-region: %d\n", ret); + goto err_power_off_phy; + } + + plat->base = ofnode_get_addr_size(args.node, "reg", &fb_region_size); + if (plat->base == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to decode framebuffer region\n"); + ret = -EINVAL; + goto err_power_off_phy; + } + + if (fb_region_size < plat->size) { + dev_err(dev, "framebuffer region too small: %llu < %u\n", + (unsigned long long)fb_region_size, plat->size); + ret = -EINVAL; + goto err_power_off_phy; + } + + ret = mtk_hdmi_get_comp_by_alias(dev, "dpi1", &hdmi->dpi1); + if (ret) + goto err_disable_comps; + + mtk_dpi_hw_enable(hdmi->dpi1); + mtk_dpi_config(hdmi->dpi1, &timing, + hdmi->csp == HDMI_COLORSPACE_RGB); + + ret = mtk_hdmi_get_comp_by_alias(dev, "vdo1-rdma4", &hdmi->rdma4); + if (ret) + goto err_disable_comps; + + ret = mtk_mdp_rdma_config(hdmi->rdma4, plat, &timing, + priv->line_length, false); + if (ret) + goto err_disable_comps; + + ret = mtk_hdmi_get_comp_by_alias(dev, "vdo1-rdma5", &hdmi->rdma5); + if (ret) + goto err_disable_comps; + + ret = mtk_mdp_rdma_config(hdmi->rdma5, plat, &timing, + priv->line_length, true); + if (ret) + goto err_disable_comps; + + /* + * The display routing muxes live in the vdosys1 syscon register block. + * It is a clock provider rather than a pipeline component, so resolve + * it by compatible and grab the register base directly. + */ + node = ofnode_by_compatible(ofnode_null(), "mediatek,mt8188-vdosys1"); + if (!ofnode_valid(node)) { + dev_err(dev, "cannot find vdosys1 node\n"); + ret = -ENODEV; + goto err_disable_comps; + } + + ret = uclass_get_device_by_ofnode(UCLASS_CLK, node, &vdosys1); + if (ret) { + dev_err(dev, "cannot get vdosys1 syscon: %d\n", ret); + goto err_disable_comps; + } + + vdosys1_base = dev_remap_addr(vdosys1); + if (!vdosys1_base) { + ret = -EINVAL; + goto err_disable_comps; + } + + mtk_hdmi_configure_vdosys1(vdosys1_base); + + ret = mtk_hdmi_get_comp_by_alias(dev, "merge3", &hdmi->merge3); + if (ret) + goto err_disable_comps; + + mtk_disp_merge_config(hdmi->merge3, priv->xsize / 2, priv->ysize, + priv->xsize / 2, priv->ysize, + priv->xsize, priv->ysize); + + ret = mtk_hdmi_get_comp_by_alias(dev, "merge5", &hdmi->merge5); + if (ret) + goto err_disable_comps; + + mtk_disp_merge_config(hdmi->merge5, priv->xsize, priv->ysize, 0, 0, + priv->xsize, priv->ysize); + + ret = mtk_hdmi_get_comp_by_alias(dev, "ethdr0", &hdmi->ethdr); + if (ret) + goto err_disable_comps; + + mtk_ethdr_config(hdmi->ethdr, priv->xsize, priv->ysize); + + ret = mtk_hdmi_get_comp_by_alias(dev, "mutex1", &hdmi->mutex); + if (ret) + goto err_disable_comps; + + mtk_disp_mutex_config_hdmi(hdmi->mutex); + + ret = mtk_hdmi_get_comp_by_alias(dev, "padding4", &hdmi->padding4); + if (ret) + goto err_disable_comps; + + mtk_disp_padding_config(hdmi->padding4); + + ret = mtk_hdmi_get_comp_by_alias(dev, "padding5", &hdmi->padding5); + if (ret) + goto err_disable_comps; + + mtk_disp_padding_config(hdmi->padding5); + + video_set_flush_dcache(dev, true); + + return 0; + +err_disable_comps: + mtk_hdmi_disable_components(hdmi); +err_power_off_phy: + generic_phy_power_off(&hdmi->phy); +err_disable_clk: + clk_disable_bulk(&hdmi->clk_bulk); + + return ret; +} + +static const struct udevice_id mtk_hdmi_ids[] = { + { + .compatible = "mediatek,mt8188-hdmi-tx", + }, + { } +}; + +U_BOOT_DRIVER(mtk_hdmi) = { + .name = "mtk_hdmi", + .id = UCLASS_VIDEO, + .of_match = mtk_hdmi_ids, + .probe = mtk_hdmi_probe, + .bind = dm_scan_fdt_dev, + .priv_auto = sizeof(struct mtk_hdmi), +}; diff --git a/drivers/video/mediatek/mtk_hdmi_regs_v2.h b/drivers/video/mediatek/mtk_hdmi_regs_v2.h new file mode 100644 index 00000000000..329bb1a5cfa --- /dev/null +++ b/drivers/video/mediatek/mtk_hdmi_regs_v2.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2021 BayLibre, SAS + * Copyright (c) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#ifndef _MTK_HDMI_REGS_H +#define _MTK_HDMI_REGS_H + +/* HDMI_TOP Config */ +#define TOP_CFG00 0x000 +#define HDMI2_ON BIT(2) +#define HDMI_MODE_HDMI BIT(3) +#define SCR_ON BIT(4) +#define TMDS_PACK_MODE GENMASK(9, 8) +#define TMDS_PACK_MODE_8BPP 0 +#define TMDS_PACK_MODE_10BPP 1 +#define TMDS_PACK_MODE_12BPP 2 +#define TMDS_PACK_MODE_16BPP 3 +#define DEEPCOLOR_PKT_EN BIT(12) +#define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16) +#define HDMI_ABIST_ENABLE BIT(31) +#define TOP_CFG01 0x004 +#define CP_SET_MUTE_EN BIT(0) +#define CP_CLR_MUTE_EN BIT(1) +#define NULL_PKT_EN BIT(2) +#define NULL_PKT_VSYNC_HIGH_EN BIT(3) + +/* HDMI_TOP Audio: Channel Mapping */ +#define TOP_AUD_MAP 0x00c +#define SD0_MAP GENMASK(2, 0) +#define SD1_MAP GENMASK(6, 4) +#define SD2_MAP GENMASK(10, 8) +#define SD3_MAP GENMASK(14, 12) +#define SD4_MAP GENMASK(18, 16) +#define SD5_MAP GENMASK(22, 20) +#define SD6_MAP GENMASK(26, 24) +#define SD7_MAP GENMASK(30, 28) + +/* Auxiliary Video Information (AVI) Infoframe */ +#define TOP_AVI_HEADER 0x024 +#define TOP_AVI_PKT00 0x028 +#define TOP_AVI_PKT01 0x02C +#define TOP_AVI_PKT02 0x030 +#define TOP_AVI_PKT03 0x034 +#define TOP_AVI_PKT04 0x038 +#define TOP_AVI_PKT05 0x03C + +/* Audio Interface Infoframe */ +#define TOP_AIF_HEADER 0x040 +#define TOP_AIF_PKT00 0x044 +#define TOP_AIF_PKT01 0x048 +#define TOP_AIF_PKT02 0x04c +#define TOP_AIF_PKT03 0x050 + +/* Audio SPDIF Infoframe */ +#define TOP_SPDIF_HEADER 0x054 +#define TOP_SPDIF_PKT00 0x058 +#define TOP_SPDIF_PKT01 0x05c +#define TOP_SPDIF_PKT02 0x060 +#define TOP_SPDIF_PKT03 0x064 +#define TOP_SPDIF_PKT04 0x068 +#define TOP_SPDIF_PKT05 0x06c +#define TOP_SPDIF_PKT06 0x070 +#define TOP_SPDIF_PKT07 0x074 + +/* Infoframes Configuration */ +#define TOP_INFO_EN 0x01c +#define AVI_EN BIT(0) +#define SPD_EN BIT(1) +#define AUD_EN BIT(2) +#define CP_EN BIT(5) +#define VSIF_EN BIT(11) +#define AVI_EN_WR BIT(16) +#define SPD_EN_WR BIT(17) +#define AUD_EN_WR BIT(18) +#define CP_EN_WR BIT(21) +#define VSIF_EN_WR BIT(27) +#define TOP_INFO_RPT 0x020 +#define AVI_RPT_EN BIT(0) +#define SPD_RPT_EN BIT(1) +#define AUD_RPT_EN BIT(2) +#define CP_RPT_EN BIT(5) +#define VSIF_RPT_EN BIT(11) + +/* Vendor Specific Infoframe */ +#define TOP_VSIF_HEADER 0x174 +#define TOP_VSIF_PKT00 0x178 +#define TOP_VSIF_PKT01 0x17c +#define TOP_VSIF_PKT02 0x180 +#define TOP_VSIF_PKT03 0x184 +#define TOP_VSIF_PKT04 0x188 +#define TOP_VSIF_PKT05 0x18c +#define TOP_VSIF_PKT06 0x190 +#define TOP_VSIF_PKT07 0x194 + +/* HDMI_TOP Misc */ +#define TOP_MISC_CTLR 0x1a4 +#define DEEP_COLOR_ADD BIT(4) + +/* Hardware interrupts */ +#define TOP_INT_STA00 0x1a8 +#define TOP_INT_ENABLE00 0x1b0 +#define HTPLG_R_INT BIT(0) +#define HTPLG_F_INT BIT(1) +#define PORD_R_INT BIT(2) +#define PORD_F_INT BIT(3) +#define HDMI_VSYNC_INT BIT(4) +#define HDMI_AUDIO_INT BIT(5) +#define HDCP2X_RX_REAUTH_REQ_DDCM_INT BIT(25) +#define TOP_INT_ENABLE01 0x1b4 +#define TOP_INT_CLR00 0x1b8 +#define TOP_INT_CLR01 0x1bc + + +/* Video Mute */ +#define TOP_VMUTE_CFG1 0x1c8 +#define REG_VMUTE_EN BIT(16) + +/* HDMI Audio IP */ +#define AIP_CTRL 0x400 +#define CTS_SW_SEL BIT(0) +#define CTS_REQ_EN BIT(1) +#define MCLK_EN BIT(2) +#define NO_MCLK_CTSGEN_SEL BIT(3) +#define AUD_IN_EN BIT(8) +#define AUD_SEL_OWRT BIT(9) +#define SPDIF_EN BIT(13) +#define HBRA_ON BIT(14) +#define DSD_EN BIT(15) +#define I2S_EN GENMASK(19, 16) +#define HBR_FROM_SPDIF BIT(20) +#define CTS_CAL_N4 BIT(23) +#define SPDIF_INTERNAL_MODULE BIT(24) +#define AIP_N_VAL 0x404 +#define AIP_CTS_SVAL 0x408 +#define AIP_SPDIF_CTRL 0x40c +#define WR_1UI_LOCK BIT(0) +#define FS_OVERRIDE_WRITE BIT(1) +#define WR_2UI_LOCK BIT(2) +#define MAX_1UI_WRITE GENMASK(15, 8) +#define MAX_2UI_SPDIF_WRITE GENMASK(23, 16) +#define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20) +#define MAX_2UI_I2S_LFE_CC_SWAP BIT(1) +#define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16) +#define AUD_ERR_THRESH GENMASK(29, 24) +#define I2S2DSD_EN BIT(30) +#define AIP_I2S_CTRL 0x410 +#define FIFO0_MAP GENMASK(1, 0) +#define FIFO1_MAP GENMASK(3, 2) +#define FIFO2_MAP GENMASK(5, 4) +#define FIFO3_MAP GENMASK(7, 6) +#define I2S_1ST_BIT_NOSHIFT BIT(8) +#define I2S_DATA_DIR_LSB BIT(9) +#define JUSTIFY_RIGHT BIT(10) +#define WS_HIGH BIT(11) +#define VBIT_COMPRESSED BIT(12) +#define CBIT_ORDER_SAME BIT(13) +#define SCK_EDGE_RISE BIT(14) +#define AIP_I2S_CHST0 0x414 +#define AIP_I2S_CHST1 0x418 +#define AIP_TXCTRL 0x424 +#define RST4AUDIO BIT(0) +#define RST4AUDIO_FIFO BIT(1) +#define RST4AUDIO_ACR BIT(2) +#define AUD_LAYOUT_1 BIT(4) +#define AUD_MUTE_FIFO_EN BIT(5) +#define AUD_PACKET_DROP BIT(6) +#define DSD_MUTE_EN BIT(7) +#define AIP_TPI_CTRL 0x428 +#define TPI_AUDIO_LOOKUP_EN BIT(2) + +/* Video downsampling configuration */ +/* + * The MT8390/MT8188 datasheet places this register at 0x8f0, not the 0x8d0 + * used by the upstream Linux header (which appears to be wrong for this SoC). + */ +#define VID_DOWNSAMPLE_CONFIG 0x8f0 +#define C444_C422_CONFIG_ENABLE BIT(0) +#define C422_C420_CONFIG_ENABLE BIT(4) +#define C422_C420_CONFIG_BYPASS BIT(5) +#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6) +#define VID_OUT_FORMAT 0x8fc +#define OUTPUT_FORMAT_DEMUX_420_ENABLE BIT(10) + +/* HDCP registers */ +#define HDCP_TOP_CTRL 0xc00 +#define HDCP2X_CTRL_0 0xc20 +#define HDCP2X_EN BIT(0) +#define HDCP2X_ENCRYPT_EN BIT(7) +#define HDCP2X_HPD_OVR BIT(10) +#define HDCP2X_HPD_SW BIT(11) +#define HDCP2X_POL_CTRL 0xc54 +#define HDCP2X_DIS_POLL_EN BIT(16) +#define HDCP1X_CTRL 0xcd0 +#define HDCP1X_ENC_EN BIT(6) + +/* HDMI DDC registers */ +#define HPD_DDC_CTRL 0xc08 +#define HPD_DDC_DELAY_CNT GENMASK(31, 16) +#define HPD_DDC_HPD_DBNC_EN BIT(2) +#define HPD_DDC_PORD_DBNC_EN BIT(3) +#define DDC_CTRL 0xc10 +#define DDC_CTRL_ADDR GENMASK(7, 1) +#define DDC_CTRL_OFFSET GENMASK(15, 8) +#define DDC_CTRL_DIN_CNT GENMASK(25, 16) +#define DDC_CTRL_CMD GENMASK(31, 28) +#define SCDC_CTRL 0xc18 +#define SCDC_DDC_SEGMENT GENMASK(15, 8) +#define HPD_DDC_STATUS 0xc60 +#define HPD_STATE GENMASK(1, 0) +#define HPD_STATE_CONNECTED 2 +#define HPD_PIN_STA BIT(4) +#define PORD_PIN_STA BIT(5) +#define DDC_I2C_IN_PROG BIT(13) +#define DDC_DATA_OUT GENMASK(23, 16) +#define SI2C_CTRL 0xcac +#define SI2C_WR BIT(0) +#define SI2C_RD BIT(1) +#define SI2C_CONFIRM_READ BIT(2) +#define SI2C_WDATA GENMASK(15, 8) +#define SI2C_ADDR GENMASK(23, 16) + +/* HDCP DDC registers */ +#define HDCP2X_DDCM_STATUS 0xc68 +#define DDC_I2C_NO_ACK BIT(10) +#define DDC_I2C_BUS_LOW BIT(11) + +/* HDMI TX registers */ +#define HDMITX_CONFIG_MT8188 0xea0 +#define HDMITX_CONFIG_MT8195 0x900 +#define HDMI_YUV420_MODE BIT(10) +#define HDMITX_SW_HPD BIT(29) +#define HDMITX_SW_RSTB BIT(31) + +/** + * enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands + * @DDC_CMD_READ_NOACK: Current address read with no ACK on last byte + * @DDC_CMD_READ: Current address read with ACK on last byte + * @DDC_CMD_SEQ_READ_NOACK: Sequential read with no ACK on last byte + * @DDC_CMD_SEQ_READ: Sequential read with ACK on last byte + * @DDC_CMD_ENH_READ_NOACK: Enhanced read with no ACK on last byte + * @DDC_CMD_ENH_READ: Enhanced read with ACK on last byte + * @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte + * @DDC_CMD_SEQ_WRITE: Sequential write requiring ACK on last byte + * @DDC_CMD_RSVD: Reserved for future use + * @DDC_CMD_CLEAR_FIFO: Clear DDC I2C FIFO + * @DDC_CMD_CLOCK_SCL: Start clocking DDC I2C SCL + * @DDC_CMD_ABORT_XFER: Abort DDC I2C transaction + */ +enum mtk_hdmi_ddc_v2_cmds { + DDC_CMD_READ_NOACK = 0x0, + DDC_CMD_READ, + DDC_CMD_SEQ_READ_NOACK, + DDC_CMD_SEQ_READ, + DDC_CMD_ENH_READ_NOACK, + DDC_CMD_ENH_READ, + DDC_CMD_SEQ_WRITE_NOACK, + DDC_CMD_SEQ_WRITE = 0x07, + DDC_CMD_CLEAR_FIFO = 0x09, + DDC_CMD_CLOCK_SCL = 0x0a, + DDC_CMD_ABORT_XFER = 0x0f +}; + +#endif /* _MTK_HDMI_REGS_H */ From patchwork Wed Sep 2 14:16:02 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296696 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=NuN/CSbR; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=Fy5ngIll; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlCw0pkZz1xwg for ; Thu, 03 Sep 2026 00:17:00 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 42BF08108D; Wed, 2 Sep 2026 14:16:58 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 35u7EN3fGYsC; Wed, 2 Sep 2026 14:16:56 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358601; bh=Wx9jTZKIGnt9GRjIRwJ71VMElZ1boGnDobHMLDryY0M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=NuN/CSbRQTg8JyYA6OjrAK+fPtzv+WCNF3QJDF1wFK+BBVoKsSQ/GVhS7WBnd3gIG ++M2Eol/bOTA8/3kvCaAPi6EMsYLr1OzJXi044c29i0ROyZBTMObAHB+uPkYX3s2gZ HAsOspY8rbWXvqPT9Uj0NGb2FiSwNW8BHRShTaViSnAZpRLeaDW8A41r6gOwnqxBLW FySnB9g+1Qguv7hPdtLO3K+McGFJI2dUURwpIlji/iStJQDm7eLF+o9FnKOm3e+mF1 jK2/8ILQ82I1ZVXFJVBmISi4vxzLyHflx62LrLE5BG/kSFlc9e1yWouA63t68gRmNT QlVWQA9u/tCvw== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id F11ED80FAE; Wed, 2 Sep 2026 14:16:40 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp4.osuosl.org (smtp4.osuosl.org [140.211.166.137]) by lists1.osuosl.org (Postfix) with ESMTP id 6AF42230 for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp4.osuosl.org (Postfix) with ESMTP id 5CB8340839 for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp4.osuosl.org ([127.0.0.1]) by localhost (smtp4.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id UNjLGTBTvMll for ; Wed, 2 Sep 2026 14:16:38 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::42b; helo=mail-wr1-x42b.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp4.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp4.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=Fy5ngIll Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by smtp4.osuosl.org (Postfix) with ESMTPS id 31F21406FA for ; Wed, 2 Sep 2026 14:16:37 +0000 (UTC) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-484415c8cb1so850320f8f.2 for ; Wed, 02 Sep 2026 07:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358595; x=1788963395; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Wx9jTZKIGnt9GRjIRwJ71VMElZ1boGnDobHMLDryY0M=; b=Fy5ngIllvImjm5U43x06XdtlXyYt0RV6zXkSVJM7h2jwkh33IyWz3qOErucNIV66Yc 9I6zWvSNwSkK2eoUMyklpmrAE4dl/360gj1Hq9a9/WhIWd56alvkmIImKdWGZjdQJQ4R fKDrWVgGUKmBvve87yNGgix3wuY5vpm+5UG4m1OkFk8uz+8Fl1A59Cc6bXy1KdS4rgll Aj6AFmdt/E1d2u5+DUshyS9e1OV7lPdvk1xYoVABoQrFnyN7Wi3TRbIw5L0ClEo59qd5 mLF0O72rmKjbsu3VZR9sRCylR5MNqxOL9/ySbAMa4nbPt33oZ2/EMC0GU3W9qq6NMwWE S0GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358595; x=1788963395; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Wx9jTZKIGnt9GRjIRwJ71VMElZ1boGnDobHMLDryY0M=; b=NKuBc/0Ja0s3b1LRgnv0w+Cou8cLGvVNLKyVCiPKAkojUdUKYnyYgnQj9z/eTZhyQx MrEtv65kAsmmY6SBVyDnhh0nAGJBFw2AQpnTGR/1UetiMaUaSiVc6lR0uK1zjiBrVFpG tNkWtIMkObXu67nEG7T/whWJO5Mux9SHcszuu0YaXUZS8IiU7oNoG6/NLPvyjhZsz8Sb 0nDH+ypk9CRB/zzzQVE7WddWFh27Lu9EYncGryrWITtmoBL3NqP9ugc7knrLIOKnxW/L 86woLvV9iQIg4SVwA/s3CEOBEx8Z/0ujka3Oj7a/q99JIoqPt+y8H/CDmtCBReSrfu/s nwPw== X-Gm-Message-State: AFuF++nnY24G2GjQTJMWDBLDfPljTqzIsHPel28Ix5PrJDiQv1XnDjEO c9EnYXT/S0Xe2J4aWDpSPf1UUZscuobPvzouC08Ng2b7AQkVmmjLDF6zeSc2/KnGg8I= X-Gm-Gg: AYBFou2kM8HUxV/gT/g8GHUP3xdBvg9gh49ojBroE5YnK2a3xt/TNyry2ATUB/SeVk/ t/lbRcYz/ndSZN+av+Hgvhzrr65xuH1f0TJdndU+iUGLfO3Qz/1+uA7ORMEAbmcG0BDJGS1GBeF 95xPdmb5jOfqPotpSz6VK9J1dVq1SfK68M15cyVzV4/U+KYHOKkxqFjGyh0BsrX+BUnyPHhogC6 LM95zT9/F8IKHcYVoyr6+DJ7IjcBmbVxfd3MfbqHXWYv3tpqNqDLwGe00VEeo+ZUbXEkKe5JQqS WsCm8C+2Ip1DGKet+1KfXD27mpWiAR0XwIDXc9h0cSrODc4BOfhN2OfBVfB+hoowBZQYv/BKrsd FsmpRgWdLI3JgGg8qLWtE3dZ2iGWxHxvOVj8eT/8x1Noc6X2SoN3Nia3e4bnaF1zSn2xwo4VO/5 dkqcJe1D9va1gIHPbruO1kFBgGO8HlAfnV1DteVedergKMjLlF3AuGWitlq2SLmg+EBN8bLLLie 5aCTiL0OtISAO1Cu1G4rdACexr6vt2tZAz58USPhwsqIYL28ebXcL1wJHKKmweffgGTeO9CPaAG YyUoJCJD+RgVQn/ChUNK2BUFnjTmy95ANOIyciHhHH1D X-Received: by 2002:a5d:6f02:0:b0:484:3604:c7bd with SMTP id ffacd0b85a97d-48488f24133mr10507964f8f.17.1788358595353; Wed, 02 Sep 2026 07:16:35 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:35 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:16:02 +0200 Subject: [PATCH v4 12/14] arm: dts: mt8390: add framebuffer reserved-memory MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-12-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org This region is specific to U-Boot and only needed by boards driving the HDMI output, so define it in mt8390-genio-common-u-boot.dtsi (included by the Genio 510 and 700 EVKs) rather than in the SoC-wide mt8188-u-boot.dtsi. It is placed at 0x72000000 to stay clear of the reserved-memory pools declared by the boards using this SoC (the Genio EVKs reserve the range 0x60000000-0x61100000 for the ADSP and AFE DMA pools) and of the kernel load window (the Genio kernel FIT images load and decompress the kernel at 0x64000000). Signed-off-by: Julien Stephan --- arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi | 1 + arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi | 1 + arch/arm/dts/mt8390-genio-common-u-boot.dtsi | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi b/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi index 586d15bf72e..dda05bcf7f4 100644 --- a/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi +++ b/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi @@ -5,3 +5,4 @@ */ #include "mt8188-u-boot.dtsi" +#include "mt8390-genio-common-u-boot.dtsi" diff --git a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi index 586d15bf72e..dda05bcf7f4 100644 --- a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi +++ b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi @@ -5,3 +5,4 @@ */ #include "mt8188-u-boot.dtsi" +#include "mt8390-genio-common-u-boot.dtsi" diff --git a/arch/arm/dts/mt8390-genio-common-u-boot.dtsi b/arch/arm/dts/mt8390-genio-common-u-boot.dtsi new file mode 100644 index 00000000000..a4db2186e2e --- /dev/null +++ b/arch/arm/dts/mt8390-genio-common-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +/ { + reserved-memory { + /* + * Keep this region clear of the board reserved-memory + * pools (the boards using this SoC reserve regions up to + * 0x61100000 for the adsp/afe DMA pools) and of the kernel + * load window: the kernel FIT images load and decompress + * the kernel at 0x64000000. + */ + framebuffer: memory@72000000 { + reg = <0 0x72000000 0 0x02000000>; + no-map; + }; + }; +}; From patchwork Wed Sep 2 14:16:03 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296699 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=wMwsbEds; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=LgZnhZk1; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=140.211.166.138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlD55H6Zz1xwg for ; Thu, 03 Sep 2026 00:17:09 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 8E03180F2F; Wed, 2 Sep 2026 14:17:07 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id Rp1tnjK15aeV; Wed, 2 Sep 2026 14:17:06 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358609; bh=OHF/shYzABG/mP6wplNfvYlGm84JFqGiwG6b4N912Ag=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=wMwsbEdsosOpQ3YLCHWsOVlAlFIhUhkNNU2VXAAZlGqfZXOQ7zpFWfdLgMsfsuoVB uqtgCEQAmt2xChLBZpxg/pCd+oQiQvmCBRbxup73/x3UjeUFSQf1i5T4S3pfwuWOsB hOFz7zlypXbq0BjWVeb3+wW7IvwxKbAtuh4SWH8VJVea6BXbK9PXDCGZ843Pl/Weh7 c6yS1j9LY6+L2DGSe35lt3gNTpuVamKNQHV2N213Mqklo6qkznmQh0580yyUuYsMxh VV5oC9nQ4Ax49+Ab3fooiKNrjpVpCXrPP92TRa3CF4Am1LawN89KDU27U4wu9sAYuD 4aPTxkHrjSs9A== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 60DA680F72; Wed, 2 Sep 2026 14:16:48 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists1.osuosl.org (Postfix) with ESMTP id 59799230 for ; Wed, 2 Sep 2026 14:16:40 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 4B482606CF for ; Wed, 2 Sep 2026 14:16:40 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id deqDpoHXjnrt for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::431; helo=mail-wr1-x431.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp3.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=LgZnhZk1 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by smtp3.osuosl.org (Postfix) with ESMTPS id 68FA6606B4 for ; Wed, 2 Sep 2026 14:16:38 +0000 (UTC) Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-484415c8bf2so890297f8f.0 for ; Wed, 02 Sep 2026 07:16:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358596; x=1788963396; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=OHF/shYzABG/mP6wplNfvYlGm84JFqGiwG6b4N912Ag=; b=LgZnhZk1iogSppoibFDjX1U2JecrD0UxwbyD4GsxsnZvI1f75A4yUde+XB9rDwTfUx rLORsjxnrhW6BhF9P6GN2cl0X5MUSXoABX85ouKa+Fu16sDUm7F7bP2v3f6iGaoijn14 vi5t65NNIMiHWMpz/liUTkl+dniexCMA70ThfsC5GQugCBMsFvMquo6x8x7tKOyH/Wie S4hG1fy8idECC4HRirREu3i7+2IrInjwDsihjyIhvB02nyewoc/uR6jdVIZ8TfcVZuWU kPuI4to9bwLMZ6PVB0Pyf8iVDiGhPLZP9bBzktHzzfHRG7474EThdCIkMUbQUoVUzCDa 4BZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358596; x=1788963396; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=OHF/shYzABG/mP6wplNfvYlGm84JFqGiwG6b4N912Ag=; b=JVlaMeIn2fv+VPN6TzRmyaYzIjssLyzRmfPTUinCKaKFGQw6Z9yNTSdcXQF+KxF4ay Sk9cpaWv+WADW1s25a9k1/HJIMNvaFMd8C+piTqxsK3Fh+1I5GOg2iNKSVHLL6z+3xBD UYGpOnWd5NzQ2nlB5VdmXiFHCf5B8TRcVw7yWZsMbZX/Oh0Tz+0pP8HV5VjeIHhXkvMa tjVoIVKX1B6qtubaKyECfbl4D63YiqZ/gH1hjIpXQA5PYh985yuU083WYXYuIUsRHjXv vQM5nuxS6KdUz5qs9fLFToXBP3K3uhEgHSnRlweNpe01PCHj2doKyGfhVpBpX/Ctb0pq XLyw== X-Gm-Message-State: AFuF++nIUX/NSS2+7r18B/ohUlaI9SDujBVac+F5DPTD1t2YSre/DoQ+ 84JqE0ZrbgmQjeGuvXahn/uhH2Csz0W3jvDU17Q5et9qDVtjWF3zgJg3A7AlN351WfQ= X-Gm-Gg: AYBFou07VLWZ5mF4lKH5cOOHEZysDDJtghYOyoPXfVFSFniptkrQLcYvyT96jXS1/rw UzEdEi+4HqDv9oZDWMUs0VuwrV9ZICXOmI8P5LsTV3ukW/vhdxCxurMTu9I7INYqNcD2NE1vbQX klBjARtmbtUBMSt8lnpuZwpCUdcpQpwMiWhZO43t2qFbASjG/4LO2xaxJqnGIchZyh9F5fKRcjv vGV3uwjURmTDf4qdYKU/hIEnEF4WRsw9wbCTVlzHZ2k600lB8g4B1R8kirH1pwVrOs7M9LWk07K LqYFvz30avLrbjK3v8BdwaPPB8tmifzyhsa7GGmLEopVV5Wflj2TNchCsC5/ekxO+q2s/08AG83 Ekp0DW874HnxoURVvmqOs52BAk2aqUJsxrBrS2vHgPFTyxZkT/tTMYTm57iJo8eCr58bbt/coC4 Cg8W2lcDbUVOwrKFNt1NJXI4rJYEtFKohhpu0jNC0urNJfvZNujFUCXksQY8Zl0NgIR7qpBAdIL EWf4P2QFp5m6eiBIal7wpBi30I1wxzhr/xaX3grCN63siSs5iDxYchN1GK0ZuNWaaGl1fNN2v4a Wp8fG80cVaNzHNJdo4FdgZdJlVZ1n0n+fNmrbf4mDMch X-Received: by 2002:a05:6000:471a:b0:484:3311:3176 with SMTP id ffacd0b85a97d-48488f22290mr9701077f8f.23.1788358596278; Wed, 02 Sep 2026 07:16:36 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:35 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:16:03 +0200 Subject: [PATCH v4 13/14] arm: dts: mt8390: add hdmi override node MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-13-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The mt8188 SoC provides an HDMI encoder and PHY fed through the DPI1 interface attached to the vdosys1 display data path. Add the U-Boot specific bits to mt8390-genio-common-u-boot.dtsi: a "memory-region" phandle on the hdmi node pointing at the framebuffer reserved-memory region; Signed-off-by: Julien Stephan --- arch/arm/dts/mt8390-genio-common-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/mt8390-genio-common-u-boot.dtsi b/arch/arm/dts/mt8390-genio-common-u-boot.dtsi index a4db2186e2e..be1543d1499 100644 --- a/arch/arm/dts/mt8390-genio-common-u-boot.dtsi +++ b/arch/arm/dts/mt8390-genio-common-u-boot.dtsi @@ -19,3 +19,8 @@ }; }; }; + +&hdmi { + /* U-Boot specific: the framebuffer lives in this reserved region */ + memory-region = <&framebuffer>; +}; From patchwork Wed Sep 2 14:16:04 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Stephan X-Patchwork-Id: 2296700 X-Patchwork-Delegate: dlechner@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.u-boot-project.org header.i=@lists.u-boot-project.org header.a=rsa-sha256 header.s=default header.b=k5wDbIzi; dkim=pass (2048-bit key; secure) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=heoh5+Dx; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.u-boot-project.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZlD76pcVz1xwg for ; Thu, 03 Sep 2026 00:17:11 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 5A7858105C; Wed, 2 Sep 2026 14:17:09 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id eRfl0tGnp8vt; Wed, 2 Sep 2026 14:17:07 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=u-boot-bounces@lists.u-boot-project.org; receiver= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lists.u-boot-project.org; s=default; t=1788358610; bh=i7X3K3Qrfl/jwTsv79fOGE5IxYE4sLASeAQZjKwPAYA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=k5wDbIzi+0nFyY29ohYxqNqx7Cp1UBqTYWjx/gKwxDw8IbmzaUDxf69eynhjg/luw RwUGhc4afo+dZA5rUuMpBWw2W8lfCLD3M0vU6HojP3hWuCt0AHgw7cPuENjGxIW3dt mkepVyTy7pmk/mv/lQixUd75ahohSz7uQDy7A7qcRdhTlv72YibqDqZPxM7KB1qhtO G0L7SIBncpubQZjUtsW4B9mtz3dlO0CzyrBt5K/Y2Q2R7BuKZlZMwNHClUzW4CMzLg xClsomuc62GYdYLrC8HcnpuJnZSYRlh+zPnXT1hFRp0qUBWMhXtcTNSY0lNjDQqaG+ IWDMqA7nFNqEg== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 3128980FB0; Wed, 2 Sep 2026 14:16:50 +0000 (UTC) X-Original-To: u-boot@lists.u-boot-project.org Delivered-To: u-boot@lists.u-boot-project.org Received: from smtp2.osuosl.org (smtp2.osuosl.org [140.211.166.133]) by lists1.osuosl.org (Postfix) with ESMTP id 496BA1D9 for ; Wed, 2 Sep 2026 14:16:41 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp2.osuosl.org (Postfix) with ESMTP id 46FD9400A6 for ; Wed, 2 Sep 2026 14:16:41 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp2.osuosl.org ([127.0.0.1]) by localhost (smtp2.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id pWP5dbH01fLa for ; Wed, 2 Sep 2026 14:16:40 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::433; helo=mail-wr1-x433.google.com; envelope-from=jstephan@baylibre.com; receiver= Authentication-Results: smtp2.osuosl.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key) header.d=baylibre.com header.i=@baylibre.com header.a=rsa-sha256 header.s=google header.b=heoh5+Dx Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by smtp2.osuosl.org (Postfix) with ESMTPS id 11E0A4006F for ; Wed, 2 Sep 2026 14:16:39 +0000 (UTC) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-485538d3499so697239f8f.0 for ; Wed, 02 Sep 2026 07:16:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1788358597; x=1788963397; darn=lists.u-boot-project.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=i7X3K3Qrfl/jwTsv79fOGE5IxYE4sLASeAQZjKwPAYA=; b=heoh5+Dx40GqfosMk9xt6cHq2mUKAeZKHv4aIkH89E6hujLFPj4yePTgGHmds7THbD usmRUGbOexZQLDPPJFLX5yvGg4ej972Saimuz796wLk2ZWWfKqZZuLDolTUDlhPwlN8Q 65oU7oMy9taSClMWd4gnoUCCeXH7gYsbzQ5aZjMg3V7X2tRcbz16IcvrE0SAWeFzmUMP mcN4YZA4dHnJLX1IOJiub3F49Y0F/nf3zcaaJ+R4Qw656xEfrKhMIP8I4s7GS37pNlyW LPst5xgQ3uGxYRlCP+EsGyzSBNuViPVpHeU9f1B/tHVWr9hnaUKJJcEdz+J+tNr8g7XR nvLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788358597; x=1788963397; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=i7X3K3Qrfl/jwTsv79fOGE5IxYE4sLASeAQZjKwPAYA=; b=TY3O1eZZkLO0oWl12jOa1TEufccNsNcay/Yc1OJBTxQOmEMA+Z/FDtub+j0xICkasw 1V1MtA7/gMEqEHDyuXFrv25Bsg3oFEkivXIU8JdX6icSKBlRXw2BOziZ6YUnRKMHUD5E HcIwSsYuR199WJ5qUIGjKFu9M8T2akAltrqh6R6U6KXi1VkOgS7EfShhLX9sEJuhP8jF kpAFsaFQEPD31DVLb+njQN3+0LEQIb2R7RMAmyiS8m9bhrOiPxwcjVMSHiah40nnBw3o 3gE2j6XgoNVhpqrTl7ausDFM4tx9kYKcxEnRx8ebGMo1fMNCCk1S9KHS2lJQFytV2jJR +tbg== X-Gm-Message-State: AFuF++moRi+574bkrjRz8rAH8jRhKtENiwkUJnD61aLb4SaVP6Z/bmpo mQpCqbwBdFT25GXWfFdoKehJv8atctCoQMLiPvikOZJXifyTU+iwJ6ntSQHPE1NcvWU= X-Gm-Gg: AYBFou0YY4pgz31IJt2tRdK5ZTw/kN1j7zJiwEx6DbJKCW16RwY3G1rFB3FqlavyF9+ VWsC4VOj3pKP1iC2dtju1+GKrqLWN9I+t/F9NlrV9oBhPS08PU++V1aLBHb3sJTbe6UC6oiwgi/ by6edGsCCxC1DtV5TEoRSUrJojpwxXVnsI6N22lQikOaGutyN78R5OMoh869pkenubz62wCeFw3 6M4qssAOYSVDf4GkcKmFhJwfpxfyIUsEDPC9m4UQhFVJdkBNC6wJhdavDIA5VgagXwanhp4Ygfi 0hZV64k3eE+IB1Sx+Dthm/a1kQj9/S5xEWnxr50CiUA/0AdgvXW2Hx1SX1hcXQzeh1HueQ/+jIS j8qyKYUbHSHq8WBi8pvl0KzgOcuAmftNFfG4+qJsl7MxBTs6U2ZSsIamlL06Wv/4J35uXrZMBIt hWOWMqhG60pSys4JFsw3IiM28JHub4unzbHpBiG3CsRw5e45diSzagHa/HXyx5SR+IOVFUsvV/X zQxWrg5ODnfvcBqPAKYWgyFcxORdoiuUHeU17NtjB4S5FFLxLn0Ison7IpuXxAbDy5P7kjN2VU3 Qma31y43qMaj8PEaLC4H0ZbiSjcVtM8MBCVNfE2Q9G+s X-Received: by 2002:a05:6000:18ab:b0:481:512b:f0e7 with SMTP id ffacd0b85a97d-48488f1898emr9675028f8f.17.1788358597285; Wed, 02 Sep 2026 07:16:37 -0700 (PDT) Received: from [192.168.1.100] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm6619546f8f.18.2026.09.02.07.16.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 07:16:36 -0700 (PDT) From: Julien Stephan Date: Wed, 02 Sep 2026 16:16:04 +0200 Subject: [PATCH v4 14/14] configs: mediatek: mt8188: enable hdmi pipeline MIME-Version: 1.0 Message-Id: <20260902-add-genio-510-and-genio-700-hdmi-v4-14-7c3b4f068a56@baylibre.com> References: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> In-Reply-To: <20260902-add-genio-510-and-genio-700-hdmi-v4-0-7c3b4f068a56@baylibre.com> To: u-boot@lists.u-boot-project.org Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Tom Rini , Anatolij Gustschin , Dario Binacchi , Heinrich Schuchardt , Johan Jonker , Patrice Chotard , Simon Glass , Pavlo Yadvychuk , Macpaul Lin , Ilias Apalodimas , Carlo Caione , Julien Masson , Rasmus Villemoes , Julien Stephan , Mattijs Korpershoek X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Enable the configuration required for the HDMI pipeline on MT8188 based boards such as the Genio 510 EVK (MT8370) and Genio 700 EVK (MT8390): video, the MediaTek HDMI driver, DM I2C for the DDC bus, the PHY uclass and the U-Boot logo. Signed-off-by: Julien Stephan --- configs/mt8188.config | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/mt8188.config b/configs/mt8188.config index c6785476d9a..31468a7f005 100644 --- a/configs/mt8188.config +++ b/configs/mt8188.config @@ -12,16 +12,21 @@ CONFIG_BOOTSTD_FULL=y # CONFIG_BOARD_INIT is not set CONFIG_CMD_CLK=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_OF_UPSTREAM=y CONFIG_CLK=y +CONFIG_DM_I2C=y CONFIG_MMC_MTK=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_POWER_DOMAIN=y CONFIG_MT8188_POWER_DOMAIN=y CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y +CONFIG_VIDEO=y +CONFIG_VIDEO_MEDIATEK_HDMI=y # CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_WDT=y CONFIG_WDT_MTK=y