From patchwork Wed Sep 2 08:38:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruv Chawla X-Patchwork-Id: 2296449 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=PiHTdI8l; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=38.145.34.32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZbmg4QdYz1xwg for ; Wed, 02 Sep 2026 18:41:23 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5A1924BA901D for ; Wed, 2 Sep 2026 08:41:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5A1924BA901D Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=PiHTdI8l X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011071.outbound.protection.outlook.com [52.101.57.71]) by sourceware.org (Postfix) with ESMTPS id 80CA04BA23E2 for ; Wed, 2 Sep 2026 08:39:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 80CA04BA23E2 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=nvidia.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 80CA04BA23E2 Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=52.101.57.71 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338364; cv=pass; b=XYe8hpi/sw9fE3YbcKM8EL+svNX0tJmhdPnBloo7r+9cKFgoOb0f5DsbfxxdgRYl2nMhAPvUagL/dvizKGQVMQGxhGlUXZPk4hKn/S79M4TVxeOgfFw+ct6Tc91ssdigPJAnSSJQ9eNe8xXvMKaobJHmM7lH4ALokHYazCP+p48= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338364; c=relaxed/simple; bh=0M0e1WIFAkAFYGCgAaXtH82HZLyY2dHi9mz+txpnYlI=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=nmRutTCSqHh7mfjZMw8CoGDAwSMRAinuBuGzpS+7/Hf4M69iC5HFafW4ULLZVkVB7RIT40sFnUkX8i3FDLL0bh56pQP0xPvRB7CCW710by81ZIu/QNh/ft74tOk4ZKWP763EK78y+ZW7cDHrCTVhvPmG9d0YovLaSUYeWenJQDI= ARC-Authentication-Results: i=2; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=PiHTdI8l DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 80CA04BA23E2 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rklJ2c2uX0/nSp7g7qG3ojPTqEUP+cn3Gr7YTRY0nG1F+m25roaYHC6vLJ+IUF0HSATqt8kDDuNr30ZoANKNbSu3KR+nWKoiVmOJ+53yGMvVJhXwyK+bQV5o5ELVWM05Lpp6mb/Pa+117b2kV7XNy4R8ws1mbMxovTmRK1iUiAUwwILPmnMORHVNTM1R4/Jwo1Osd6sQfSdRgwE48yl9/Hr/SaFLDYsglfRMYZo9R/atc2stUYvg1w1nJk1JfFzL6D691CDpjos/VNz3J4J9oX1hjZbjWylpzq64l46se4da4TY8GYrEGu7h5o48w2dKLm+dXZSaPbzV18rkxzTypg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6M+N850CfaGyGd7S4QCDYbtV/2Rmp9MFBtmzcpND4mA=; b=E6oe5+0B1VWy2ovchfT8ZdMsBpDd0O8z0d2LSm/eSMGtDlmB0UvCJtXtz49xSAVd+WTh2ZTAyOTCskqd8/nlnWN2EorScCytnI/tVIypYoqwbNs10UlfdCcnlXtxszM91cTiWvZU8CW7GjKVP73EccvHcX3Y5Z7un9GoenaBLR0hdmqgIEiu0P479fdF7M9eI5D4klKnEz0F6tz5Z01Hh/LxFT/IhJACX9KKKIH78X4qOjLnBIntp8qLUYfb6VSbUgZmXmH0Crn6iMNeOdO9knfWU+17mcZkGAPxwGKaMQezlHpj++MvcfNBVgcgKh6eMUsO+xe+Dr3UyZHq5U2JgA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6M+N850CfaGyGd7S4QCDYbtV/2Rmp9MFBtmzcpND4mA=; b=PiHTdI8lHKLLR70qYkck3b1SJT77QVRgP6z4fKHBQwjwToD6txk542Guw2vcg0TMqB1cgUb0boNLlvYFKLNhN5LE3gR7djWbAldPqo9fZrBEtChldB8e9TtPzcQ7DRT022JD8rcFdnXc3pJImXl5j7Yn+hHILudWHm83QPApnP6LPd6YPWVbAxmvqSmyEsHdFQPdP2ESd3/Mj268QzN2aCBYK3Cv8Pj8jeztRSMQ5JUPl1eHKTwFrgGAYvUcAyn8YWA+xz7gYdKIS5HwjT0U5FaxrWcwPjQIooEgG7qs+vk2qTMngzK2M1Dd/JWmRdP/lD7fOXu26iYx7YkAGM1YqQ== Received: from SA9P223CA0022.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::27) by SN7PR12MB6983.namprd12.prod.outlook.com (2603:10b6:806:261::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.17; Wed, 2 Sep 2026 08:39:10 +0000 Received: from SN1PEPF00036F40.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::66) by SA9P223CA0022.outlook.office365.com (2603:10b6:806:26::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.360.13 via Frontend Transport; Wed, 2 Sep 2026 08:39:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF00036F40.mail.protection.outlook.com (10.167.248.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Wed, 2 Sep 2026 08:39:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:38:55 -0700 Received: from MVD4TP25H0.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:38:53 -0700 From: To: CC: , Subject: [PATCH 1/6] aarch64: Port NEON saturating add/sub intrinsics to pragma-based framework Date: Wed, 2 Sep 2026 14:08:23 +0530 Message-ID: <20260902083828.45767-2-dhruvc@nvidia.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260902083828.45767-1-dhruvc@nvidia.com> References: <20260902083828.45767-1-dhruvc@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F40:EE_|SN7PR12MB6983:EE_ X-MS-Office365-Filtering-Correlation-Id: cd2b3e07-d8b9-410b-27ea-08df08cda90f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|23010399003|1800799024|376014|22082099003|18002099003|3023799007|56012099006|13003099007|6133799003|10067099003|11063799006; X-Microsoft-Antispam-Message-Info: NfiS296KYQnsrgKCa1LVAfQfHep+IhpuxgIt4sdNbVyxhZqa26g8TrgjFj5JlRXH7FoEoEji6bHuNIsw2yd7SUtQ9uBXJw4hvsGqbppsbkz6dO3qB3GEW2KMdCHtt7PLyhOVKRAvyLh6DuF/JfyCMef1vvakzLPlzn+LrbZYLgaGwgvZjmapyt4DzC/5q+kR8UpiScQEBIQ9wceaN7/NUO7QwGRLPpkUFlZpDdS9A2Z3vYa5uYmg0rSMn6Hcrn75A+mCDIgxq62KXAP1C37EyblYxwOP0/U8BiMpHeg1fm45TROEKzH7YqBTxN40dTUsMLs6ja3T0l9GI8bV32g7uOpIk07qMT4czUHFFYGS8Y7ofDRv2eANQUN+8TynvfXqyIqwj8jvOxb1D284ZICbwkEbdGFinUjfJB8XLrGlXnLO3ytnXSTkEXUgxBM5f0kxxLGbFlnzTwvn6pDV8G98AyOkWXF4LKctyyh3r/6mgVjlCZjgZuNrPufqkRGZTlfbJtjGHP/grWw1SWdME9ZwfGSZjJt6feiB/9nC6ntJG7VeDhsQIh9GXFkR0Q+w9OIt+i6y8mTAZK8xXPVnj32YaXPRn5NIGYowm88psny6lOEsFxyJjGl4+c62AHO0xpY1Fy0YH9TCT1KCn2iVB4Ksb9mvOrLrS+EQKHlNAoRLIkhsuAurCxXNCTTCIlkFgiXBv9n7je4iRfpoi25NrpHClA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(82310400026)(23010399003)(1800799024)(376014)(22082099003)(18002099003)(3023799007)(56012099006)(13003099007)(6133799003)(10067099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: twqmnCmxscjx9GgpyRwsHKQtOBJLFVm4/tih/BP1MFmOqRkW87vS2+we39QIxXIXt15wd4Xfn34VWe/+wW/RzbxEx24KT57V4XTs6ZpPB1ymUNzCNBF7Fxz5+qp6r5SKxWeFYA2YNCegaQT3Q/RH4j042Rm4fgTh/DAaN5Y6qRVhTTwVIwz1UlGHJDXqC3N+TNGJXEVYLgkjj79NDyPsOw0nEL/24qhue6rCjqgnVs1gBsaHpBrrkSGwlMp9gTDZ3x6uWl88R2GsN8b5yw2OaL7op3kFyQNWq4Oj+SFE6iaOQMZuoR3/4/e/ytqWZQ4ZUSA+zt/R7gvnl2+whrP78tftxbWBo3utDSnvcL9E2ETJvB9IEr2dvdxyKvAxUc2+hRnx0BpgM0PNM03w7UzlpF8HrdaWTzsYOw1Oi+mYvxdmKNgiTkci4o8GgmL2AJVC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 08:39:10.5967 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd2b3e07-d8b9-410b-27ea-08df08cda90f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F40.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6983 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Dhruv Chawla Port the following intrinsics to the pragma-based framework: * vqadd * vqsub Plus their scalar variants: vq{add,sub}{b,h,s,d}. The following are not ported in this patch as they cannot be directly lowered from an IFN through an existing instruction pattern: * vqadd_s64 * vqadd_u64 * vqsub_s64 * vqsub_u64 This is because the pattern does not iterate through the modes (V1DI) required to lower them (it uses the VSDQ_I_QI_HI iterator). Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla gcc/ChangeLog: * config/aarch64/aarch64-neon-builtins-base.cc (vqaddb, vqaddh, vqadds, vqaddd, vqadd, vqaddq, vqsubb, vqsubh, vqsubs, vqsubd, vqsub, vqsubq): New function bases. * config/aarch64/aarch64-neon-builtins-base.def (vqaddb, vqaddh, vqadds, vqaddd, vqadd, vqaddq, vqsubb, vqsubh, vqsubs, vqsubd, vqsub, vqsubq): New function groups. * config/aarch64/arm_neon.h (vqadd_s8, vqadd_s16, vqadd_s32, vqadd_u8, vqadd_u16, vqadd_u32, vqaddq_s8, vqaddq_s16, vqaddq_s32, vqaddq_s64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_s8, vqsub_s16, vqsub_s32, vqsub_u8, vqsub_u16, vqsub_u32, vqsubq_s8, vqsubq_s16, vqsubq_s32, vqsubq_s64, vqsubq_u8, vqsubq_u16, vqsubq_u32, vqsubq_u64, vqaddb_s8, vqaddh_s16, vqadds_s32, vqaddd_s64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqsubb_s8, vqsubh_s16, vqsubs_s32, vqsubd_s64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64): Delete functions. (vqadd_s64): Relocate to be grouped with the other {s,u}64 functions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/neon/vqadd.c: New test. * gcc.target/aarch64/neon/vqsub.c: Likewise. --- .../aarch64/aarch64-neon-builtins-base.cc | 14 + .../aarch64/aarch64-neon-builtins-base.def | 16 + gcc/config/aarch64/arm_neon.h | 318 +----------------- gcc/testsuite/gcc.target/aarch64/neon/vqadd.c | 192 +++++++++++ gcc/testsuite/gcc.target/aarch64/neon/vqsub.c | 192 +++++++++++ 5 files changed, 417 insertions(+), 315 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vqadd.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vqsub.c diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index d8fae81388e..5c886d32f42 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -753,6 +753,20 @@ NEON_FUNCTION (vaddd, gimple_expr, (PLUS_EXPR)) NEON_FUNCTION (vadd, gimple_expr, (PLUS_EXPR, PLUS_EXPR, BIT_XOR_EXPR)) NEON_FUNCTION (vaddq, gimple_expr, (PLUS_EXPR, PLUS_EXPR, BIT_XOR_EXPR)) +// Saturating arithmetic +NEON_FUNCTION (vqaddb, gimple_ifn, (IFN_SAT_ADD)) +NEON_FUNCTION (vqaddh, gimple_ifn, (IFN_SAT_ADD)) +NEON_FUNCTION (vqadds, gimple_ifn, (IFN_SAT_ADD)) +NEON_FUNCTION (vqaddd, gimple_ifn, (IFN_SAT_ADD)) +NEON_FUNCTION (vqadd, gimple_ifn, (IFN_SAT_ADD)) +NEON_FUNCTION (vqaddq, gimple_ifn, (IFN_SAT_ADD)) +NEON_FUNCTION (vqsubb, gimple_ifn, (IFN_SAT_SUB)) +NEON_FUNCTION (vqsubh, gimple_ifn, (IFN_SAT_SUB)) +NEON_FUNCTION (vqsubs, gimple_ifn, (IFN_SAT_SUB)) +NEON_FUNCTION (vqsubd, gimple_ifn, (IFN_SAT_SUB)) +NEON_FUNCTION (vqsub, gimple_ifn, (IFN_SAT_SUB)) +NEON_FUNCTION (vqsubq, gimple_ifn, (IFN_SAT_SUB)) + // Bitwise operations NEON_FUNCTION (vand, gimple_expr, (BIT_AND_EXPR)) NEON_FUNCTION (vandq, gimple_expr, (BIT_AND_EXPR)) diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index 7257f59bbc5..52e4746453b 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -76,6 +76,22 @@ DEF_NEON_FUNCTION (vadd, h_float, ("D0,D0,D0")) DEF_NEON_FUNCTION (vaddq, h_float, ("Q0,Q0,Q0")) #undef REQUIRED_EXTENSIONS +// Saturating arithmetic +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) +DEF_NEON_FUNCTION (vqaddb, b_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqaddh, h_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqadds, s_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqaddd, d_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqadd, bhs_integer, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vqaddq, all_integer, ("Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vqsubb, b_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqsubh, h_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqsubs, s_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqsubd, d_integer, ("s0,s0,s0")) +DEF_NEON_FUNCTION (vqsub, bhs_integer, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vqsubq, all_integer, ("Q0,Q0,Q0")) +#undef REQUIRED_EXTENSIONS + // Bitwise operations #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) DEF_NEON_FUNCTION (vand, all_integer, ("D0,D0,D0")) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 873a1195d3e..985b4bdb6cc 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -1071,41 +1071,6 @@ vsubw_high_u32 (uint64x2_t __a, uint32x4_t __b) return __builtin_aarch64_usubw2v4si_uuu (__a, __b); } -__extension__ extern __inline int8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadd_s8 (int8x8_t __a, int8x8_t __b) -{ - return (int8x8_t) __builtin_aarch64_ssaddv8qi (__a, __b); -} - -__extension__ extern __inline int16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadd_s16 (int16x4_t __a, int16x4_t __b) -{ - return (int16x4_t) __builtin_aarch64_ssaddv4hi (__a, __b); -} - -__extension__ extern __inline int32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadd_s32 (int32x2_t __a, int32x2_t __b) -{ - return (int32x2_t) __builtin_aarch64_ssaddv2si (__a, __b); -} - -__extension__ extern __inline int64x1_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadd_s64 (int64x1_t __a, int64x1_t __b) -{ - return (int64x1_t) {__builtin_aarch64_ssadddi (__a[0], __b[0])}; -} - -__extension__ extern __inline uint8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadd_u8 (uint8x8_t __a, uint8x8_t __b) -{ - return __builtin_aarch64_usaddv8qi_uuu (__a, __b); -} - __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vhsub_s8 (int8x8_t __a, int8x8_t __b) @@ -1358,18 +1323,11 @@ vsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c) return __builtin_aarch64_subhn2v2di_uuuu (__a, __b, __c); } -__extension__ extern __inline uint16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadd_u16 (uint16x4_t __a, uint16x4_t __b) -{ - return __builtin_aarch64_usaddv4hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x2_t +__extension__ extern __inline int64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadd_u32 (uint32x2_t __a, uint32x2_t __b) +vqadd_s64 (int64x1_t __a, int64x1_t __b) { - return __builtin_aarch64_usaddv2si_uuu (__a, __b); + return (int64x1_t) {__builtin_aarch64_ssadddi (__a[0], __b[0])}; } __extension__ extern __inline uint64x1_t @@ -1379,83 +1337,6 @@ vqadd_u64 (uint64x1_t __a, uint64x1_t __b) return (uint64x1_t) {__builtin_aarch64_usadddi_uuu (__a[0], __b[0])}; } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_s8 (int8x16_t __a, int8x16_t __b) -{ - return (int8x16_t) __builtin_aarch64_ssaddv16qi (__a, __b); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_s16 (int16x8_t __a, int16x8_t __b) -{ - return (int16x8_t) __builtin_aarch64_ssaddv8hi (__a, __b); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_s32 (int32x4_t __a, int32x4_t __b) -{ - return (int32x4_t) __builtin_aarch64_ssaddv4si (__a, __b); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_s64 (int64x2_t __a, int64x2_t __b) -{ - return (int64x2_t) __builtin_aarch64_ssaddv2di (__a, __b); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_u8 (uint8x16_t __a, uint8x16_t __b) -{ - return __builtin_aarch64_usaddv16qi_uuu (__a, __b); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_u16 (uint16x8_t __a, uint16x8_t __b) -{ - return __builtin_aarch64_usaddv8hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return __builtin_aarch64_usaddv4si_uuu (__a, __b); -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddq_u64 (uint64x2_t __a, uint64x2_t __b) -{ - return __builtin_aarch64_usaddv2di_uuu (__a, __b); -} - -__extension__ extern __inline int8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsub_s8 (int8x8_t __a, int8x8_t __b) -{ - return (int8x8_t) __builtin_aarch64_sssubv8qi (__a, __b); -} - -__extension__ extern __inline int16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsub_s16 (int16x4_t __a, int16x4_t __b) -{ - return (int16x4_t) __builtin_aarch64_sssubv4hi (__a, __b); -} - -__extension__ extern __inline int32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsub_s32 (int32x2_t __a, int32x2_t __b) -{ - return (int32x2_t) __builtin_aarch64_sssubv2si (__a, __b); -} - __extension__ extern __inline int64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqsub_s64 (int64x1_t __a, int64x1_t __b) @@ -1463,27 +1344,6 @@ vqsub_s64 (int64x1_t __a, int64x1_t __b) return (int64x1_t) {__builtin_aarch64_sssubdi (__a[0], __b[0])}; } -__extension__ extern __inline uint8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsub_u8 (uint8x8_t __a, uint8x8_t __b) -{ - return __builtin_aarch64_ussubv8qi_uuu (__a, __b); -} - -__extension__ extern __inline uint16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsub_u16 (uint16x4_t __a, uint16x4_t __b) -{ - return __builtin_aarch64_ussubv4hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsub_u32 (uint32x2_t __a, uint32x2_t __b) -{ - return __builtin_aarch64_ussubv2si_uuu (__a, __b); -} - __extension__ extern __inline uint64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqsub_u64 (uint64x1_t __a, uint64x1_t __b) @@ -1491,62 +1351,6 @@ vqsub_u64 (uint64x1_t __a, uint64x1_t __b) return (uint64x1_t) {__builtin_aarch64_ussubdi_uuu (__a[0], __b[0])}; } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_s8 (int8x16_t __a, int8x16_t __b) -{ - return (int8x16_t) __builtin_aarch64_sssubv16qi (__a, __b); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_s16 (int16x8_t __a, int16x8_t __b) -{ - return (int16x8_t) __builtin_aarch64_sssubv8hi (__a, __b); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_s32 (int32x4_t __a, int32x4_t __b) -{ - return (int32x4_t) __builtin_aarch64_sssubv4si (__a, __b); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_s64 (int64x2_t __a, int64x2_t __b) -{ - return (int64x2_t) __builtin_aarch64_sssubv2di (__a, __b); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_u8 (uint8x16_t __a, uint8x16_t __b) -{ - return __builtin_aarch64_ussubv16qi_uuu (__a, __b); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_u16 (uint16x8_t __a, uint16x8_t __b) -{ - return __builtin_aarch64_ussubv8hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return __builtin_aarch64_ussubv4si_uuu (__a, __b); -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubq_u64 (uint64x2_t __a, uint64x2_t __b) -{ - return __builtin_aarch64_ussubv2di_uuu (__a, __b); -} - __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqneg_s8 (int8x8_t __a) @@ -13921,64 +13725,6 @@ vqabsd_s64 (int64_t __a) return __builtin_aarch64_sqabsdi (__a); } -/* vqadd */ - -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddb_s8 (int8_t __a, int8_t __b) -{ - return (int8_t) __builtin_aarch64_ssaddqi (__a, __b); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddh_s16 (int16_t __a, int16_t __b) -{ - return (int16_t) __builtin_aarch64_ssaddhi (__a, __b); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadds_s32 (int32_t __a, int32_t __b) -{ - return (int32_t) __builtin_aarch64_ssaddsi (__a, __b); -} - -__extension__ extern __inline int64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddd_s64 (int64_t __a, int64_t __b) -{ - return __builtin_aarch64_ssadddi (__a, __b); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddb_u8 (uint8_t __a, uint8_t __b) -{ - return (uint8_t) __builtin_aarch64_usaddqi_uuu (__a, __b); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddh_u16 (uint16_t __a, uint16_t __b) -{ - return (uint16_t) __builtin_aarch64_usaddhi_uuu (__a, __b); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqadds_u32 (uint32_t __a, uint32_t __b) -{ - return (uint32_t) __builtin_aarch64_usaddsi_uuu (__a, __b); -} - -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqaddd_u64 (uint64_t __a, uint64_t __b) -{ - return __builtin_aarch64_usadddi_uuu (__a, __b); -} - /* vqdmlal */ __extension__ extern __inline int32x4_t @@ -15620,64 +15366,6 @@ vqshrund_n_s64 (int64_t __a, const int __b) return (int32_t) __builtin_aarch64_sqshrun_ndi (__a, __b); } -/* vqsub */ - -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubb_s8 (int8_t __a, int8_t __b) -{ - return (int8_t) __builtin_aarch64_sssubqi (__a, __b); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubh_s16 (int16_t __a, int16_t __b) -{ - return (int16_t) __builtin_aarch64_sssubhi (__a, __b); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubs_s32 (int32_t __a, int32_t __b) -{ - return (int32_t) __builtin_aarch64_sssubsi (__a, __b); -} - -__extension__ extern __inline int64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubd_s64 (int64_t __a, int64_t __b) -{ - return __builtin_aarch64_sssubdi (__a, __b); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubb_u8 (uint8_t __a, uint8_t __b) -{ - return (uint8_t) __builtin_aarch64_ussubqi_uuu (__a, __b); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubh_u16 (uint16_t __a, uint16_t __b) -{ - return (uint16_t) __builtin_aarch64_ussubhi_uuu (__a, __b); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubs_u32 (uint32_t __a, uint32_t __b) -{ - return (uint32_t) __builtin_aarch64_ussubsi_uuu (__a, __b); -} - -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vqsubd_u64 (uint64_t __a, uint64_t __b) -{ - return __builtin_aarch64_ussubdi_uuu (__a, __b); -} - /* vqtbl2 */ __extension__ extern __inline int8x8_t diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vqadd.c b/gcc/testsuite/gcc.target/aarch64/neon/vqadd.c new file mode 100644 index 00000000000..322f54c5a42 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vqadd.c @@ -0,0 +1,192 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vqadd_u8: +** uqadd v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_u8, uint8x8_t) + +/* +** test_vqadd_s8: +** sqadd v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_s8, int8x8_t) + +/* +** test_vqadd_u16: +** uqadd v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_u16, uint16x4_t) + +/* +** test_vqadd_s16: +** sqadd v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_s16, int16x4_t) + +/* +** test_vqadd_u32: +** uqadd v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_u32, uint32x2_t) + +/* +** test_vqadd_s32: +** sqadd v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_s32, int32x2_t) + +/* +** test_vqadd_u64: +** uqadd d0, (d0, d1|d1, d0) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_u64, uint64x1_t) + +/* +** test_vqadd_s64: +** sqadd d0, (d0, d1|d1, d0) +** ret +*/ +TEST_UNIFORM_BINARY (vqadd_s64, int64x1_t) + +/* +** test_vqaddq_u8: +** uqadd v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_u8, uint8x16_t) + +/* +** test_vqaddq_s8: +** sqadd v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_s8, int8x16_t) + +/* +** test_vqaddq_u16: +** uqadd v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_u16, uint16x8_t) + +/* +** test_vqaddq_s16: +** sqadd v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_s16, int16x8_t) + +/* +** test_vqaddq_u32: +** uqadd v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_u32, uint32x4_t) + +/* +** test_vqaddq_s32: +** sqadd v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_s32, int32x4_t) + +/* +** test_vqaddq_u64: +** uqadd v0\.2d, (v0\.2d, v1\.2d|v1\.2d, v0\.2d) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_u64, uint64x2_t) + +/* +** test_vqaddq_s64: +** sqadd v0\.2d, (v0\.2d, v1\.2d|v1\.2d, v0\.2d) +** ret +*/ +TEST_UNIFORM_BINARY (vqaddq_s64, int64x2_t) + +/* +** test_vqaddb_u8: +** dup v([0-9]+)\.8b, w[0-9]+ +** dup v([0-9]+)\.8b, w[0-9]+ +** uqadd b([0-9]+), (b\2, b\1|b\1, b\2) +** umov w0, v\3\.b\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqaddb_u8, uint8_t) + +/* +** test_vqaddb_s8: +** dup v([0-9]+)\.8b, w[0-9]+ +** dup v([0-9]+)\.8b, w[0-9]+ +** sqadd b([0-9]+), (b\2, b\1|b\1, b\2) +** umov w0, v\3\.b\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqaddb_s8, int8_t) + +/* +** test_vqaddh_u16: +** dup v([0-9]+)\.4h, w[0-9]+ +** dup v([0-9]+)\.4h, w[0-9]+ +** uqadd h([0-9]+), (h\2, h\1|h\1, h\2) +** umov w0, v\3\.h\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqaddh_u16, uint16_t) + +/* +** test_vqaddh_s16: +** dup v([0-9]+)\.4h, w[0-9]+ +** dup v([0-9]+)\.4h, w[0-9]+ +** sqadd h([0-9]+), (h\2, h\1|h\1, h\2) +** umov w0, v\3\.h\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqaddh_s16, int16_t) + +/* +** test_vqadds_u32: +** adds (w[0-9]+), (w0, w1|w1, w0) +** csinv w0, \1, wzr, cc +** ret +*/ +TEST_UNIFORM_BINARY (vqadds_u32, uint32_t) + +/* +** test_vqadds_s32: +** fmov (s[0-9]+), w[0-9]+ +** fmov (s[0-9]+), w[0-9]+ +** sqadd s([0-9]+), (\2, \1|\1, \2) +** fmov w0, s\3 +** ret +*/ +TEST_UNIFORM_BINARY (vqadds_s32, int32_t) + +/* +** test_vqaddd_u64: +** adds (x[0-9]+), (x0, x1|x1, x0) +** csinv x0, \1, xzr, cc +** ret +*/ +TEST_UNIFORM_BINARY (vqaddd_u64, uint64_t) + +/* +** test_vqaddd_s64: +** fmov (d[0-9]+), x[0-9]+ +** fmov (d[0-9]+), x[0-9]+ +** sqadd d([0-9]+), (\2, \1|\1, \2) +** fmov x0, d\3 +** ret +*/ +TEST_UNIFORM_BINARY (vqaddd_s64, int64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vqsub.c b/gcc/testsuite/gcc.target/aarch64/neon/vqsub.c new file mode 100644 index 00000000000..52ac2f102eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vqsub.c @@ -0,0 +1,192 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vqsub_u8: +** uqsub v0\.8b, v0\.8b, v1\.8b +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_u8, uint8x8_t) + +/* +** test_vqsub_s8: +** sqsub v0\.8b, v0\.8b, v1\.8b +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_s8, int8x8_t) + +/* +** test_vqsub_u16: +** uqsub v0\.4h, v0\.4h, v1\.4h +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_u16, uint16x4_t) + +/* +** test_vqsub_s16: +** sqsub v0\.4h, v0\.4h, v1\.4h +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_s16, int16x4_t) + +/* +** test_vqsub_u32: +** uqsub v0\.2s, v0\.2s, v1\.2s +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_u32, uint32x2_t) + +/* +** test_vqsub_s32: +** sqsub v0\.2s, v0\.2s, v1\.2s +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_s32, int32x2_t) + +/* +** test_vqsub_u64: +** uqsub d0, d0, d1 +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_u64, uint64x1_t) + +/* +** test_vqsub_s64: +** sqsub d0, d0, d1 +** ret +*/ +TEST_UNIFORM_BINARY (vqsub_s64, int64x1_t) + +/* +** test_vqsubq_u8: +** uqsub v0\.16b, v0\.16b, v1\.16b +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_u8, uint8x16_t) + +/* +** test_vqsubq_s8: +** sqsub v0\.16b, v0\.16b, v1\.16b +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_s8, int8x16_t) + +/* +** test_vqsubq_u16: +** uqsub v0\.8h, v0\.8h, v1\.8h +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_u16, uint16x8_t) + +/* +** test_vqsubq_s16: +** sqsub v0\.8h, v0\.8h, v1\.8h +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_s16, int16x8_t) + +/* +** test_vqsubq_u32: +** uqsub v0\.4s, v0\.4s, v1\.4s +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_u32, uint32x4_t) + +/* +** test_vqsubq_s32: +** sqsub v0\.4s, v0\.4s, v1\.4s +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_s32, int32x4_t) + +/* +** test_vqsubq_u64: +** uqsub v0\.2d, v0\.2d, v1\.2d +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_u64, uint64x2_t) + +/* +** test_vqsubq_s64: +** sqsub v0\.2d, v0\.2d, v1\.2d +** ret +*/ +TEST_UNIFORM_BINARY (vqsubq_s64, int64x2_t) + +/* +** test_vqsubb_u8: +** dup v([0-9]+)\.8b, w0 +** dup v([0-9]+)\.8b, w1 +** uqsub b([0-9]+), b\1, b\2 +** umov w0, v\3\.b\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqsubb_u8, uint8_t) + +/* +** test_vqsubb_s8: +** dup v([0-9]+)\.8b, w0 +** dup v([0-9]+)\.8b, w1 +** sqsub b([0-9]+), b\1, b\2 +** umov w0, v\3\.b\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqsubb_s8, int8_t) + +/* +** test_vqsubh_u16: +** dup v([0-9]+)\.4h, w0 +** dup v([0-9]+)\.4h, w1 +** uqsub h([0-9]+), h\1, h\2 +** umov w0, v\3\.h\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqsubh_u16, uint16_t) + +/* +** test_vqsubh_s16: +** dup v([0-9]+)\.4h, w0 +** dup v([0-9]+)\.4h, w1 +** sqsub h([0-9]+), h\1, h\2 +** umov w0, v\3\.h\[0\] +** ret +*/ +TEST_UNIFORM_BINARY (vqsubh_s16, int16_t) + +/* +** test_vqsubs_u32: +** subs (w[0-9]+), w0, w1 +** csel w0, \1, wzr, cs +** ret +*/ +TEST_UNIFORM_BINARY (vqsubs_u32, uint32_t) + +/* +** test_vqsubs_s32: +** fmov (s[0-9]+), w0 +** fmov (s[0-9]+), w1 +** sqsub s([0-9]+), \1, \2 +** fmov w0, s\3 +** ret +*/ +TEST_UNIFORM_BINARY (vqsubs_s32, int32_t) + +/* +** test_vqsubd_u64: +** subs (x[0-9]+), x0, x1 +** csel x0, \1, xzr, cs +** ret +*/ +TEST_UNIFORM_BINARY (vqsubd_u64, uint64_t) + +/* +** test_vqsubd_s64: +** fmov (d[0-9]+), x0 +** fmov (d[0-9]+), x1 +** sqsub d([0-9]+), \1, \2 +** fmov x0, d\3 +** ret +*/ +TEST_UNIFORM_BINARY (vqsubd_s64, int64_t) From patchwork Wed Sep 2 08:38:24 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruv Chawla X-Patchwork-Id: 2296450 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=Tu6tTP3u; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZbn41czMz1xwg for ; Wed, 02 Sep 2026 18:41:44 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BE3244BA23C1 for ; Wed, 2 Sep 2026 08:41:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BE3244BA23C1 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=Tu6tTP3u X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azlp170110003.outbound.protection.outlook.com [IPv6:2a01:111:f403:c110::3]) by sourceware.org (Postfix) with ESMTPS id C48244BA798C for ; Wed, 2 Sep 2026 08:39:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C48244BA798C Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=nvidia.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C48244BA798C Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=2a01:111:f403:c110::3 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338364; cv=pass; b=flOXGcW2UOfelXiyDlFzLedqZt9qQb8+xB17OCtX6m+MMhjEYxRIHTYXCrGMyIQXsk2vQUp3u4veSVTh3iV3VNlGjPFgqwDElXY2Q2VFfQuB5fwc3VUXgSTmzPXX3DBtd2J26pjVz3t+orvsvlFIMRpZY/Sq173/IY5igkSsVDU= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338364; c=relaxed/simple; bh=C42qg10X0xqbcosrls/DMD65+KHmnQbMcy4jQCbJeWY=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=ehh9Vyry5hCscsQnW75lx5GFEcMbGQcyPgHOcQimMySwQ6YYkjzgpgGCY29+L3Di8X/BY4SkAd5js9NQKyA/XCHoaPO8kEy+pOxv/BgejarDA42I1QnEBoRtuDZi8GMH2Ge0m6BxurVJCnYI2cpCDQH2SuQ9rytahlVbWPix00k= ARC-Authentication-Results: i=2; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=Tu6tTP3u DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C48244BA798C ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ctaAfnFmkPenIaG4CKueKq6FaUua3TozTQRGzMbWihRBG+C3jzgsNNvK0WWkti4CjTrfFNlhhRdf2f+yP1BsLnpS79BPO+QQUNgsnu9o466yjxU+lOZvT/4bd5QHSeWWzZ+JNfQL8uyFyFflfRf8wcwXjKDv3X0pQLCZ1oaoT6ZLHyRHWrdiVVv+lWbu7k5rHOK5r6HCOX3StxGq/0Vf+id6XFmG+kaqSQSe8F4Fnk8yHpFzNg+7oX6NPW6PcCbYypsucUQSu/P0gMFtmE5aYvCdlB8UQlcGN3MfpuySx4rD+Rxed/gFiXQOOovZhUiamj1HVAqztB8tmaGfBM3HPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EndAmYcdFMYSU3WX5HD/74uuHUqWyPibrJsvt8PDfLc=; b=fny4voSq330DPr7KOXKuy1C4YlYPjwgGI+NWE2MOh7gDlkW9JlY7s6j4YKnEe5nryOLUdzTxe34VIAul6BR7XzsVTmWjD/qbKIml+tlD3VF/kWaFiXIsr6f1zvKJ+7M8q2H4xtcRBYICbVn9CrnYyHxMtmAkfK1y8vxettXEuCUbE5zet/QOyEuTiq+PQbEc0KdBxEJRwyY0Mb3vIslxA1g2nERGU/xdXThGjSaF6rC1fvhYv6lnj9iYHN9asQHkmpTm/GW72+RUAhhZUJ2Cq7leD823Ayaktjl1rM7RHDWoILPeKYjKK38qGLot3DratnNVmowxdAa5Pw5AWYcIhQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EndAmYcdFMYSU3WX5HD/74uuHUqWyPibrJsvt8PDfLc=; b=Tu6tTP3uU8X59z+993mZk7tB38PFDTMcnQVno1re8hkeTC06iEWGmauHsohKS9UbPSfoPIHM/fXnniwtqoVu1m4fgkoR54eXlEADqhB/0u+jIirE8a/SIJWSDGbe04FkEPcWaKbDIHzS3fer0+OoEf4rDXkylURkQBh3r/oweS9IkLfTUOXm4Qk2U/YKd+Dxpiw9GYkYYtkFsxvnWNSJmvwxmihqP7ElPwZVsEWzHQGTEJcSD7YiRtVai2kICUlUbHTg5Lewpm8xVKnq7c+iohp/5Tg9ArybMZ4LUjItW2tJQfXs+rRTCTMkUDF13Pg5gd0cTxCoyKzVmDo8DypNpQ== Received: from DM6PR08CA0038.namprd08.prod.outlook.com (2603:10b6:5:1e0::12) by CH1PR12MB9696.namprd12.prod.outlook.com (2603:10b6:610:2b0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.13; Wed, 2 Sep 2026 08:39:11 +0000 Received: from DS3PEPF000099E2.namprd04.prod.outlook.com (2603:10b6:5:1e0:cafe::8f) by DM6PR08CA0038.outlook.office365.com (2603:10b6:5:1e0::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.11 via Frontend Transport; Wed, 2 Sep 2026 08:39:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Wed, 2 Sep 2026 08:39:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:38:57 -0700 Received: from MVD4TP25H0.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:38:55 -0700 From: To: CC: , Subject: [PATCH 2/6] aarch64: Port NEON reduction intrinsics to pragma-based framework Date: Wed, 2 Sep 2026 14:08:24 +0530 Message-ID: <20260902083828.45767-3-dhruvc@nvidia.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260902083828.45767-1-dhruvc@nvidia.com> References: <20260902083828.45767-1-dhruvc@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|CH1PR12MB9696:EE_ X-MS-Office365-Filtering-Correlation-Id: 80b9433e-9e35-4d60-0f9e-08df08cda91b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700016|23010399003|82310400026|56012099006|10067099003|11063799006|5023799004|6133799003|3023799007|18002099003|22082099003|13003099007; X-Microsoft-Antispam-Message-Info: nb8G/nQhhePT1eVPP2axW4nm41lA88W6RICYwleYU/XzVuR/e+9rEhbspCrjlgbiA9kcPV9zNJ0zhUm1FbIhYuIOLuvFYVkmkZbD/TcxHeFXnDy1VaHjKcBujJFm2AWWeR7p6AGuaeLq4rndQUbU/5ir87nuXV/raM2UzqrdaO19cia5WkeOrjyGqiT05G2niHcbxnQFu/GQ43/iHt2yOcFBhhkKzGrx8f3qNJeReobhc8ncf7F7mP/eKK5IB+S3QC9Mry7NbYn0jJtJJRAf8K/XboUJfKb+Igkup90pNckFTQR+ZtOcJcRW/aFHysgJs0jxMwibm63VgRs76EDe0oHyL8TX52XadkYrDO8/19y3+AWb834oqsx1GE2xfZzwPd5BykdVR6GsgluIJyadQd8/s2yQOxzUEtjuhdxBhwdxZj52/ZsnUNHjkI6cfDMZbvG/ncJjeO77OZCBG8SGGSiX1oShV+GVsJ3ODiw4Cj/6Zswa2to2DaetCAD+K0DEpmWrHZMqzrHJ+0cfuhkJ+0FQn2yQnIaTNktHIU2FxWFIrp6pEakJ0NWd6hahEcpxGrVLU8eKSMcRyG9LbwRRxXacqF2iZKaA/k4u7DnWLkZQ02LQptjCJ6JM02DL+B736WCYvUigGAEbIgKp9y1DTqo0I9cbweEdgforicrGjgNOM+sp1WddGmEvlrW7UL6i1CBKPO7vBxSl3t4OSFf4bw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700016)(23010399003)(82310400026)(56012099006)(10067099003)(11063799006)(5023799004)(6133799003)(3023799007)(18002099003)(22082099003)(13003099007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GpfGrp2dRwZt0IDXDThCiGSkPn2gsZBo24DbLduGbk839c4JCXWan5lvJJWLdqO/68F3Erq5w5WzUzB+pCrcCHHeQ+NiyOLgaPon+LORnVwVXbeCp+UceHnNfwwOb/KbiKPSQxhypLx64k/e9RTLBOkvf6gNlZpWZyRZNEGnyvq/0LwTICjHsp8cBa2+1ruIcVoJ1MDE0yOX20KDJ4C3C7AAjL0FBWNU8H6ZWVsn5Obgb/mcsxjw5GsC3McNinYwR5jtpC3NZmvHXocWq1JvoJ7v/VVdCkGZTr99aPC65hvGhMo8yEQgZnPXNKQsdE7xEx4DNK3swzBSpxzCJn2j5tyEAZBAcKUJVMhaAK0jk60euK3EeB/4KT67jdMzz09rlIvgAgBH7TLKfl+i3qapZDWX4TwYZy6aDJuPsjlV2DHxILCw1RGoYppjVt7r06FP X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 08:39:10.6841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80b9433e-9e35-4d60-0f9e-08df08cda91b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9696 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Dhruv Chawla Port the following intrinsics to the pragma-based framework: * vaddv * vmaxv * vminv * vmaxnmv * vminnmv The following are not ported in this patch as they cannot be directly lowered from an IFN through an existing instruction pattern: * vmaxv_f16 * vmaxv_f32 * vmaxvq_f16 * vmaxvq_f32 * vmaxvq_f64 * vminv_f16 * vminv_f32 * vminvq_f16 * vminvq_f32 * vminvq_f64 This is due to the NaN semantics of these intrinsics which require mapping to _nan variants. Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla gcc/ChangeLog: * config/aarch64/aarch64-acle-builtins.h (TYPES_s_float_bhs_integer, TYPES_sd_float_all_integer, s_float_bhs_integer, sd_float_all_integer): New type lists. * config/aarch64/aarch64-neon-builtins-base.cc (vaddv, vaddvq, vmaxv, vmaxvq, vminv, vminvq, vmaxnmv, vmaxnmvq, vminnmv, vminnmvq): New function bases. * config/aarch64/aarch64-neon-builtins-base.def (vaddv, vaddvq, vmaxv, vmaxvq, vminv, vminvq, vmaxnmv, vmaxnmvq, vminnmv, vminnmvq): New function groups. * config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8, vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64, vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32, vaddvq_f64, vmaxv_s8, vmaxv_s16, vmaxv_s32, vmaxv_u8, vmaxv_u16, vmaxv_u32, vmaxvq_s8, vmaxvq_s16, vmaxvq_s32, vmaxvq_u8, vmaxvq_u16, vmaxvq_u32, vmaxnmv_f32, vmaxnmvq_f32, vmaxnmvq_f64, vminv_s8, vminv_s16, vminv_s32, vminv_u8, vminv_u16, vminv_u32, vminvq_s8, vminvq_s16, vminvq_s32, vminvq_u8, vminvq_u16, vminvq_u32, vminnmv_f32, vminnmvq_f32, vminnmvq_f64, vmaxnmv_f16, vmaxnmvq_f16, vminnmv_f16, vminnmvq_f16): Delete functions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/neon/vaddv.c: New test. * gcc.target/aarch64/neon/vmaxnmv.c: New test. * gcc.target/aarch64/neon/vmaxv.c: New test. * gcc.target/aarch64/neon/vminnmv.c: New test. * gcc.target/aarch64/neon/vminv.c: New test. --- gcc/config/aarch64/aarch64-acle-builtins.h | 14 + .../aarch64/aarch64-neon-builtins-base.cc | 12 + .../aarch64/aarch64-neon-builtins-base.def | 22 ++ gcc/config/aarch64/arm_neon.h | 363 ------------------ gcc/testsuite/gcc.target/aarch64/neon/vaddv.c | 138 +++++++ .../gcc.target/aarch64/neon/vmaxnmv.c | 39 ++ gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c | 135 +++++++ .../gcc.target/aarch64/neon/vminnmv.c | 39 ++ gcc/testsuite/gcc.target/aarch64/neon/vminv.c | 135 +++++++ 9 files changed, 534 insertions(+), 363 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vaddv.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxnmv.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminnmv.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminv.c diff --git a/gcc/config/aarch64/aarch64-acle-builtins.h b/gcc/config/aarch64/aarch64-acle-builtins.h index 481a294c938..afbcafa7822 100644 --- a/gcc/config/aarch64/aarch64-acle-builtins.h +++ b/gcc/config/aarch64/aarch64-acle-builtins.h @@ -1393,6 +1393,18 @@ function_expander::result_mode () const #define TYPES_s_float_sd_integer(S, D, T) \ TYPES_s_float (S, D, T), TYPES_sd_integer (S, D, T) +/* _f32 + _s8 _s16 _s32 + _u8 _u16 _u32. */ +#define TYPES_s_float_bhs_integer(S, D, T) \ + TYPES_s_float (S, D, T), TYPES_bhs_integer (S, D, T) + +/* _f32 _f64 + _s8 _s16 _s32 _s64 + _u8 _u16 _u32 _u64. */ +#define TYPES_sd_float_all_integer(S, D, T) \ + TYPES_sd_float (S, D, T), TYPES_all_integer (S, D, T) + /* _s32. */ #define TYPES_s_signed(S, D, T) \ S (s32) @@ -2084,6 +2096,8 @@ DEF_SVE_TYPES_ARRAY (hsd_integer); DEF_SVE_TYPES_ARRAY (hsd_data); DEF_SVE_TYPES_ARRAY (s_float); DEF_SVE_TYPES_ARRAY (s_float_hsd_integer); +DEF_SVE_TYPES_ARRAY (s_float_bhs_integer); +DEF_SVE_TYPES_ARRAY (sd_float_all_integer); DEF_SVE_TYPES_ARRAY (s_float_mf8); DEF_SVE_TYPES_ARRAY (s_float_sd_integer); DEF_SVE_TYPES_ARRAY (s_signed); diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index 5c886d32f42..ca122d65a51 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -767,6 +767,18 @@ NEON_FUNCTION (vqsubd, gimple_ifn, (IFN_SAT_SUB)) NEON_FUNCTION (vqsub, gimple_ifn, (IFN_SAT_SUB)) NEON_FUNCTION (vqsubq, gimple_ifn, (IFN_SAT_SUB)) +// Reductions +NEON_FUNCTION (vaddv, gimple_ifn, (IFN_REDUC_PLUS)) +NEON_FUNCTION (vaddvq, gimple_ifn, (IFN_REDUC_PLUS)) +NEON_FUNCTION (vmaxv, gimple_ifn, (IFN_REDUC_MAX)) +NEON_FUNCTION (vmaxvq, gimple_ifn, (IFN_REDUC_MAX)) +NEON_FUNCTION (vminv, gimple_ifn, (IFN_REDUC_MIN)) +NEON_FUNCTION (vminvq, gimple_ifn, (IFN_REDUC_MIN)) +NEON_FUNCTION (vmaxnmv, gimple_ifn, (IFN_REDUC_FMAX)) +NEON_FUNCTION (vmaxnmvq, gimple_ifn, (IFN_REDUC_FMAX)) +NEON_FUNCTION (vminnmv, gimple_ifn, (IFN_REDUC_FMIN)) +NEON_FUNCTION (vminnmvq, gimple_ifn, (IFN_REDUC_FMIN)) + // Bitwise operations NEON_FUNCTION (vand, gimple_expr, (BIT_AND_EXPR)) NEON_FUNCTION (vandq, gimple_expr, (BIT_AND_EXPR)) diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index 52e4746453b..b3c0fc42298 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -92,6 +92,28 @@ DEF_NEON_FUNCTION (vqsub, bhs_integer, ("D0,D0,D0")) DEF_NEON_FUNCTION (vqsubq, all_integer, ("Q0,Q0,Q0")) #undef REQUIRED_EXTENSIONS +// Reductions +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) +DEF_NEON_FUNCTION (vaddv, s_float_bhs_integer, ("s0,D0")) +DEF_NEON_FUNCTION (vaddvq, sd_float_all_integer, ("s0,Q0")) +DEF_NEON_FUNCTION (vmaxv, bhs_integer, ("s0,D0")) +DEF_NEON_FUNCTION (vmaxvq, bhs_integer, ("s0,Q0")) +DEF_NEON_FUNCTION (vminv, bhs_integer, ("s0,D0")) +DEF_NEON_FUNCTION (vminvq, bhs_integer, ("s0,Q0")) +DEF_NEON_FUNCTION (vmaxnmv, s_float, ("s0,D0")) +DEF_NEON_FUNCTION (vmaxnmvq, sd_float, ("s0,Q0")) +DEF_NEON_FUNCTION (vminnmv, s_float, ("s0,D0")) +DEF_NEON_FUNCTION (vminnmvq, sd_float, ("s0,Q0")) +#undef REQUIRED_EXTENSIONS + +// Reductions (FP16) +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD | AARCH64_FL_F16) +DEF_NEON_FUNCTION (vmaxnmv, h_float, ("s0,D0")) +DEF_NEON_FUNCTION (vmaxnmvq, h_float, ("s0,Q0")) +DEF_NEON_FUNCTION (vminnmv, h_float, ("s0,D0")) +DEF_NEON_FUNCTION (vminnmvq, h_float, ("s0,Q0")) +#undef REQUIRED_EXTENSIONS + // Bitwise operations #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) DEF_NEON_FUNCTION (vand, all_integer, ("D0,D0,D0")) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 985b4bdb6cc..1fccc7e3237 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -5083,127 +5083,6 @@ vabsd_s64 (int64_t __a) return __a < 0 ? - (uint64_t) __a : __a; } -/* vaddv */ - -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddv_s8 (int8x8_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v8qi (__a); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddv_s16 (int16x4_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v4hi (__a); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddv_s32 (int32x2_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v2si (__a); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddv_u8 (uint8x8_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v8qi_uu (__a); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddv_u16 (uint16x4_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v4hi_uu (__a); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddv_u32 (uint32x2_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v2si_uu (__a); -} - -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_s8 (int8x16_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v16qi (__a); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_s16 (int16x8_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v8hi (__a); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_s32 (int32x4_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v4si (__a); -} - -__extension__ extern __inline int64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_s64 (int64x2_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v2di (__a); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_u8 (uint8x16_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v16qi_uu (__a); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_u16 (uint16x8_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v8hi_uu (__a); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_u32 (uint32x4_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v4si_uu (__a); -} - -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_u64 (uint64x2_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v2di_uu (__a); -} - -__extension__ extern __inline float32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddv_f32 (float32x2_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v2sf (__a); -} - -__extension__ extern __inline float32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v4sf (__a); -} - -__extension__ extern __inline float64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vaddvq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_reduc_plus_scal_v2df (__a); -} - /* ARMv8.1-A intrinsics. */ #pragma GCC push_options #pragma GCC target ("+nothing+rdma") @@ -12393,48 +12272,6 @@ vmaxv_f32 (float32x2_t __a) return __builtin_aarch64_reduc_smax_nan_scal_v2sf (__a); } -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxv_s8 (int8x8_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v8qi (__a); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxv_s16 (int16x4_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v4hi (__a); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxv_s32 (int32x2_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v2si (__a); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxv_u8 (uint8x8_t __a) -{ - return __builtin_aarch64_reduc_umax_scal_v8qi_uu (__a); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxv_u16 (uint16x4_t __a) -{ - return __builtin_aarch64_reduc_umax_scal_v4hi_uu (__a); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxv_u32 (uint32x2_t __a) -{ - return __builtin_aarch64_reduc_umax_scal_v2si_uu (__a); -} - __extension__ extern __inline float32_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmaxvq_f32 (float32x4_t __a) @@ -12449,71 +12286,6 @@ vmaxvq_f64 (float64x2_t __a) return __builtin_aarch64_reduc_smax_nan_scal_v2df (__a); } -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxvq_s8 (int8x16_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v16qi (__a); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxvq_s16 (int16x8_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v8hi (__a); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxvq_s32 (int32x4_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v4si (__a); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxvq_u8 (uint8x16_t __a) -{ - return __builtin_aarch64_reduc_umax_scal_v16qi_uu (__a); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxvq_u16 (uint16x8_t __a) -{ - return __builtin_aarch64_reduc_umax_scal_v8hi_uu (__a); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxvq_u32 (uint32x4_t __a) -{ - return __builtin_aarch64_reduc_umax_scal_v4si_uu (__a); -} - -/* vmaxnmv */ - -__extension__ extern __inline float32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmv_f32 (float32x2_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v2sf (__a); -} - -__extension__ extern __inline float32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmvq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v4sf (__a); -} - -__extension__ extern __inline float64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmvq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v2df (__a); -} - /* vmin */ __extension__ extern __inline float32x2_t @@ -12677,48 +12449,6 @@ vminv_f32 (float32x2_t __a) return __builtin_aarch64_reduc_smin_nan_scal_v2sf (__a); } -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminv_s8 (int8x8_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v8qi (__a); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminv_s16 (int16x4_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v4hi (__a); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminv_s32 (int32x2_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v2si (__a); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminv_u8 (uint8x8_t __a) -{ - return __builtin_aarch64_reduc_umin_scal_v8qi_uu (__a); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminv_u16 (uint16x4_t __a) -{ - return __builtin_aarch64_reduc_umin_scal_v4hi_uu (__a); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminv_u32 (uint32x2_t __a) -{ - return __builtin_aarch64_reduc_umin_scal_v2si_uu (__a); -} - __extension__ extern __inline float32_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vminvq_f32 (float32x4_t __a) @@ -12733,71 +12463,6 @@ vminvq_f64 (float64x2_t __a) return __builtin_aarch64_reduc_smin_nan_scal_v2df (__a); } -__extension__ extern __inline int8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminvq_s8 (int8x16_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v16qi (__a); -} - -__extension__ extern __inline int16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminvq_s16 (int16x8_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v8hi (__a); -} - -__extension__ extern __inline int32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminvq_s32 (int32x4_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v4si (__a); -} - -__extension__ extern __inline uint8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminvq_u8 (uint8x16_t __a) -{ - return __builtin_aarch64_reduc_umin_scal_v16qi_uu (__a); -} - -__extension__ extern __inline uint16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminvq_u16 (uint16x8_t __a) -{ - return __builtin_aarch64_reduc_umin_scal_v8hi_uu (__a); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminvq_u32 (uint32x4_t __a) -{ - return __builtin_aarch64_reduc_umin_scal_v4si_uu (__a); -} - -/* vminnmv */ - -__extension__ extern __inline float32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmv_f32 (float32x2_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v2sf (__a); -} - -__extension__ extern __inline float32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmvq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v4sf (__a); -} - -__extension__ extern __inline float64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmvq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v2df (__a); -} - /* vmla */ __extension__ extern __inline float32x2_t @@ -20541,34 +20206,6 @@ vminvq_f16 (float16x8_t __a) return __builtin_aarch64_reduc_smin_nan_scal_v8hf (__a); } -__extension__ extern __inline float16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmv_f16 (float16x4_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v4hf (__a); -} - -__extension__ extern __inline float16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmvq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_reduc_smax_scal_v8hf (__a); -} - -__extension__ extern __inline float16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmv_f16 (float16x4_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v4hf (__a); -} - -__extension__ extern __inline float16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmvq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_reduc_smin_scal_v8hf (__a); -} - #pragma GCC pop_options /* AdvSIMD Dot Product intrinsics. */ diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vaddv.c b/gcc/testsuite/gcc.target/aarch64/neon/vaddv.c new file mode 100644 index 00000000000..43b91b102cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vaddv.c @@ -0,0 +1,138 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vaddv_u8: +** addv b([0-9]+), v0\.8b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vaddv_u8, uint8_t, uint8x8_t) + +/* +** test_vaddv_s8: +** addv b([0-9]+), v0\.8b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vaddv_s8, int8_t, int8x8_t) + +/* +** test_vaddv_u16: +** addv h([0-9]+), v0\.4h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vaddv_u16, uint16_t, uint16x4_t) + +/* +** test_vaddv_s16: +** addv h([0-9]+), v0\.4h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vaddv_s16, int16_t, int16x4_t) + +/* +** test_vaddv_u32: +** addp v([0-9]+)\.2s, v0\.2s, v0\.2s +** fmov w0, s\1 +** ret +*/ +TEST_UNARY (vaddv_u32, uint32_t, uint32x2_t) + +/* +** test_vaddv_s32: +** addp v([0-9]+)\.2s, v0\.2s, v0\.2s +** fmov w0, s\1 +** ret +*/ +TEST_UNARY (vaddv_s32, int32_t, int32x2_t) + +/* +** test_vaddvq_u8: +** addv b([0-9]+), v0\.16b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vaddvq_u8, uint8_t, uint8x16_t) + +/* +** test_vaddvq_s8: +** addv b([0-9]+), v0\.16b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vaddvq_s8, int8_t, int8x16_t) + +/* +** test_vaddvq_u16: +** addv h([0-9]+), v0\.8h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vaddvq_u16, uint16_t, uint16x8_t) + +/* +** test_vaddvq_s16: +** addv h([0-9]+), v0\.8h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vaddvq_s16, int16_t, int16x8_t) + +/* +** test_vaddvq_u32: +** addv (s[0-9]+), v0\.4s +** fmov w0, \1 +** ret +*/ +TEST_UNARY (vaddvq_u32, uint32_t, uint32x4_t) + +/* +** test_vaddvq_s32: +** addv (s[0-9]+), v0\.4s +** fmov w0, \1 +** ret +*/ +TEST_UNARY (vaddvq_s32, int32_t, int32x4_t) + +/* +** test_vaddvq_u64: +** addp (d[0-9]+), v0\.2d +** fmov x0, \1 +** ret +*/ +TEST_UNARY (vaddvq_u64, uint64_t, uint64x2_t) + +/* +** test_vaddvq_s64: +** addp (d[0-9]+), v0\.2d +** fmov x0, \1 +** ret +*/ +TEST_UNARY (vaddvq_s64, int64_t, int64x2_t) + +/* +** test_vaddv_f32: +** faddp s0, v0\.2s +** ret +*/ +TEST_UNARY (vaddv_f32, float32_t, float32x2_t) + +/* +** test_vaddvq_f32: +** faddp (v[0-9]+\.4s), v0\.4s, v0\.4s +** faddp v0\.4s, \1, \1 +** ret +*/ +TEST_UNARY (vaddvq_f32, float32_t, float32x4_t) + +/* +** test_vaddvq_f64: +** faddp d0, v0\.2d +** ret +*/ +TEST_UNARY (vaddvq_f64, float64_t, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vmaxnmv.c b/gcc/testsuite/gcc.target/aarch64/neon/vmaxnmv.c new file mode 100644 index 00000000000..47f54144fdb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vmaxnmv.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vmaxnmv_f16: +** fmaxnmv h0, v0\.4h +** ret +*/ +TEST_UNARY (vmaxnmv_f16, float16_t, float16x4_t) + +/* +** test_vmaxnmv_f32: +** fmaxnmp s0, v0\.2s +** ret +*/ +TEST_UNARY (vmaxnmv_f32, float32_t, float32x2_t) + +/* +** test_vmaxnmvq_f16: +** fmaxnmv h0, v0\.8h +** ret +*/ +TEST_UNARY (vmaxnmvq_f16, float16_t, float16x8_t) + +/* +** test_vmaxnmvq_f32: +** fmaxnmv s0, v0\.4s +** ret +*/ +TEST_UNARY (vmaxnmvq_f32, float32_t, float32x4_t) + +/* +** test_vmaxnmvq_f64: +** fmaxnmp d0, v0\.2d +** ret +*/ +TEST_UNARY (vmaxnmvq_f64, float64_t, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c b/gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c new file mode 100644 index 00000000000..a28da5fbb70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c @@ -0,0 +1,135 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vmaxv_u8: +** umaxv b([0-9]+), v0\.8b +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vmaxv_u8, uint8_t, uint8x8_t) + +/* +** test_vmaxv_s8: +** smaxv b([0-9]+), v0\.8b +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vmaxv_s8, int8_t, int8x8_t) + +/* +** test_vmaxv_u16: +** umaxv h([0-9]+), v0\.4h +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vmaxv_u16, uint16_t, uint16x4_t) + +/* +** test_vmaxv_s16: +** smaxv h([0-9]+), v0\.4h +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vmaxv_s16, int16_t, int16x4_t) + +/* +** test_vmaxv_u32: +** umaxp v([0-9]+)\.2s, v0\.2s, v0\.2s +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vmaxv_u32, uint32_t, uint32x2_t) + +/* +** test_vmaxv_s32: +** smaxp v([0-9]+)\.2s, v0\.2s, v0\.2s +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vmaxv_s32, int32_t, int32x2_t) + +/* +** test_vmaxvq_u8: +** umaxv b([0-9]+), v0\.16b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vmaxvq_u8, uint8_t, uint8x16_t) + +/* +** test_vmaxvq_s8: +** smaxv b([0-9]+), v0\.16b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vmaxvq_s8, int8_t, int8x16_t) + +/* +** test_vmaxvq_u16: +** umaxv h([0-9]+), v0\.8h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vmaxvq_u16, uint16_t, uint16x8_t) + +/* +** test_vmaxvq_s16: +** smaxv h([0-9]+), v0\.8h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vmaxvq_s16, int16_t, int16x8_t) + +/* +** test_vmaxvq_u32: +** umaxv (s[0-9]+), v0\.4s +** fmov w0, \1 +** ret +*/ +TEST_UNARY (vmaxvq_u32, uint32_t, uint32x4_t) + +/* +** test_vmaxvq_s32: +** smaxv (s[0-9]+), v0\.4s +** fmov w0, \1 +** ret +*/ +TEST_UNARY (vmaxvq_s32, int32_t, int32x4_t) + +/* +** test_vmaxv_f16: +** fmaxv h0, v0\.4h +** ret +*/ +TEST_UNARY (vmaxv_f16, float16_t, float16x4_t) + +/* +** test_vmaxv_f32: +** fmaxp s0, v0\.2s +** ret +*/ +TEST_UNARY (vmaxv_f32, float32_t, float32x2_t) + +/* +** test_vmaxvq_f16: +** fmaxv h0, v0\.8h +** ret +*/ +TEST_UNARY (vmaxvq_f16, float16_t, float16x8_t) + +/* +** test_vmaxvq_f32: +** fmaxv s0, v0\.4s +** ret +*/ +TEST_UNARY (vmaxvq_f32, float32_t, float32x4_t) + +/* +** test_vmaxvq_f64: +** fmaxp d0, v0\.2d +** ret +*/ +TEST_UNARY (vmaxvq_f64, float64_t, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vminnmv.c b/gcc/testsuite/gcc.target/aarch64/neon/vminnmv.c new file mode 100644 index 00000000000..04765f7d3bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vminnmv.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vminnmv_f16: +** fminnmv h0, v0\.4h +** ret +*/ +TEST_UNARY (vminnmv_f16, float16_t, float16x4_t) + +/* +** test_vminnmv_f32: +** fminnmp s0, v0\.2s +** ret +*/ +TEST_UNARY (vminnmv_f32, float32_t, float32x2_t) + +/* +** test_vminnmvq_f16: +** fminnmv h0, v0\.8h +** ret +*/ +TEST_UNARY (vminnmvq_f16, float16_t, float16x8_t) + +/* +** test_vminnmvq_f32: +** fminnmv s0, v0\.4s +** ret +*/ +TEST_UNARY (vminnmvq_f32, float32_t, float32x4_t) + +/* +** test_vminnmvq_f64: +** fminnmp d0, v0\.2d +** ret +*/ +TEST_UNARY (vminnmvq_f64, float64_t, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vminv.c b/gcc/testsuite/gcc.target/aarch64/neon/vminv.c new file mode 100644 index 00000000000..9b7657357fd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vminv.c @@ -0,0 +1,135 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vminv_u8: +** uminv b([0-9]+), v0\.8b +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vminv_u8, uint8_t, uint8x8_t) + +/* +** test_vminv_s8: +** sminv b([0-9]+), v0\.8b +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vminv_s8, int8_t, int8x8_t) + +/* +** test_vminv_u16: +** uminv h([0-9]+), v0\.4h +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vminv_u16, uint16_t, uint16x4_t) + +/* +** test_vminv_s16: +** sminv h([0-9]+), v0\.4h +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vminv_s16, int16_t, int16x4_t) + +/* +** test_vminv_u32: +** uminp v([0-9]+)\.2s, v0\.2s, v0\.2s +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vminv_u32, uint32_t, uint32x2_t) + +/* +** test_vminv_s32: +** sminp v([0-9]+)\.2s, v0\.2s, v0\.2s +** umov x0, v\1\.d\[0\] +** ret +*/ +TEST_UNARY (vminv_s32, int32_t, int32x2_t) + +/* +** test_vminvq_u8: +** uminv b([0-9]+), v0\.16b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vminvq_u8, uint8_t, uint8x16_t) + +/* +** test_vminvq_s8: +** sminv b([0-9]+), v0\.16b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_UNARY (vminvq_s8, int8_t, int8x16_t) + +/* +** test_vminvq_u16: +** uminv h([0-9]+), v0\.8h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vminvq_u16, uint16_t, uint16x8_t) + +/* +** test_vminvq_s16: +** sminv h([0-9]+), v0\.8h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_UNARY (vminvq_s16, int16_t, int16x8_t) + +/* +** test_vminvq_u32: +** uminv (s[0-9]+), v0\.4s +** fmov w0, \1 +** ret +*/ +TEST_UNARY (vminvq_u32, uint32_t, uint32x4_t) + +/* +** test_vminvq_s32: +** sminv (s[0-9]+), v0\.4s +** fmov w0, \1 +** ret +*/ +TEST_UNARY (vminvq_s32, int32_t, int32x4_t) + +/* +** test_vminv_f16: +** fminv h0, v0\.4h +** ret +*/ +TEST_UNARY (vminv_f16, float16_t, float16x4_t) + +/* +** test_vminv_f32: +** fminp s0, v0\.2s +** ret +*/ +TEST_UNARY (vminv_f32, float32_t, float32x2_t) + +/* +** test_vminvq_f16: +** fminv h0, v0\.8h +** ret +*/ +TEST_UNARY (vminvq_f16, float16_t, float16x8_t) + +/* +** test_vminvq_f32: +** fminv s0, v0\.4s +** ret +*/ +TEST_UNARY (vminvq_f32, float32_t, float32x4_t) + +/* +** test_vminvq_f64: +** fminp d0, v0\.2d +** ret +*/ +TEST_UNARY (vminvq_f64, float64_t, float64x2_t) From patchwork Wed Sep 2 08:38:25 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruv Chawla X-Patchwork-Id: 2296448 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=nGrqCxzM; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZblN07Ptz1xwg for ; Wed, 02 Sep 2026 18:40:16 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ED8ED4BA79B7 for ; Wed, 2 Sep 2026 08:40:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ED8ED4BA79B7 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=nGrqCxzM X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazlp170100005.outbound.protection.outlook.com [IPv6:2a01:111:f403:c111::5]) by sourceware.org (Postfix) with ESMTPS id AE5E34BA23E9 for ; Wed, 2 Sep 2026 08:39:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AE5E34BA23E9 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=nvidia.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AE5E34BA23E9 Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=2a01:111:f403:c111::5 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338361; cv=pass; b=yFDqNQQ+H4GGmCem9dPgOoysqn0YUsqJ3fOcnSn1EMfoUZGBZKgYhdgAc9SFQCbaHgJXtmCF0xEqpQ1v65gBWczHsHvtAd4hr1IYfW/LQN19GPmow5b053cHg1dAaLHqhZiw0ScXY4+yqq20T2GSgJvViZrAZ/A5NJa5wBC8ljQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338361; c=relaxed/simple; bh=ZX12URrdEbc210b/f4g/ZxaHAntSjWSKxZQ9nK28Szk=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=rdytwmxZNgY/BFDG6Esxx+5veCatKno9K+Kn5s/3yZd/qS0lvIEUQY1onenwaF4IDWoAv87bbtiBzzTl6chPXLUGSHHaKL/KjRolcVSSs5tbX5ZJo2Er1KFHLziCB1N8zOjYr4MzsRJWdBscIPhKYNYs6fZzogtvcU4lDbv8Ick= ARC-Authentication-Results: i=2; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=nGrqCxzM DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AE5E34BA23E9 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=buiBfiNKGT+Kcjy40DGqzWV5OoWwKCskwonG1Ti9yoc147jhZkWLiOGXIw8+JoJEIi3YqRHArhuP9rEdmZYbnDWPcepzZMlNsxp1/LCOvkXNoytHemw8Rvr4/vXKnPpY2a9RDovls8rWL2+V+nFmLyIwxZ6xMYwY6lIVSIAVEMlHNH5qlkivjhyw1pQLJvdJ/cwW0wPe7eTaWS4w9xNNNC//z/ygrmXSyx6QttAUIb443HqlGvHb7rMJQhSwxlfeTMfz09fBLDqeYx+7EzqoTX+rNtQK7QzJzb6IsR+nEKgPClzgno4YeyQgQBDXxi6k6qMpy8UENC/P86iwDt4ezw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jJ6z55yNAZDl1QqDhLArW0hwpk6Q4N/qg7jownYVzec=; b=GxUS/Ewj5J6SaNFbQCTLutTKmLzE5MwcnCMYif1PAMKvr6bzDokhRzs2d5xXpg/DUxpKNgaPh5fDQjG/2zFwZ4Zj7DINMdnZNSp6+EIsnMINQT8ZhAHxM41Bf5/SEe0z/+hljnWzUJlDIFRiG1zsRQO2a2vAARVcwnIaDkXSOeNoAemkcYCLTpnY94LZD8GSu6fUyod6BLQSN8h0d2DUt7VxEQs1sUzqZ6wkiPMr3DPSXLE1yjWr+NvrYVOXLyjrYfejdyDJETHIwjqhBoE6LphwIpyvyApu8pduga8T8l1Tn+OCXBpCKH3jQ7F/fg2UMdmanZRGEAyXF1T10YxbQQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jJ6z55yNAZDl1QqDhLArW0hwpk6Q4N/qg7jownYVzec=; b=nGrqCxzMLKxSylMNbU1PHVMqL9+GBIh3txm1p2xt3X6+3wJWi6qAK9qBfKbeHWGyxYoK2CoiorSbzklKqBx2IS+A5nH88NI2IGag80RHqAssUxbANjtSXBnJV9VV/kklLQRKbPE6U67duq9D9BOvUF4wplq/a93MKtkg3LI3syVPhzWWYS6CUJMbadOQJNLi04CI9Ar2xaGwGv469hppBYmtqqYvEvMaT+xuNxJgJpMgqhIUT0Ksu77g/zQvPVZOmN1w3fRBWQwJjG9keoAU8Q64xoyUaPyQzHQwePIsyp01kOvw+OOdrcXj8vPTNiTlkJ7EV04qg3A6AHQqX9RR4w== Received: from DM6PR08CA0057.namprd08.prod.outlook.com (2603:10b6:5:1e0::31) by DS4PR12MB9683.namprd12.prod.outlook.com (2603:10b6:8:280::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.13; Wed, 2 Sep 2026 08:39:15 +0000 Received: from DS3PEPF000099E2.namprd04.prod.outlook.com (2603:10b6:5:1e0:cafe::5c) by DM6PR08CA0057.outlook.office365.com (2603:10b6:5:1e0::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.11 via Frontend Transport; Wed, 2 Sep 2026 08:39:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Wed, 2 Sep 2026 08:39:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:38:59 -0700 Received: from MVD4TP25H0.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:38:57 -0700 From: To: CC: , Subject: [PATCH 3/6] aarch64: Port NEON halving-add intrinsics to pragma-based framework Date: Wed, 2 Sep 2026 14:08:25 +0530 Message-ID: <20260902083828.45767-4-dhruvc@nvidia.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260902083828.45767-1-dhruvc@nvidia.com> References: <20260902083828.45767-1-dhruvc@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|DS4PR12MB9683:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d26a0ee-3d74-4fac-f04a-08df08cdabcc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|376014|23010399003|1800799024|82310400026|13003099007|10067099003|6133799003|56012099006|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: cqdTWPt9La17mPN58csxoWtr38VQp01bPcWtnhq7wSx7YC0q7GDZtMUjqP588U9v4RmUwil6l1ExrLwkHg2VAf6078HVCxoAcj6GmXTg++OZzB0rSy/3s3mErRYa1esIQJCa86sGyHSOoz8V82ccTpf/oak2N+Aq08OjpyYBXOddUsUrWuqiFvMRy5DcTQQihPSh/S82DhThtmu+yNnIkbbvFHx9zEY4IyDhb+MB3zMPas8Iu4VRjImOdm9f2RDbi+Mu8VsYt5jfm7dbVDQrUoN90srMe7/ESmjgzZB+x6vzca4sgt7Ihu9HH/4K6A4LfzBMu3SsNv9hPslGs7rLrfsLdtms/6WBE6j0kYvqpeJTtncNL0GMSEcNuGHlULysW1NACMnk1zHZS9mAPXmK66zePvepKx8RMIqSZ3Q6Io9QPPrAcvWyfRvaSRwOoVPHT1TRdG+zHisnFOwExpKVMbhRD2lI95D+PcE6Ry/fWGVt0buiZZKYF6xADzD/da1L94Pir5IuR36ezx00DR/MQh2akZ+pWUQSRrPp85a8q3rBcEAZYvkNzhH5WXeD3h/8beyIxZLVkl5CkDilN7LbibPUJ97BruaEhVCZjyXQm/7+AviPfQdZ9YZU/uf0hJjnZw0jlukJCvSxMqTWk1Y7bOXLy7zg3HG5HTuW7UZ4uuIg4tG3ot4/L/ZxEOFDFhaS39EAoQR9y2D/fiVDwkdbmA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(376014)(23010399003)(1800799024)(82310400026)(13003099007)(10067099003)(6133799003)(56012099006)(11063799006)(22082099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: E3WtCgS9I9BaUkClW+BvUr5Ri7PeAU9O3mqT2LQ/2EbaIaxV6yOjP+3cBTz8nv8reraRzBKmtyd25tlngTHy5UmINdCGh58Czufvq+EY2c6DxE5/46UAnXfXMh+YcHnT65XCN1I30RbGN4H31XXXEOwAXdPdzwtLPkjQcttDEf65rMT1CGOiV0ijnX56lYQXLr2mZZdHQU71V9c48r69AxuowNlqUDYiUB0Hn7XKT2u70Sb9QRRcQP+o1fH9h0fTAXBZj4mjufP6oL8Vz504MrSDtrt7vIztQhF0Kn5mdB11ESxWvPsTjW1JmMzTbmzq2phjprbAiOsbnwes2hwoHgh3zEtuYYZp85j2Wed/3rqqitA+50ZC+bBlqaWii3a+18NzURCPIN81jXdJA5cpZzT/Oa788rQvMNBASiUoQIraHukoMYlDC/Hr+tq4j4Zz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 08:39:15.1942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d26a0ee-3d74-4fac-f04a-08df08cdabcc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9683 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Dhruv Chawla Port the following intrinsics to the pragma-based framework: * vhadd * vrhadd The arm_neon_{1,2,3}.c test cases now expect the ACLE streaming-mode diagnostic instead of an inlining failure. The inlining_10.c and inlining_11.c test cases are updated to use the vqtbl intrinsic instead of vhadd as the latter is no longer implemented as an always_inline function in arm_neon.h. Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla gcc/ChangeLog: * config/aarch64/aarch64-neon-builtins-base.cc (vhadd, vhaddq, vrhadd, vrhaddq): New function bases. * config/aarch64/aarch64-neon-builtins-base.def (vhadd, vhaddq, vrhadd, vrhaddq): New function groups. * config/aarch64/arm_neon.h (vhadd_s8, vhadd_s16, vhadd_s32, vhadd_u8, vhadd_u16, vhadd_u32, vhaddq_s8, vhaddq_s16, vhaddq_s32, vhaddq_u8, vhaddq_u16, vhaddq_u32, vrhadd_s8, vrhadd_s16, vrhadd_s32, vrhadd_u8, vrhadd_u16, vrhadd_u32, vrhaddq_s8, vrhaddq_s16, vrhaddq_s32, vrhaddq_u8, vrhaddq_u16, vrhaddq_u32): Delete functions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sme/arm_neon_1.c: Update the expected dg-error message. * gcc.target/aarch64/sme/arm_neon_2.c: Likewise. * gcc.target/aarch64/sme/arm_neon_3.c: Likewise. * gcc.target/aarch64/sme/inlining_10.c: Replace vhadd with vqtbl as vhadd is no longer always_inline. * gcc.target/aarch64/sme/inlining_11.c: Likewise. * gcc.target/aarch64/neon/vhadd.c: New test. * gcc.target/aarch64/neon/vrhadd.c: Likewise. --- .../aarch64/aarch64-neon-builtins-base.cc | 6 + .../aarch64/aarch64-neon-builtins-base.def | 8 + gcc/config/aarch64/arm_neon.h | 168 ------------------ gcc/testsuite/gcc.target/aarch64/neon/vhadd.c | 88 +++++++++ .../gcc.target/aarch64/neon/vrhadd.c | 88 +++++++++ .../gcc.target/aarch64/sme/arm_neon_1.c | 4 +- .../gcc.target/aarch64/sme/arm_neon_2.c | 4 +- .../gcc.target/aarch64/sme/arm_neon_3.c | 4 +- .../gcc.target/aarch64/sme/inlining_10.c | 6 +- .../gcc.target/aarch64/sme/inlining_11.c | 6 +- 10 files changed, 199 insertions(+), 183 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vhadd.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrhadd.c diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index ca122d65a51..39f8892e35f 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -779,6 +779,12 @@ NEON_FUNCTION (vmaxnmvq, gimple_ifn, (IFN_REDUC_FMAX)) NEON_FUNCTION (vminnmv, gimple_ifn, (IFN_REDUC_FMIN)) NEON_FUNCTION (vminnmvq, gimple_ifn, (IFN_REDUC_FMIN)) +// Halving add +NEON_FUNCTION (vhadd, gimple_ifn, (IFN_AVG_FLOOR)) +NEON_FUNCTION (vhaddq, gimple_ifn, (IFN_AVG_FLOOR)) +NEON_FUNCTION (vrhadd, gimple_ifn, (IFN_AVG_CEIL)) +NEON_FUNCTION (vrhaddq, gimple_ifn, (IFN_AVG_CEIL)) + // Bitwise operations NEON_FUNCTION (vand, gimple_expr, (BIT_AND_EXPR)) NEON_FUNCTION (vandq, gimple_expr, (BIT_AND_EXPR)) diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index b3c0fc42298..ddb12c497bb 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -114,6 +114,14 @@ DEF_NEON_FUNCTION (vminnmv, h_float, ("s0,D0")) DEF_NEON_FUNCTION (vminnmvq, h_float, ("s0,Q0")) #undef REQUIRED_EXTENSIONS +// Halving add +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) +DEF_NEON_FUNCTION (vhadd, bhs_integer, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vhaddq, bhs_integer, ("Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vrhadd, bhs_integer, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vrhaddq, bhs_integer, ("Q0,Q0,Q0")) +#undef REQUIRED_EXTENSIONS + // Bitwise operations #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) DEF_NEON_FUNCTION (vand, all_integer, ("D0,D0,D0")) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 1fccc7e3237..d23b59504f4 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -273,174 +273,6 @@ vaddw_high_u32 (uint64x2_t __a, uint32x4_t __b) return __builtin_aarch64_uaddw2v4si_uuu (__a, __b); } -__extension__ extern __inline int8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhadd_s8 (int8x8_t __a, int8x8_t __b) -{ - return __builtin_aarch64_shaddv8qi (__a, __b); -} - -__extension__ extern __inline int16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhadd_s16 (int16x4_t __a, int16x4_t __b) -{ - return __builtin_aarch64_shaddv4hi (__a, __b); -} - -__extension__ extern __inline int32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhadd_s32 (int32x2_t __a, int32x2_t __b) -{ - return __builtin_aarch64_shaddv2si (__a, __b); -} - -__extension__ extern __inline uint8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhadd_u8 (uint8x8_t __a, uint8x8_t __b) -{ - return __builtin_aarch64_uhaddv8qi_uuu (__a, __b); -} - -__extension__ extern __inline uint16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhadd_u16 (uint16x4_t __a, uint16x4_t __b) -{ - return __builtin_aarch64_uhaddv4hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhadd_u32 (uint32x2_t __a, uint32x2_t __b) -{ - return __builtin_aarch64_uhaddv2si_uuu (__a, __b); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhaddq_s8 (int8x16_t __a, int8x16_t __b) -{ - return __builtin_aarch64_shaddv16qi (__a, __b); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhaddq_s16 (int16x8_t __a, int16x8_t __b) -{ - return __builtin_aarch64_shaddv8hi (__a, __b); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhaddq_s32 (int32x4_t __a, int32x4_t __b) -{ - return __builtin_aarch64_shaddv4si (__a, __b); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhaddq_u8 (uint8x16_t __a, uint8x16_t __b) -{ - return __builtin_aarch64_uhaddv16qi_uuu (__a, __b); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhaddq_u16 (uint16x8_t __a, uint16x8_t __b) -{ - return __builtin_aarch64_uhaddv8hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vhaddq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return __builtin_aarch64_uhaddv4si_uuu (__a, __b); -} - -__extension__ extern __inline int8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhadd_s8 (int8x8_t __a, int8x8_t __b) -{ - return __builtin_aarch64_srhaddv8qi (__a, __b); -} - -__extension__ extern __inline int16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhadd_s16 (int16x4_t __a, int16x4_t __b) -{ - return __builtin_aarch64_srhaddv4hi (__a, __b); -} - -__extension__ extern __inline int32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhadd_s32 (int32x2_t __a, int32x2_t __b) -{ - return __builtin_aarch64_srhaddv2si (__a, __b); -} - -__extension__ extern __inline uint8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhadd_u8 (uint8x8_t __a, uint8x8_t __b) -{ - return __builtin_aarch64_urhaddv8qi_uuu (__a, __b); -} - -__extension__ extern __inline uint16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhadd_u16 (uint16x4_t __a, uint16x4_t __b) -{ - return __builtin_aarch64_urhaddv4hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhadd_u32 (uint32x2_t __a, uint32x2_t __b) -{ - return __builtin_aarch64_urhaddv2si_uuu (__a, __b); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhaddq_s8 (int8x16_t __a, int8x16_t __b) -{ - return __builtin_aarch64_srhaddv16qi (__a, __b); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhaddq_s16 (int16x8_t __a, int16x8_t __b) -{ - return __builtin_aarch64_srhaddv8hi (__a, __b); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhaddq_s32 (int32x4_t __a, int32x4_t __b) -{ - return __builtin_aarch64_srhaddv4si (__a, __b); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b) -{ - return __builtin_aarch64_urhaddv16qi_uuu (__a, __b); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b) -{ - return __builtin_aarch64_urhaddv8hi_uuu (__a, __b); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return __builtin_aarch64_urhaddv4si_uuu (__a, __b); -} - __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddhn_s16 (int16x8_t __a, int16x8_t __b) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vhadd.c b/gcc/testsuite/gcc.target/aarch64/neon/vhadd.c new file mode 100644 index 00000000000..8411f6a4e30 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vhadd.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vhadd_u8: +** uhadd v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vhadd_u8, uint8x8_t) + +/* +** test_vhadd_s8: +** shadd v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vhadd_s8, int8x8_t) + +/* +** test_vhadd_u16: +** uhadd v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vhadd_u16, uint16x4_t) + +/* +** test_vhadd_s16: +** shadd v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vhadd_s16, int16x4_t) + +/* +** test_vhadd_u32: +** uhadd v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vhadd_u32, uint32x2_t) + +/* +** test_vhadd_s32: +** shadd v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vhadd_s32, int32x2_t) + +/* +** test_vhaddq_u8: +** uhadd v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vhaddq_u8, uint8x16_t) + +/* +** test_vhaddq_s8: +** shadd v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vhaddq_s8, int8x16_t) + +/* +** test_vhaddq_u16: +** uhadd v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vhaddq_u16, uint16x8_t) + +/* +** test_vhaddq_s16: +** shadd v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vhaddq_s16, int16x8_t) + +/* +** test_vhaddq_u32: +** uhadd v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vhaddq_u32, uint32x4_t) + +/* +** test_vhaddq_s32: +** shadd v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vhaddq_s32, int32x4_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrhadd.c b/gcc/testsuite/gcc.target/aarch64/neon/vrhadd.c new file mode 100644 index 00000000000..46e3cb864c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrhadd.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrhadd_u8: +** urhadd v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vrhadd_u8, uint8x8_t) + +/* +** test_vrhadd_s8: +** srhadd v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vrhadd_s8, int8x8_t) + +/* +** test_vrhadd_u16: +** urhadd v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vrhadd_u16, uint16x4_t) + +/* +** test_vrhadd_s16: +** srhadd v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vrhadd_s16, int16x4_t) + +/* +** test_vrhadd_u32: +** urhadd v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vrhadd_u32, uint32x2_t) + +/* +** test_vrhadd_s32: +** srhadd v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vrhadd_s32, int32x2_t) + +/* +** test_vrhaddq_u8: +** urhadd v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vrhaddq_u8, uint8x16_t) + +/* +** test_vrhaddq_s8: +** srhadd v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vrhaddq_s8, int8x16_t) + +/* +** test_vrhaddq_u16: +** urhadd v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vrhaddq_u16, uint16x8_t) + +/* +** test_vrhaddq_s16: +** srhadd v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vrhaddq_s16, int16x8_t) + +/* +** test_vrhaddq_u32: +** urhadd v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vrhaddq_u32, uint32x4_t) + +/* +** test_vrhaddq_s32: +** srhadd v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vrhaddq_s32, int32x4_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_1.c b/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_1.c index 5b5346cf435..9f50bb92722 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_1.c @@ -4,10 +4,8 @@ #pragma GCC target "+nosme" -// { dg-error {inlining failed.*'vhaddq_s32'} "" { target *-*-* } 0 } - int32x4_t foo (int32x4_t x, int32x4_t y) [[arm::streaming_compatible]] { - return vhaddq_s32 (x, y); + return vhaddq_s32 (x, y); // { dg-error {ACLE function 'vhaddq_s32' cannot be called when SME streaming mode is enabled} } } diff --git a/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_2.c b/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_2.c index 2092c4471f0..9a4fff5e98c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_2.c @@ -2,10 +2,8 @@ #include -// { dg-error {inlining failed.*'vhaddq_s32'} "" { target *-*-* } 0 } - int32x4_t foo (int32x4_t x, int32x4_t y) [[arm::streaming_compatible]] { - return vhaddq_s32 (x, y); + return vhaddq_s32 (x, y); // { dg-error {ACLE function 'vhaddq_s32' cannot be called when SME streaming mode is enabled} } } diff --git a/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_3.c b/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_3.c index 36794e5b0df..19f633e1849 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/arm_neon_3.c @@ -2,10 +2,8 @@ #include -// { dg-error {inlining failed.*'vhaddq_s32'} "" { target *-*-* } 0 } - int32x4_t foo (int32x4_t x, int32x4_t y) [[arm::streaming]] { - return vhaddq_s32 (x, y); + return vhaddq_s32 (x, y); // { dg-error {ACLE function 'vhaddq_s32' cannot be called when SME streaming mode is enabled} } } diff --git a/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c b/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c index 131fb7a6637..3e9af18265f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c @@ -18,9 +18,9 @@ call_vadd () } inline void __attribute__((always_inline)) -call_vhadd () // { dg-error "inlining failed" } +call_vqtbl () // { dg-error "inlining failed" } { - neon[0] = vhaddq_u8 (neon[1], neon[2]); + neon[0] = vqtbl1q_u8 (neon[1], neon[2]); } inline void __attribute__((always_inline)) @@ -51,7 +51,7 @@ void sc_caller () [[arm::inout("za"), arm::streaming_compatible]] { call_vadd (); - call_vhadd (); + call_vqtbl (); call_svadd (); call_svld1_gather (); call_svzero (); diff --git a/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c b/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c index d500a62743d..e60b357dfa2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c @@ -18,9 +18,9 @@ call_vadd () } inline void __attribute__((always_inline)) -call_vhadd () // { dg-error "inlining failed" } +call_vqtbl () // { dg-error "inlining failed" } { - neon[0] = vhaddq_u8 (neon[1], neon[2]); + neon[0] = vqtbl1q_u8 (neon[1], neon[2]); } inline void __attribute__((always_inline)) @@ -51,7 +51,7 @@ void sc_caller () [[arm::inout("za"), arm::streaming]] { call_vadd (); - call_vhadd (); + call_vqtbl (); call_svadd (); call_svld1_gather (); call_svzero (); From patchwork Wed Sep 2 08:38:26 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruv Chawla X-Patchwork-Id: 2296447 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=POZtZRSs; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZblK73Fzz1xwg for ; Wed, 02 Sep 2026 18:40:13 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C594D4BA79A5 for ; Wed, 2 Sep 2026 08:40:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C594D4BA79A5 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=POZtZRSs X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazlp170120007.outbound.protection.outlook.com [IPv6:2a01:111:f403:c101::7]) by sourceware.org (Postfix) with ESMTPS id A6B954BA79A6 for ; Wed, 2 Sep 2026 08:39:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A6B954BA79A6 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=nvidia.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A6B954BA79A6 Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=2a01:111:f403:c101::7 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338362; cv=pass; b=URmaJ4o9lEc9XmCMIEDW27kBdL7CMCiN9quPjpbRuaTeNUlaiHoMLXNRlw3D6CTbwFNbjhq6XnI0BPgbn8wymcqNg4SnUToN9csVTwYX5s8+nXIjmkH4c3orBlh566vYhRGrh6wkjHI3gkedepkM1+sDLJ2uNdj0UqzVnJ0N20c= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338362; c=relaxed/simple; bh=CoRp+LyUsA1omZv+uziC31PnK3nietGzEgA7aVr86xM=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=ozWi2ol769j8GXJYw8aVWAPWV2mP/U0jX2+gV35m0FiDHmOT3MrVO1eCGz5hNW7LDIlCgxTfzDtTtmdlpqjTd2XS7iW6NsTw+M6e/pnD3bDKH0ZPPQ5yb6PjgNMLO2NJlbD47FBlvnGTvYfirU9s6ScS9DUE7BuINxntflrmZms= ARC-Authentication-Results: i=2; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=POZtZRSs DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A6B954BA79A6 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oUxdUjxUqCfgXaBprCsVzQgEVQE8xv4m3dzRM3EOPOKqU3uHx6aNmawtNFAq+rf9cIsI1tw99cPqWVh6Mcw72ntsH7Bnx4IFtBwNCUtqhFNDpjehYM9J7gGDwOf/wNWXBcD2pcCs05L4QXz+/YS7Pww7t/hbXyiBEdOo9qtSXqTUKf5YaYDrmsyuBJP67O46kKSH+ijiqiMZ4uklPhtLs5YNBjbzkmncoKBMUgfAi4t9gUTkaHA+hQgNU0lV+VyTn5aPIJIRZdHKjQKO7Pxp7POnEFsDQpwRtjfIF5wwQ4wzX6DTWVDajUqyEaZUeSyq9YWTFq6Qt6KTgUv4m/uM3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jJUeKKs0Iyd0m7DRY+Ze75SUai9d39b/nQ7xXvlajWQ=; b=rt95lk127MDJRe8iimyOGvJJntuC2J7lUmRgz3YUXZEmhWTIpri7VXBWFXyaYGFkyxm6U7MUPHS/bp/ta5wrSRPO7uudxF7aRF6sdQA0LCkOqtBWhdfi+8+54816ddAETkxLF0p6FcKBl+bl1Z8P1zV+OlnTmCWXhdcjxJddtKUkfHFSx+NL3FOZBLKlUI6g/sZ4641XaHsb6pTeJFUvEM8T3OLN08n6SUOzCSE7PRtm8lEZohfnCVmS9bdw47bf0Mg2fqhH4vYC/X3fjXVo/ifg+DMs09h+SbsOxWJR/5JSKAD4termTAFQf4tU0Cgk8zIJFWZTL3I8q4JZ0SgOwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jJUeKKs0Iyd0m7DRY+Ze75SUai9d39b/nQ7xXvlajWQ=; b=POZtZRSshgHBoPUibeLZe2TxTiysnquvJ8iMuHueqiVF6Gu3beJhOjtUnnmh51fMjj4NFAsVsEpK9rr6T4/K0dDVMOv8RNSj03m8PbXzFZI7cO5riaPVPQ4BbwNrUhFGQuz8SDRD7OLZ2e1vc5aljN24xYWVGYEYCfZPX10sOm9DQi5oS0CpWYcdT9MeGLSyalHsJsSxe9SZ4bWR5O27CesYRv324u9qH++y89G0tTVKoUL4Z32EUDdfxxov3qivAecFk23cnJSZI9xNO1GJfVwQxmmvP1u+LIxwaWAaarraSI0QQLOaiStazCr7C1OIjSZveHbwXhbl5HFWC64zDA== Received: from SA1PR03CA0011.namprd03.prod.outlook.com (2603:10b6:806:2d3::23) by CH2PR12MB9496.namprd12.prod.outlook.com (2603:10b6:610:27e::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.11; Wed, 2 Sep 2026 08:39:17 +0000 Received: from SN1PEPF00036F3E.namprd05.prod.outlook.com (2603:10b6:806:2d3:cafe::92) by SA1PR03CA0011.outlook.office365.com (2603:10b6:806:2d3::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.11 via Frontend Transport; Wed, 2 Sep 2026 08:39:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF00036F3E.mail.protection.outlook.com (10.167.248.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Wed, 2 Sep 2026 08:39:16 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:39:01 -0700 Received: from MVD4TP25H0.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:38:59 -0700 From: To: CC: , Subject: [PATCH 4/6] aarch64: Port NEON square-root intrinsics to pragma-based framework Date: Wed, 2 Sep 2026 14:08:26 +0530 Message-ID: <20260902083828.45767-5-dhruvc@nvidia.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260902083828.45767-1-dhruvc@nvidia.com> References: <20260902083828.45767-1-dhruvc@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3E:EE_|CH2PR12MB9496:EE_ X-MS-Office365-Filtering-Correlation-Id: 4137819f-2a3d-4fb2-6ae4-08df08cdaca4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|376014|23010399003|82310400026|13003099007|3023799007|10067099003|56012099006|6133799003|18002099003|11063799006|22082099003; X-Microsoft-Antispam-Message-Info: ePfO5GiS2GT/W+LnMMBVjhzy+pOV4Y/weURf9Iz/Q7strtoZy4mUzXkO2HCExLocB84nd5HPnbuFKdhRpnjetf64h1hBEJTguBfNTy46neDMd/j8FuLfRYa3dPSwyRcFi4/BHSewdQXvr0jR4yZYHAsDnBDR5buui0KL9ycbfBRb1xZca5sv67/e1/Fn/ttyEQ0jLwU7PvHS3tK0jLkLqaNVZV2L85qZEvNmS7RJ0xg1EpoEnzYy1Vui8ix9xgmULNmwv1fpZIy2aCybSCnHkSNBdpkZ6gte99ohCditv6Z9jdaICjyVe2av5Tv4taxxhJ3R9YYrfZIV7IqC4GyiTMyH/9AuSt1rOryzD19doy8M3fsxh5nW71NZEHuMaJQoxg9775OL3+3AsYMUgbmi0kRjWNoNLmjuwUUXHJinLEyzkHOZavY/fo3ZDM973iPJx/jwUskGop8NrK8yCecKN/RTbKEsXuKSW7ZJRF72cZj8gwp1u+oAcRLGDX4JtaGxT3PA1+0TnlsaU3qo7b3worLkqXQpEvKgBKXtz/TY8z+PikoxEaw0n+l5Fw4bLf9pnxlmCY5hO4UeTWX/jj6/IO19oVH/OM42hKhRifXSFfWachvQrHhkONAhKEvubPib5M0G+I5UezMu9T+S7lwvllcWXrWH73FLCnN23e3DDor/v+A0SRcjp92V3kpSjzjA1Q6F8/dbY5/fNl3XHkVrTw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(1800799024)(376014)(23010399003)(82310400026)(13003099007)(3023799007)(10067099003)(56012099006)(6133799003)(18002099003)(11063799006)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uTKiGYIWE49eXb1I+7TDhczLGbSvHc41w+XXeDO0oJHtYJb/ImnLtFxYG9NcaNK4YQHhKcNmRsAQjFYUayScpa9wDVOacT1uKhUn6UtIQ63iF0oaOtBbVXtZFP/hs6OmAPraL9l791PC0yNAiP0H7Fr8VmyMAbD78o/GsgSPRlZIIE6lYZDWrmXGR+gytLrYAjqlGnMN9TZ+fggsdA40zcRDu8eoydl+cyVjDQnoGtQ5vdHYOygf5oiKlPGLAHb8vulUvGrsCh8WvkqmetEa2R5dk2Fcyi+pcaNnGcQkn+SUPnd+3uz3RSKb5auhwarGeEz4kIcalatQyfE7wdseRG/QTcguV2vQJEphjSNnk01DnWsjCJopcjhdaAtZWfb5pi7nwOzQDQWi2KOUYgqynf6J1rEThw5aN9juvaVhW99/J2dyC44wuSC6I21TOdLw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 08:39:16.1666 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4137819f-2a3d-4fb2-6ae4-08df08cdaca4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9496 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Dhruv Chawla Port the vsqrt set of intrinsics to the pragma-based framework. The vsqrt_f64 intrinsic is not ported here as it cannot be directly lowered from an IFN through an existing instruction pattern. This is because the pattern does not iterate through the mode (V1DF) required to lower it (it uses the VHSDF iterator). Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla gcc/ChangeLog: * config/aarch64/aarch64-neon-builtins-base.cc (vsqrt, vsqrtq): New function bases. * config/aarch64/aarch64-neon-builtins-base.def (vsqrt, vsqrtq): New function groups. * config/aarch64/arm_neon.h (vsqrt_f32, vsqrtq_f32, vsqrtq_f64, vsqrt_f16, vsqrtq_f16): Delete functions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/neon/vsqrt.c: New test. --- .../aarch64/aarch64-neon-builtins-base.cc | 4 ++ .../aarch64/aarch64-neon-builtins-base.def | 12 +++++ gcc/config/aarch64/arm_neon.h | 34 -------------- gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c | 46 +++++++++++++++++++ 4 files changed, 62 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index 39f8892e35f..ca4ace4a020 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -785,6 +785,10 @@ NEON_FUNCTION (vhaddq, gimple_ifn, (IFN_AVG_FLOOR)) NEON_FUNCTION (vrhadd, gimple_ifn, (IFN_AVG_CEIL)) NEON_FUNCTION (vrhaddq, gimple_ifn, (IFN_AVG_CEIL)) +// Square root +NEON_FUNCTION (vsqrt, gimple_ifn, (IFN_SQRT)) +NEON_FUNCTION (vsqrtq, gimple_ifn, (IFN_SQRT)) + // Bitwise operations NEON_FUNCTION (vand, gimple_expr, (BIT_AND_EXPR)) NEON_FUNCTION (vandq, gimple_expr, (BIT_AND_EXPR)) diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index ddb12c497bb..98efa204e4a 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -122,6 +122,18 @@ DEF_NEON_FUNCTION (vrhadd, bhs_integer, ("D0,D0,D0")) DEF_NEON_FUNCTION (vrhaddq, bhs_integer, ("Q0,Q0,Q0")) #undef REQUIRED_EXTENSIONS +// Square root +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) +DEF_NEON_FUNCTION (vsqrt, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vsqrtq, sd_float, ("Q0,Q0")) +#undef REQUIRED_EXTENSIONS + +// Square root (FP16) +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD | AARCH64_FL_F16) +DEF_NEON_FUNCTION (vsqrt, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vsqrtq, h_float, ("Q0,Q0")) +#undef REQUIRED_EXTENSIONS + // Bitwise operations #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) DEF_NEON_FUNCTION (vand, all_integer, ("D0,D0,D0")) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index d23b59504f4..68f92f76de0 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -16711,19 +16711,6 @@ vsqaddd_u64 (uint64_t __a, int64_t __b) } /* vsqrt */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsqrt_f32 (float32x2_t __a) -{ - return __builtin_aarch64_sqrtv2sf (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsqrtq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_sqrtv4sf (__a); -} __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -16732,13 +16719,6 @@ vsqrt_f64 (float64x1_t __a) return (float64x1_t) { __builtin_aarch64_sqrtdf (__a[0]) }; } -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsqrtq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_sqrtv2df (__a); -} - /* vsra */ __extension__ extern __inline int8x8_t @@ -19318,20 +19298,6 @@ vrsqrteq_f16 (float16x8_t __a) return __builtin_aarch64_rsqrtev8hf (__a); } -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsqrt_f16 (float16x4_t __a) -{ - return __builtin_aarch64_sqrtv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsqrtq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_sqrtv8hf (__a); -} - /* ARMv8.2-A FP16 two operands vector intrinsics. */ __extension__ extern __inline float16x4_t diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c b/gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c new file mode 100644 index 00000000000..3b623f3ae56 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vsqrt_f16: +** fsqrt v0.4h, v0.4h +** ret +*/ +TEST_UNIFORM_UNARY (vsqrt_f16, float16x4_t) + +/* +** test_vsqrt_f32: +** fsqrt v0.2s, v0.2s +** ret +*/ +TEST_UNIFORM_UNARY (vsqrt_f32, float32x2_t) + +/* +** test_vsqrt_f64: +** fsqrt d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vsqrt_f64, float64x1_t) + +/* +** test_vsqrtq_f16: +** fsqrt v0.8h, v0.8h +** ret +*/ +TEST_UNIFORM_UNARY (vsqrtq_f16, float16x8_t) + +/* +** test_vsqrtq_f32: +** fsqrt v0.4s, v0.4s +** ret +*/ +TEST_UNIFORM_UNARY (vsqrtq_f32, float32x4_t) + +/* +** test_vsqrtq_f64: +** fsqrt v0.2d, v0.2d +** ret +*/ +TEST_UNIFORM_UNARY (vsqrtq_f64, float64x2_t) From patchwork Wed Sep 2 08:38:27 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruv Chawla X-Patchwork-Id: 2296451 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=tWEZ8P7h; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=38.145.34.32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZbpv0g05z1xwg for ; Wed, 02 Sep 2026 18:43:19 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 966834BA79A9 for ; Wed, 2 Sep 2026 08:43:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 966834BA79A9 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=tWEZ8P7h X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazlp170120002.outbound.protection.outlook.com [IPv6:2a01:111:f403:c001::2]) by sourceware.org (Postfix) with ESMTPS id EA9144BA5435 for ; Wed, 2 Sep 2026 08:39:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EA9144BA5435 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=nvidia.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EA9144BA5435 Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=2a01:111:f403:c001::2 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338374; cv=pass; b=PxryWcu4zrrjMhURMfZEQYa30PETbByrituivpi9XUNMvJlXQR/SiWcTcMSX4ZyxFLwEGNL+sfw/rqvcATkfaMdg43rhVbULg0b48pOpVIZzxYaiLOcVV5nJWQ0mgdt+F23pfwRxuFMWoup+CBOdkKjBAVHK4q0qOj9y3+nybwM= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338374; c=relaxed/simple; bh=hkjXjpMSlTj6+UD+Y8b9oFtMEtnhNC+FVXDRXIQWPLA=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=xoOmW2IwC3ZNdgA6//KXLk0bCKWg5VbVBxaVhn963m+52I1Uvnx+GDtjRCqaDLQQ6NT/NElIIQB0kFRNk6eThTVskdaPy5huUDZmLLg2NS6osG2NI/T4l8mq4725Vc9MoHSMR8HuPX+spOUnhp/xZdVO9ziOKGXDxRBXZeEif1A= ARC-Authentication-Results: i=2; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=tWEZ8P7h DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EA9144BA5435 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PC+2F2gt05ZvCfxMZcHs/QHfRK8qrzrux9qtw2JrYpLKyFJyFHvwXv4ZARf3YeHRYMadXLL/yppng79DPq90V8L92hLCtQ5boL9h2fxcMf2w6RKru6JGFbpZbvpBVQCOdoSS/keKCVc0eyXNr+3lxlGN2vjAi1oPutstfLr+zFRZ4kAhRTOtBY3siDrZV6lSIKFYCISOlZX3vBcQ48fu3ULNINDMhGUFRwZdJ8KSrkLk+48JSehLfLWz/4/jUt45JsCvKAVfEh6R9ByV0/IzjZTXjjP3HeQ39Eq+7vM2p+KWMCRsnrOIx2oKGfPzPK/Ab3ltrwLQbMHIGCgA941E/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ejgneFJyMHINm7s/lgIe7jHoTjnECIpCquK1K01/qNQ=; b=bHAxPayXGuaYXZAEX0WAoiQZyDCHlGC4IXpnn/whlZSuDuKO0mdngS52Bt9rPdSB9MQUOFC+26a3XPq8/cNb+EsaVVmlrAKNrV9aYSNaJq6LUc7VmUVIA7ZUPG09Yu+OuQp2+grSKuRsDhEd6FK/BNIhBVOoxtvs+W2wLgCkdQUd909yEdAt2cdM9TXvp/EOKD3wwdQhPlspGagUjE14u9V2hBQdz8x9h5ERLl6WuYwFSoGGB+ynBhiRrBzSONAegJ/1h1tnFCi0uspucJq8DkgDgLMAJqBuVXAF4dmZeCgzh9pomtqXJjrRCbGBCqcZh81N0PDu6+dvIml6Okgc+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ejgneFJyMHINm7s/lgIe7jHoTjnECIpCquK1K01/qNQ=; b=tWEZ8P7hp7DZEMOP+wBDmuxN6q2m+uLe0lxn9QCb9aQpetGX6FcvidqVwh1PnTwHMllZqoxPhOOcmENPYcR/fUZLQkgzIobutTWc8C9FL+oRCZzzvvVxB27EsoHWi03+n6/URF9Yei238YgUiLjFDejDLP/9L/SvJ+OLkbq+T2QWr3I6g5DWKyg6VFzXL2p3Hq7cTMw9HeXOl/tq+PLC/6I5BjoOZu+AjQ3BPLBOITzvl49TFfP89J4Xq712qtSNFpVRRwBKuPTg72YTSLR382ZL+bx300PgUxcyXk4HzrSLJjTdzmJ+R4Owe1t77gjwDBXZyYvX5kXNWdulHZ5E2g== Received: from DS7P221CA0026.NAMP221.PROD.OUTLOOK.COM (2603:10b6:8:25c::13) by CY5PR12MB6599.namprd12.prod.outlook.com (2603:10b6:930:41::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.10; Wed, 2 Sep 2026 08:39:23 +0000 Received: from DS3PEPF000099DD.namprd04.prod.outlook.com (2603:10b6:8:25c:cafe::8a) by DS7P221CA0026.outlook.office365.com (2603:10b6:8:25c::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.11 via Frontend Transport; Wed, 2 Sep 2026 08:39:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS3PEPF000099DD.mail.protection.outlook.com (10.167.17.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Wed, 2 Sep 2026 08:39:22 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:39:03 -0700 Received: from MVD4TP25H0.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:39:01 -0700 From: To: CC: , Subject: [PATCH 5/6] aarch64: Port NEON rounding intrinsics to the pragma-based framework Date: Wed, 2 Sep 2026 14:08:27 +0530 Message-ID: <20260902083828.45767-6-dhruvc@nvidia.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260902083828.45767-1-dhruvc@nvidia.com> References: <20260902083828.45767-1-dhruvc@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DD:EE_|CY5PR12MB6599:EE_ X-MS-Office365-Filtering-Correlation-Id: f2ce553e-26f6-4f13-0734-08df08cdb056 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|82310400026|23010399003|376014|10067099003|6133799003|3023799007|22082099003|11063799006|56012099006|18002099003|13003099007; X-Microsoft-Antispam-Message-Info: 96R+XYFjtBs5XcLMJoY4z7r+o/T8bt+4eD3IlytZ7ENlNJo3YzYsYghSvHac+L9y6ABPPUVvz6uMC2pLUZUdmr/0ITANzUbAAyU267r1rsqhAu0XOog1EA46kKPu/a5A3VGlI+JlxxcwHMzlck7yjbkJkdn1sMg9sXlc792C7dMwwS6ww+QkEJnWriy0hh/kKMNalTNOCSB2WgWgGiWuIIgd0qOWTd3I8F4C5iYUs+olj/QLu+EVlQuxJ3cALh7rGKjcbm7df2s9PZ9J0GDGHiLOzCW5Z4jUjQRiGHhuCaTcvVdNuL/zh45MZvRE7Ugm4yEtWlZk3CxSEYSmmM02Uru2hJy/wCdmfJ5Vy/UXQ/Rf7S69onnZ03UC6b6/dm4dkcEVOtIaOko/pjqIBQ52rmzRLn+Z3Qt4uF3PbNIfLf55+pPfZrvl7bP5jhhuio/8lr1HvQDi7rTSiW82JsvMlpBd1buSQ30bFjBoLHn/jQjSH2cvci8iUnbmiMwGGpJKfkd5AtgmJOKsJtpauUYMxPYUX5jZPqz/8gPXcFou4mgPeuj1MX95AZWyejRWEDxK39H/waYJO+e0z97PSJpfWDe2conk8gU4YSB7tDeWTWPVur29RIIvrQKICnUl4FdZuWBVLrkZk/PIe9L7nSHQdXs7S9z5h8CrhZaSqno5gA+5bnpD8gS01IKb7l/Uy5zFWULkAGranaO6qyeaEYALKQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(1800799024)(82310400026)(23010399003)(376014)(10067099003)(6133799003)(3023799007)(22082099003)(11063799006)(56012099006)(18002099003)(13003099007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VwvSmRr97tbhaJiQmlpcfJosBF5+d3M6cnfljnxGPI9OA1VwXvUzjtb5SOpdLQunqrcqzhoLRbQ5NlA64xZYXGv3QIi6b+E4buqnY8UYfRgjR2F3KLqROMPaMdVW7YKK+oraPTKuTrqHvmP6WKNYzzjni3NPm4S3qL5JOht50cqKFuKXXLtU+yvXSBmYsiXi/Ac5OQ1zzxiaPL23Mg4/AuNUKCWWeNEv7CxC0i8is4X2tnLC4cG71euX4tqViPhbfHSS1PjSUWYmyXW/ZxnGbNnECu+wwTbsqW+YHXzPvrvgvM85TjTcgezlJOl7BOBbOHs1NNr07Pvdi3iYsE/QdV2ge/gOne9eLxnrD48r4sw2Vmcl0BrgSdvgnpGpAdhfh5CFEM6sXusRWgyN2BHpSeiBuFEqG6WEWyf133IZj09NpW2cRAPV5TMIX4R7ZZ6E X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 08:39:22.8312 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2ce553e-26f6-4f13-0734-08df08cdb056 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6599 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Dhruv Chawla Port the following intrinsics to the pragma-based framework: * vrnd * vrnda * vrndi * vrndm * vrndn * vrndns * vrndp * vrndx The following are not ported in this patch as they cannot be directly lowered from an IFN through an existing instruction pattern: * vrnd_f64 * vrnda_f64 * vrndi_f64 * vrndm_f64 * vrndn_f64 * vrndp_f64 * vrndx_f64 This is because the pattern does not iterate through the mode (V1DF) required to lower them (it uses the VHSDF iterator). Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla gcc/ChangeLog: * config/aarch64/aarch64-neon-builtins-base.cc (vrnd, vrndq, vrnda, vrndaq, vrndi, vrndiq, vrndm, vrndmq, vrndn, vrndns, vrndnq, vrndp, vrndpq, vrndx, vrndxq): New function bases. * config/aarch64/aarch64-neon-builtins-base.def (vrnd, vrndq, vrnda, vrndaq, vrndi, vrndiq, vrndm, vrndmq, vrndn, vrndns, vrndnq, vrndp, vrndpq, vrndx, vrndxq): New function groups. * config/aarch64/arm_neon.h (vrnd_f32, vrndq_f32, vrndq_f64, vrnda_f32, vrndaq_f32, vrndaq_f64, vrndi_f32, vrndiq_f32, vrndiq_f64, vrndm_f32, vrndmq_f32, vrndmq_f64, vrndns_f32, vrndn_f32, vrndnq_f32, vrndnq_f64, vrndp_f32, vrndpq_f32, vrndpq_f64, vrndx_f32, vrndxq_f32, vrndxq_f64, vrnd_f16, vrndq_f16, vrnda_f16, vrndaq_f16, vrndi_f16, vrndiq_f16, vrndm_f16, vrndmq_f16, vrndn_f16, vrndnq_f16, vrndp_f16, vrndpq_f16, vrndx_f16, vrndxq_f16): Delete functions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/neon/vrnd.c: New test. * gcc.target/aarch64/neon/vrnda.c: Likewise. * gcc.target/aarch64/neon/vrndi.c: Likewise. * gcc.target/aarch64/neon/vrndm.c: Likewise. * gcc.target/aarch64/neon/vrndn.c: Likewise. * gcc.target/aarch64/neon/vrndp.c: Likewise. * gcc.target/aarch64/neon/vrndx.c: Likewise. --- .../aarch64/aarch64-neon-builtins-base.cc | 17 ++ .../aarch64/aarch64-neon-builtins-base.def | 37 +++ gcc/config/aarch64/arm_neon.h | 252 ------------------ gcc/testsuite/gcc.target/aarch64/neon/vrnd.c | 45 ++++ gcc/testsuite/gcc.target/aarch64/neon/vrnda.c | 45 ++++ gcc/testsuite/gcc.target/aarch64/neon/vrndi.c | 45 ++++ gcc/testsuite/gcc.target/aarch64/neon/vrndm.c | 45 ++++ gcc/testsuite/gcc.target/aarch64/neon/vrndn.c | 52 ++++ gcc/testsuite/gcc.target/aarch64/neon/vrndp.c | 45 ++++ gcc/testsuite/gcc.target/aarch64/neon/vrndx.c | 45 ++++ 10 files changed, 376 insertions(+), 252 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrnd.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrnda.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndi.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndm.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndp.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndx.c diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index ca4ace4a020..b8bb324f7de 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -789,6 +789,23 @@ NEON_FUNCTION (vrhaddq, gimple_ifn, (IFN_AVG_CEIL)) NEON_FUNCTION (vsqrt, gimple_ifn, (IFN_SQRT)) NEON_FUNCTION (vsqrtq, gimple_ifn, (IFN_SQRT)) +// Rounding +NEON_FUNCTION (vrnd, gimple_ifn, (IFN_TRUNC)) +NEON_FUNCTION (vrndq, gimple_ifn, (IFN_TRUNC)) +NEON_FUNCTION (vrnda, gimple_ifn, (IFN_ROUND)) +NEON_FUNCTION (vrndaq, gimple_ifn, (IFN_ROUND)) +NEON_FUNCTION (vrndi, gimple_ifn, (IFN_NEARBYINT)) +NEON_FUNCTION (vrndiq, gimple_ifn, (IFN_NEARBYINT)) +NEON_FUNCTION (vrndm, gimple_ifn, (IFN_FLOOR)) +NEON_FUNCTION (vrndmq, gimple_ifn, (IFN_FLOOR)) +NEON_FUNCTION (vrndn, gimple_ifn, (IFN_ROUNDEVEN)) +NEON_FUNCTION (vrndnq, gimple_ifn, (IFN_ROUNDEVEN)) +NEON_FUNCTION (vrndp, gimple_ifn, (IFN_CEIL)) +NEON_FUNCTION (vrndpq, gimple_ifn, (IFN_CEIL)) +NEON_FUNCTION (vrndx, gimple_ifn, (IFN_RINT)) +NEON_FUNCTION (vrndxq, gimple_ifn, (IFN_RINT)) +NEON_FUNCTION (vrndns, gimple_ifn, (IFN_ROUNDEVEN)) + // Bitwise operations NEON_FUNCTION (vand, gimple_expr, (BIT_AND_EXPR)) NEON_FUNCTION (vandq, gimple_expr, (BIT_AND_EXPR)) diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index 98efa204e4a..70f14c46f0a 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -134,6 +134,43 @@ DEF_NEON_FUNCTION (vsqrt, h_float, ("D0,D0")) DEF_NEON_FUNCTION (vsqrtq, h_float, ("Q0,Q0")) #undef REQUIRED_EXTENSIONS +// Rounding +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) +DEF_NEON_FUNCTION (vrnd, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndq, sd_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrnda, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndaq, sd_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndi, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndiq, sd_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndm, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndmq, sd_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndn, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndns, s_float, ("s0,s0")) +DEF_NEON_FUNCTION (vrndnq, sd_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndp, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndpq, sd_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndx, s_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndxq, sd_float, ("Q0,Q0")) +#undef REQUIRED_EXTENSIONS + +// Rounding (FP16) +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD | AARCH64_FL_F16) +DEF_NEON_FUNCTION (vrnd, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndq, h_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrnda, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndaq, h_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndi, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndiq, h_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndm, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndmq, h_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndn, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndnq, h_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndp, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndpq, h_float, ("Q0,Q0")) +DEF_NEON_FUNCTION (vrndx, h_float, ("D0,D0")) +DEF_NEON_FUNCTION (vrndxq, h_float, ("Q0,Q0")) +#undef REQUIRED_EXTENSIONS + // Bitwise operations #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) DEF_NEON_FUNCTION (vand, all_integer, ("D0,D0,D0")) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 68f92f76de0..59eba4c70ed 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -15248,13 +15248,6 @@ vrecpxd_f64 (float64_t __a) /* vrnd */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrnd_f32 (float32x2_t __a) -{ - return __builtin_aarch64_btruncv2sf (__a); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrnd_f64 (float64x1_t __a) @@ -15262,29 +15255,8 @@ vrnd_f64 (float64x1_t __a) return vset_lane_f64 (__builtin_trunc (vget_lane_f64 (__a, 0)), __a, 0); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_btruncv4sf (__a); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_btruncv2df (__a); -} - /* vrnda */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrnda_f32 (float32x2_t __a) -{ - return __builtin_aarch64_roundv2sf (__a); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrnda_f64 (float64x1_t __a) @@ -15292,29 +15264,8 @@ vrnda_f64 (float64x1_t __a) return vset_lane_f64 (__builtin_round (vget_lane_f64 (__a, 0)), __a, 0); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndaq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_roundv4sf (__a); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndaq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_roundv2df (__a); -} - /* vrndi */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndi_f32 (float32x2_t __a) -{ - return __builtin_aarch64_nearbyintv2sf (__a); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrndi_f64 (float64x1_t __a) @@ -15322,29 +15273,8 @@ vrndi_f64 (float64x1_t __a) return vset_lane_f64 (__builtin_nearbyint (vget_lane_f64 (__a, 0)), __a, 0); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndiq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_nearbyintv4sf (__a); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndiq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_nearbyintv2df (__a); -} - /* vrndm */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndm_f32 (float32x2_t __a) -{ - return __builtin_aarch64_floorv2sf (__a); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrndm_f64 (float64x1_t __a) @@ -15352,36 +15282,8 @@ vrndm_f64 (float64x1_t __a) return vset_lane_f64 (__builtin_floor (vget_lane_f64 (__a, 0)), __a, 0); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndmq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_floorv4sf (__a); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndmq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_floorv2df (__a); -} - /* vrndn */ -__extension__ extern __inline float32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndns_f32 (float32_t __a) -{ - return __builtin_aarch64_roundevensf (__a); -} - -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndn_f32 (float32x2_t __a) -{ - return __builtin_aarch64_roundevenv2sf (__a); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrndn_f64 (float64x1_t __a) @@ -15389,29 +15291,8 @@ vrndn_f64 (float64x1_t __a) return (float64x1_t) {__builtin_aarch64_roundevendf (__a[0])}; } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndnq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_roundevenv4sf (__a); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndnq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_roundevenv2df (__a); -} - /* vrndp */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndp_f32 (float32x2_t __a) -{ - return __builtin_aarch64_ceilv2sf (__a); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrndp_f64 (float64x1_t __a) @@ -15419,29 +15300,8 @@ vrndp_f64 (float64x1_t __a) return vset_lane_f64 (__builtin_ceil (vget_lane_f64 (__a, 0)), __a, 0); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndpq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_ceilv4sf (__a); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndpq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_ceilv2df (__a); -} - /* vrndx */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndx_f32 (float32x2_t __a) -{ - return __builtin_aarch64_rintv2sf (__a); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrndx_f64 (float64x1_t __a) @@ -15449,20 +15309,6 @@ vrndx_f64 (float64x1_t __a) return vset_lane_f64 (__builtin_rint (vget_lane_f64 (__a, 0)), __a, 0); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndxq_f32 (float32x4_t __a) -{ - return __builtin_aarch64_rintv4sf (__a); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndxq_f64 (float64x2_t __a) -{ - return __builtin_aarch64_rintv2df (__a); -} - /* vrshl */ __extension__ extern __inline int8x8_t @@ -19186,104 +19032,6 @@ vrecpeq_f16 (float16x8_t __a) return __builtin_aarch64_frecpev8hf (__a); } -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrnd_f16 (float16x4_t __a) -{ - return __builtin_aarch64_btruncv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_btruncv8hf (__a); -} - -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrnda_f16 (float16x4_t __a) -{ - return __builtin_aarch64_roundv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndaq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_roundv8hf (__a); -} - -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndi_f16 (float16x4_t __a) -{ - return __builtin_aarch64_nearbyintv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndiq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_nearbyintv8hf (__a); -} - -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndm_f16 (float16x4_t __a) -{ - return __builtin_aarch64_floorv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndmq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_floorv8hf (__a); -} - -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndn_f16 (float16x4_t __a) -{ - return __builtin_aarch64_roundevenv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndnq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_roundevenv8hf (__a); -} - -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndp_f16 (float16x4_t __a) -{ - return __builtin_aarch64_ceilv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndpq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_ceilv8hf (__a); -} - -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndx_f16 (float16x4_t __a) -{ - return __builtin_aarch64_rintv4hf (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vrndxq_f16 (float16x8_t __a) -{ - return __builtin_aarch64_rintv8hf (__a); -} - __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrsqrte_f16 (float16x4_t __a) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrnd.c b/gcc/testsuite/gcc.target/aarch64/neon/vrnd.c new file mode 100644 index 00000000000..6c4ce68b947 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrnd.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrnd_f16: +** frintz v0\.4h, v0\.4h +** ret +*/ +TEST_UNIFORM_UNARY (vrnd_f16, float16x4_t) + +/* +** test_vrnd_f32: +** frintz v0\.2s, v0\.2s +** ret +*/ +TEST_UNIFORM_UNARY (vrnd_f32, float32x2_t) + +/* +** test_vrnd_f64: +** frintz d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vrnd_f64, float64x1_t) + +/* +** test_vrndq_f16: +** frintz v0\.8h, v0\.8h +** ret +*/ +TEST_UNIFORM_UNARY (vrndq_f16, float16x8_t) + +/* +** test_vrndq_f32: +** frintz v0\.4s, v0\.4s +** ret +*/ +TEST_UNIFORM_UNARY (vrndq_f32, float32x4_t) +/* +** test_vrndq_f64: +** frintz v0\.2d, v0\.2d +** ret +*/ +TEST_UNIFORM_UNARY (vrndq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrnda.c b/gcc/testsuite/gcc.target/aarch64/neon/vrnda.c new file mode 100644 index 00000000000..f62cd744f1b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrnda.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrnda_f16: +** frinta v0\.4h, v0\.4h +** ret +*/ +TEST_UNIFORM_UNARY (vrnda_f16, float16x4_t) + +/* +** test_vrnda_f32: +** frinta v0\.2s, v0\.2s +** ret +*/ +TEST_UNIFORM_UNARY (vrnda_f32, float32x2_t) + +/* +** test_vrnda_f64: +** frinta d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vrnda_f64, float64x1_t) + +/* +** test_vrndaq_f16: +** frinta v0\.8h, v0\.8h +** ret +*/ +TEST_UNIFORM_UNARY (vrndaq_f16, float16x8_t) + +/* +** test_vrndaq_f32: +** frinta v0\.4s, v0\.4s +** ret +*/ +TEST_UNIFORM_UNARY (vrndaq_f32, float32x4_t) +/* +** test_vrndaq_f64: +** frinta v0\.2d, v0\.2d +** ret +*/ +TEST_UNIFORM_UNARY (vrndaq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrndi.c b/gcc/testsuite/gcc.target/aarch64/neon/vrndi.c new file mode 100644 index 00000000000..3e25f068c60 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrndi.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrndi_f16: +** frinti v0\.4h, v0\.4h +** ret +*/ +TEST_UNIFORM_UNARY (vrndi_f16, float16x4_t) + +/* +** test_vrndi_f32: +** frinti v0\.2s, v0\.2s +** ret +*/ +TEST_UNIFORM_UNARY (vrndi_f32, float32x2_t) + +/* +** test_vrndi_f64: +** frinti d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vrndi_f64, float64x1_t) + +/* +** test_vrndiq_f16: +** frinti v0\.8h, v0\.8h +** ret +*/ +TEST_UNIFORM_UNARY (vrndiq_f16, float16x8_t) + +/* +** test_vrndiq_f32: +** frinti v0\.4s, v0\.4s +** ret +*/ +TEST_UNIFORM_UNARY (vrndiq_f32, float32x4_t) +/* +** test_vrndiq_f64: +** frinti v0\.2d, v0\.2d +** ret +*/ +TEST_UNIFORM_UNARY (vrndiq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrndm.c b/gcc/testsuite/gcc.target/aarch64/neon/vrndm.c new file mode 100644 index 00000000000..9b3a27f640d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrndm.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrndm_f16: +** frintm v0\.4h, v0\.4h +** ret +*/ +TEST_UNIFORM_UNARY (vrndm_f16, float16x4_t) + +/* +** test_vrndm_f32: +** frintm v0\.2s, v0\.2s +** ret +*/ +TEST_UNIFORM_UNARY (vrndm_f32, float32x2_t) + +/* +** test_vrndm_f64: +** frintm d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vrndm_f64, float64x1_t) + +/* +** test_vrndmq_f16: +** frintm v0\.8h, v0\.8h +** ret +*/ +TEST_UNIFORM_UNARY (vrndmq_f16, float16x8_t) + +/* +** test_vrndmq_f32: +** frintm v0\.4s, v0\.4s +** ret +*/ +TEST_UNIFORM_UNARY (vrndmq_f32, float32x4_t) +/* +** test_vrndmq_f64: +** frintm v0\.2d, v0\.2d +** ret +*/ +TEST_UNIFORM_UNARY (vrndmq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrndn.c b/gcc/testsuite/gcc.target/aarch64/neon/vrndn.c new file mode 100644 index 00000000000..48606cec14f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrndn.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrndn_f16: +** frintn v0\.4h, v0\.4h +** ret +*/ +TEST_UNIFORM_UNARY (vrndn_f16, float16x4_t) + +/* +** test_vrndn_f32: +** frintn v0\.2s, v0\.2s +** ret +*/ +TEST_UNIFORM_UNARY (vrndn_f32, float32x2_t) + +/* +** test_vrndn_f64: +** frintn d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vrndn_f64, float64x1_t) + +/* +** test_vrndnq_f16: +** frintn v0\.8h, v0\.8h +** ret +*/ +TEST_UNIFORM_UNARY (vrndnq_f16, float16x8_t) + +/* +** test_vrndnq_f32: +** frintn v0\.4s, v0\.4s +** ret +*/ +TEST_UNIFORM_UNARY (vrndnq_f32, float32x4_t) +/* +** test_vrndnq_f64: +** frintn v0\.2d, v0\.2d +** ret +*/ +TEST_UNIFORM_UNARY (vrndnq_f64, float64x2_t) + +/* +** test_vrndns_f32: +** frintn s0, s0 +** ret +*/ +TEST_UNIFORM_UNARY (vrndns_f32, float32_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrndp.c b/gcc/testsuite/gcc.target/aarch64/neon/vrndp.c new file mode 100644 index 00000000000..1d2b75bb8d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrndp.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrndp_f16: +** frintp v0\.4h, v0\.4h +** ret +*/ +TEST_UNIFORM_UNARY (vrndp_f16, float16x4_t) + +/* +** test_vrndp_f32: +** frintp v0\.2s, v0\.2s +** ret +*/ +TEST_UNIFORM_UNARY (vrndp_f32, float32x2_t) + +/* +** test_vrndp_f64: +** frintp d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vrndp_f64, float64x1_t) + +/* +** test_vrndpq_f16: +** frintp v0\.8h, v0\.8h +** ret +*/ +TEST_UNIFORM_UNARY (vrndpq_f16, float16x8_t) + +/* +** test_vrndpq_f32: +** frintp v0\.4s, v0\.4s +** ret +*/ +TEST_UNIFORM_UNARY (vrndpq_f32, float32x4_t) +/* +** test_vrndpq_f64: +** frintp v0\.2d, v0\.2d +** ret +*/ +TEST_UNIFORM_UNARY (vrndpq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vrndx.c b/gcc/testsuite/gcc.target/aarch64/neon/vrndx.c new file mode 100644 index 00000000000..5f3d92e0a54 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vrndx.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vrndx_f16: +** frintx v0\.4h, v0\.4h +** ret +*/ +TEST_UNIFORM_UNARY (vrndx_f16, float16x4_t) + +/* +** test_vrndx_f32: +** frintx v0\.2s, v0\.2s +** ret +*/ +TEST_UNIFORM_UNARY (vrndx_f32, float32x2_t) + +/* +** test_vrndx_f64: +** frintx d0, d0 +** ret +*/ +TEST_UNIFORM_UNARY (vrndx_f64, float64x1_t) + +/* +** test_vrndxq_f16: +** frintx v0\.8h, v0\.8h +** ret +*/ +TEST_UNIFORM_UNARY (vrndxq_f16, float16x8_t) + +/* +** test_vrndxq_f32: +** frintx v0\.4s, v0\.4s +** ret +*/ +TEST_UNIFORM_UNARY (vrndxq_f32, float32x4_t) +/* +** test_vrndxq_f64: +** frintx v0\.2d, v0\.2d +** ret +*/ +TEST_UNIFORM_UNARY (vrndxq_f64, float64x2_t) From patchwork Wed Sep 2 08:38:28 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruv Chawla X-Patchwork-Id: 2296452 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=n8O+UnxE; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZbq70l7Nz1xwg for ; Wed, 02 Sep 2026 18:43:31 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BCC4F4BA2E14 for ; Wed, 2 Sep 2026 08:43:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BCC4F4BA2E14 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=n8O+UnxE X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazlp170130007.outbound.protection.outlook.com [IPv6:2a01:111:f403:c105::7]) by sourceware.org (Postfix) with ESMTPS id 39C444BA23E2 for ; Wed, 2 Sep 2026 08:39:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 39C444BA23E2 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=nvidia.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 39C444BA23E2 Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=2a01:111:f403:c105::7 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338373; cv=pass; b=v9wpx3eqWwk9eF4Lf+2wKynGb3GjmFtLIWPbw/DjaXyosL9gSkTtVObbke2FUaDYK3lcbahMBatpvQAibrgbsnvVsELpC/+MvgM6rHZYf38CVRawdIAWBSldDsal7rAheMxhrILuRzjdqsXDQCHHGrF0E+/RIAHsPeDHi7ECT+o= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1788338373; c=relaxed/simple; bh=ZP6e3XXtiPOKpDKVcDQKqVvqwlLN/5ugEw3WGRyo+as=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=s89OWxZs43S5N0ks0S0dRyv+0J0/lYWGDDRqnpcbpAzOvRvEiSwe1ElQYsSPIxvBXyxYHMsg1wr6GNQEMrslajCrPP5XwodAPxg1OTpSHTVvfkc9rE4O1DFeKPPIXZYDsdaAD6tZxox5QYtx0mucRtsXZV0iAuROie1Vu4P0Sxc= ARC-Authentication-Results: i=2; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=n8O+UnxE DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 39C444BA23E2 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=BYmyEsZ3KG70mRd4CV6ttffOzk581SuTexsiLQaGAYXwyJDF9JCOhDzanotEO2PBQPfvrD6p3OZ+oHTbNTgfLAuLhDBHnv9bcHnnx0Cl7gJ88LceVFg7YhFANW3t6S+4AgXfysH/97yVlMlIVqRsaZ6VKieoPIdAvgA7dR/lIjl3EtaYO+0GV12ncFSX/PFM1hiXhOhv4moeLYTh3gg6NgYr001BMS2kA/Uo2Tgem+/8vNGEZGkKbLZ3CLbJQ7avxcDJp9ME9fcO6bgI4+AzRzaTeH6LEnpcuoflcRYaI8vJfipkynZgglsjhpAzlCmI5xNC/NrgSGX8seEK2FDocg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UOWqAhuh2dH/rVeUxLIYpixbgyPeSUQX/wpBsyCWa3k=; b=DrByebcVkICBr3ukfzmI0zHfG9btRy0adphnmixOi/WnxGF9EgwqCJE9/ffwMCmBXWgRaKSfPUb4I0rZ6E3quqUBkR62SNJ9rbRcEhuvwVBfrbJAzSxapTzsTqwLXI3UfIzBrlQovTlHB7PImMIAgyYU7ow3lqb6M+gKmWPWH5UH3i4DjItZ037YrsXmIBl1ihzXdYHPSonYvK9v0ow5Iq1OPqSRvXE0SkAFOLkXqmaj0zld77a6CtQl1Io697IBDPX//lnY7UtNbDcMXRRk3JnFuQwdC1UWhtIaDT0gNdkIHdUzakBsV7ncwvLXg51ytrK8VeCn2y7izkwE9rOqZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UOWqAhuh2dH/rVeUxLIYpixbgyPeSUQX/wpBsyCWa3k=; b=n8O+UnxEzMoE3rtJUH/zEGBU3HRdh1yDzRmICESkcMGb/heV+rBYUlcVrnq6Gk5H/INGMG+PfYuyCzbGRg2dt3FO3lzSqv4I7sFfDAllvZlL437eh1x68a263Xjkbc+OdKqt8qr/yqDaFQe04JVhtvb24irBQjCKZ6J5TYf1Wejmbs4WJ07agKLlXZ4lURya60k2Ml440+b1fAxi924WGNZ0CDJdYxFcSMvaSVIQI5+Te+emOSshCSLcg0msCQCIL+/L4Ge2SNJuEnE5aFPiFucQ0PExdnKwjBXgVQ1NaDrMPZ7HGiiL8XvyM1LfbZ6VRfJtXmGP7lW6NMiGT3iqxw== Received: from CH0PR03CA0096.namprd03.prod.outlook.com (2603:10b6:610:cd::11) by DS0PR12MB7557.namprd12.prod.outlook.com (2603:10b6:8:130::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.11; Wed, 2 Sep 2026 08:39:25 +0000 Received: from DS3PEPF000099DB.namprd04.prod.outlook.com (2603:10b6:610:cd:cafe::8d) by CH0PR03CA0096.outlook.office365.com (2603:10b6:610:cd::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.11 via Frontend Transport; Wed, 2 Sep 2026 08:39:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS3PEPF000099DB.mail.protection.outlook.com (10.167.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Wed, 2 Sep 2026 08:39:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:39:05 -0700 Received: from MVD4TP25H0.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 2 Sep 2026 01:39:03 -0700 From: To: CC: , Subject: [PATCH 6/6] aarch64: Port NEON min/max intrinsics to the pragma-based framework Date: Wed, 2 Sep 2026 14:08:28 +0530 Message-ID: <20260902083828.45767-7-dhruvc@nvidia.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260902083828.45767-1-dhruvc@nvidia.com> References: <20260902083828.45767-1-dhruvc@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|DS0PR12MB7557:EE_ X-MS-Office365-Filtering-Correlation-Id: 53f7a9d3-9a09-4250-6029-08df08cdb16b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700016|23010399003|1800799024|376014|22082099003|18002099003|3023799007|13003099007|56012099006|11063799006|10067099003|6133799003; X-Microsoft-Antispam-Message-Info: PpYjLDnHo73pcsSa4aQkRyF8ET67wUB22umubEQhSniGCLHqDvEVWK5czCMyqvwYBkwnripyyPYRhv+6EbbMqmg6rNEhE0dYBnrGelS4z2PJCJ//0TWhAJUsOLJSF63lEl2v9rkgikqV112k5NfadJZV4GdJYmFxrANve5ypDTZcM3etV/3bHj1l9MMfJK0yo8v6Rh6xT0cnTycdiPCu7x3w9GNAZuVmR06Ev0/kmQ0MReaMohQJ9GnirNozFBhxbSWZuL9wqVj3zQh7HZPGgKM9ZQkayihG8kddrmfTSSN+Sc0VHTTVgcBGno292iDsiO442sVusnsAYzJeC9j0Gs1qD8vhvAguGzdbhRc84b7Dfy8TPVtNz9xs0xkVZBN3uMMbg1q4BA3RSs2pgqY8xtX5TuJ8kgY+vDJUKQ/Qs+qO4k1Vle1eOEH9TodzTHCIJEjr6OQI10UVCTBwh+86B+Y/qxGiTyKyryQv/5sukksX0kByuB9OKYDvVREWAfpkkw4x79IgzNcUo3RyVzJODbouZJRpAfdm+zBvlP8RkSfn6trGeki/KOpPhWvDZB4IiQxzSIX4VdsdbhRV0QF/Qrd0dKnHZHq1G7hoGt0bSUbFJiaFOenboviEJDXWN1U7M+6TtC0audK0t+yyK8OsRgMucQC7mnSfcfcwwLq7dhP22LbTRO8CdKa4YFmN/Um4q9QIkd270h8TvT2r7fPfng== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700016)(23010399003)(1800799024)(376014)(22082099003)(18002099003)(3023799007)(13003099007)(56012099006)(11063799006)(10067099003)(6133799003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6XhyYasr7n7pLNnQRKvHph0lMGH6hq2J/JIzvl139/aVm4ITx8s3f0fKlPojo3acZcoPL1+vdPOeGyg7U11pcnPcsKVSpxoDBrxiA7q+ioJswXA5MvC23gr9whGkgfBPS153MzafRWZI9qcol7p3wT3symTzYEkcH1ullWMK5bQThubRPBL7qgRCeU2g04UFvQH2PsxBIU3TGba5XcOt+AxJr0WbuWTMw4WkwHFYOppG2tJVix7gMNeoMCZV9Y0JM4PwIisvgxjEgrPuBJeb2AufjEAAevYLBuvXMoY5aJMaGO8tB9JTUYQqDjmccMYSp1PRcw0ApD6+qiq94UlkwW3OmaB1n5uI2lr0SXkCsWZxzHhvIdqiiWoLL9RsFhZIzsM2fHNkzOQst/0GIh00rvJdCyI5noW8WCJI5JEYCAL2lfqU032UL+LF1T83P8MC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 08:39:24.6389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53f7a9d3-9a09-4250-6029-08df08cdb16b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7557 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Dhruv Chawla Port the following intrinsics to the pragma-based framework: * vmax * vmin * vmaxnm * vminnm The faminmax-no-codegen.c test now ends up folding to a single instruction (famax / famin) in a few cases. The following are not ported in this patch as they cannot be directly lowered from an IFN through an existing instruction pattern: * vmax_f16 * vmax_f32 * vmax_f64 * vmaxq_f16 * vmaxq_f32 * vmaxq_f64 * vmin_f16 * vmin_f32 * vmin_f64 * vminq_f16 * vminq_f32 * vminq_f64 This is due to the NaN semantics of these intrinsics which require lowering to _nan variants. * vmaxnm_f64 * vminnm_f64 This is due to the iterator used in the pattern (VHSDF) not covering the mode (V1DF) for these intrinsics. Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla gcc/ChangeLog: * config/aarch64/aarch64-neon-builtins-base.cc (vmax, vmaxq, vmin, vminq, vmaxnm, vmaxnmq, vminnm, vminnmq): New function bases. * config/aarch64/aarch64-neon-builtins-base.def (vmax, vmaxq, vmin, vminq, vmaxnm, vmaxnmq, vminnm, vminnmq): New function groups. * config/aarch64/arm_neon.h (vmax_s8, vmax_s16, vmax_s32, vmax_u8, vmax_u16, vmax_u32, vmaxq_s8, vmaxq_s16, vmaxq_s32, vmaxq_u8, vmaxq_u16, vmaxq_u32, vmaxnm_f32, vmaxnmq_f32, vmaxnmq_f64, vmin_s8, vmin_s16, vmin_s32, vmin_u8, vmin_u16, vmin_u32, vminq_s8, vminq_s16, vminq_s32, vminq_u8, vminq_u16, vminq_u32, vminnm_f32, vminnmq_f32, vminnmq_f64, vmaxnm_f16, vmaxnmq_f16, vminnm_f16, vminnmq_f16): Delete functions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/faminmax-no-codegen.c: Update check-function-bodies checks. * gcc.target/aarch64/neon/vmax.c: New test. * gcc.target/aarch64/neon/vmaxnm.c: Likewise. * gcc.target/aarch64/neon/vmin.c: Likewise. * gcc.target/aarch64/neon/vminnm.c: Likewise. --- .../aarch64/aarch64-neon-builtins-base.cc | 10 + .../aarch64/aarch64-neon-builtins-base.def | 20 ++ gcc/config/aarch64/arm_neon.h | 249 ------------------ gcc/testsuite/gcc.target/aarch64/neon/vmax.c | 130 +++++++++ .../gcc.target/aarch64/neon/vmaxnm.c | 46 ++++ gcc/testsuite/gcc.target/aarch64/neon/vmin.c | 130 +++++++++ .../gcc.target/aarch64/neon/vminnm.c | 46 ++++ .../aarch64/simd/faminmax-no-codegen.c | 40 +-- 8 files changed, 392 insertions(+), 279 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmax.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxnm.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmin.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminnm.c diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index b8bb324f7de..487c5dac302 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -767,6 +767,16 @@ NEON_FUNCTION (vqsubd, gimple_ifn, (IFN_SAT_SUB)) NEON_FUNCTION (vqsub, gimple_ifn, (IFN_SAT_SUB)) NEON_FUNCTION (vqsubq, gimple_ifn, (IFN_SAT_SUB)) +// Max/min +NEON_FUNCTION (vmax, gimple_expr, (MAX_EXPR)) +NEON_FUNCTION (vmaxq, gimple_expr, (MAX_EXPR)) +NEON_FUNCTION (vmin, gimple_expr, (MIN_EXPR)) +NEON_FUNCTION (vminq, gimple_expr, (MIN_EXPR)) +NEON_FUNCTION (vmaxnm, gimple_ifn, (IFN_FMAX)) +NEON_FUNCTION (vmaxnmq, gimple_ifn, (IFN_FMAX)) +NEON_FUNCTION (vminnm, gimple_ifn, (IFN_FMIN)) +NEON_FUNCTION (vminnmq, gimple_ifn, (IFN_FMIN)) + // Reductions NEON_FUNCTION (vaddv, gimple_ifn, (IFN_REDUC_PLUS)) NEON_FUNCTION (vaddvq, gimple_ifn, (IFN_REDUC_PLUS)) diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index 70f14c46f0a..21181aacc9b 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -92,6 +92,26 @@ DEF_NEON_FUNCTION (vqsub, bhs_integer, ("D0,D0,D0")) DEF_NEON_FUNCTION (vqsubq, all_integer, ("Q0,Q0,Q0")) #undef REQUIRED_EXTENSIONS +// Max/min +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) +DEF_NEON_FUNCTION (vmax, bhs_integer, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vmaxq, bhs_integer, ("Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vmin, bhs_integer, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vminq, bhs_integer, ("Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vmaxnm, s_float, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vmaxnmq, sd_float, ("Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vminnm, s_float, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vminnmq, sd_float, ("Q0,Q0,Q0")) +#undef REQUIRED_EXTENSIONS + +// Max/min (FP16) +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD | AARCH64_FL_F16) +DEF_NEON_FUNCTION (vmaxnm, h_float, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vmaxnmq, h_float, ("Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vminnm, h_float, ("D0,D0,D0")) +DEF_NEON_FUNCTION (vminnmq, h_float, ("Q0,Q0,Q0")) +#undef REQUIRED_EXTENSIONS + // Reductions #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD) DEF_NEON_FUNCTION (vaddv, s_float_bhs_integer, ("s0,D0")) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 59eba4c70ed..ea82a7ed719 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -11504,51 +11504,6 @@ vmax_f64 (float64x1_t __a, float64x1_t __b) vget_lane_f64 (__b, 0)) }; } -__extension__ extern __inline int8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmax_s8 (int8x8_t __a, int8x8_t __b) -{ - return __builtin_aarch64_smaxv8qi (__a, __b); -} - -__extension__ extern __inline int16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmax_s16 (int16x4_t __a, int16x4_t __b) -{ - return __builtin_aarch64_smaxv4hi (__a, __b); -} - -__extension__ extern __inline int32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmax_s32 (int32x2_t __a, int32x2_t __b) -{ - return __builtin_aarch64_smaxv2si (__a, __b); -} - -__extension__ extern __inline uint8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmax_u8 (uint8x8_t __a, uint8x8_t __b) -{ - return (uint8x8_t) __builtin_aarch64_umaxv8qi ((int8x8_t) __a, - (int8x8_t) __b); -} - -__extension__ extern __inline uint16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmax_u16 (uint16x4_t __a, uint16x4_t __b) -{ - return (uint16x4_t) __builtin_aarch64_umaxv4hi ((int16x4_t) __a, - (int16x4_t) __b); -} - -__extension__ extern __inline uint32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmax_u32 (uint32x2_t __a, uint32x2_t __b) -{ - return (uint32x2_t) __builtin_aarch64_umaxv2si ((int32x2_t) __a, - (int32x2_t) __b); -} - __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmaxq_f32 (float32x4_t __a, float32x4_t __b) @@ -11563,50 +11518,6 @@ vmaxq_f64 (float64x2_t __a, float64x2_t __b) return __builtin_aarch64_fmax_nanv2df (__a, __b); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxq_s8 (int8x16_t __a, int8x16_t __b) -{ - return __builtin_aarch64_smaxv16qi (__a, __b); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxq_s16 (int16x8_t __a, int16x8_t __b) -{ - return __builtin_aarch64_smaxv8hi (__a, __b); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxq_s32 (int32x4_t __a, int32x4_t __b) -{ - return __builtin_aarch64_smaxv4si (__a, __b); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxq_u8 (uint8x16_t __a, uint8x16_t __b) -{ - return (uint8x16_t) __builtin_aarch64_umaxv16qi ((int8x16_t) __a, - (int8x16_t) __b); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxq_u16 (uint16x8_t __a, uint16x8_t __b) -{ - return (uint16x8_t) __builtin_aarch64_umaxv8hi ((int16x8_t) __a, - (int16x8_t) __b); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return (uint32x4_t) __builtin_aarch64_umaxv4si ((int32x4_t) __a, - (int32x4_t) __b); -} /* vmulx */ __extension__ extern __inline float32x2_t @@ -12065,13 +11976,6 @@ vpminnms_f32 (float32x2_t __a) /* vmaxnm */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnm_f32 (float32x2_t __a, float32x2_t __b) -{ - return __builtin_aarch64_fmaxv2sf (__a, __b); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmaxnm_f64 (float64x1_t __a, float64x1_t __b) @@ -12081,20 +11985,6 @@ vmaxnm_f64 (float64x1_t __a, float64x1_t __b) vget_lane_f64 (__b, 0)) }; } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) -{ - return __builtin_aarch64_fmaxv4sf (__a, __b); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmq_f64 (float64x2_t __a, float64x2_t __b) -{ - return __builtin_aarch64_fmaxv2df (__a, __b); -} - /* vmaxv */ __extension__ extern __inline float32_t @@ -12136,51 +12026,6 @@ vmin_f64 (float64x1_t __a, float64x1_t __b) vget_lane_f64 (__b, 0)) }; } -__extension__ extern __inline int8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmin_s8 (int8x8_t __a, int8x8_t __b) -{ - return __builtin_aarch64_sminv8qi (__a, __b); -} - -__extension__ extern __inline int16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmin_s16 (int16x4_t __a, int16x4_t __b) -{ - return __builtin_aarch64_sminv4hi (__a, __b); -} - -__extension__ extern __inline int32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmin_s32 (int32x2_t __a, int32x2_t __b) -{ - return __builtin_aarch64_sminv2si (__a, __b); -} - -__extension__ extern __inline uint8x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmin_u8 (uint8x8_t __a, uint8x8_t __b) -{ - return (uint8x8_t) __builtin_aarch64_uminv8qi ((int8x8_t) __a, - (int8x8_t) __b); -} - -__extension__ extern __inline uint16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmin_u16 (uint16x4_t __a, uint16x4_t __b) -{ - return (uint16x4_t) __builtin_aarch64_uminv4hi ((int16x4_t) __a, - (int16x4_t) __b); -} - -__extension__ extern __inline uint32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmin_u32 (uint32x2_t __a, uint32x2_t __b) -{ - return (uint32x2_t) __builtin_aarch64_uminv2si ((int32x2_t) __a, - (int32x2_t) __b); -} - __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vminq_f32 (float32x4_t __a, float32x4_t __b) @@ -12195,60 +12040,8 @@ vminq_f64 (float64x2_t __a, float64x2_t __b) return __builtin_aarch64_fmin_nanv2df (__a, __b); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminq_s8 (int8x16_t __a, int8x16_t __b) -{ - return __builtin_aarch64_sminv16qi (__a, __b); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminq_s16 (int16x8_t __a, int16x8_t __b) -{ - return __builtin_aarch64_sminv8hi (__a, __b); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminq_s32 (int32x4_t __a, int32x4_t __b) -{ - return __builtin_aarch64_sminv4si (__a, __b); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminq_u8 (uint8x16_t __a, uint8x16_t __b) -{ - return (uint8x16_t) __builtin_aarch64_uminv16qi ((int8x16_t) __a, - (int8x16_t) __b); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminq_u16 (uint16x8_t __a, uint16x8_t __b) -{ - return (uint16x8_t) __builtin_aarch64_uminv8hi ((int16x8_t) __a, - (int16x8_t) __b); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return (uint32x4_t) __builtin_aarch64_uminv4si ((int32x4_t) __a, - (int32x4_t) __b); -} - /* vminnm */ -__extension__ extern __inline float32x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnm_f32 (float32x2_t __a, float32x2_t __b) -{ - return __builtin_aarch64_fminv2sf (__a, __b); -} - __extension__ extern __inline float64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vminnm_f64 (float64x1_t __a, float64x1_t __b) @@ -12258,20 +12051,6 @@ vminnm_f64 (float64x1_t __a, float64x1_t __b) vget_lane_f64 (__b, 0)) }; } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmq_f32 (float32x4_t __a, float32x4_t __b) -{ - return __builtin_aarch64_fminv4sf (__a, __b); -} - -__extension__ extern __inline float64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmq_f64 (float64x2_t __a, float64x2_t __b) -{ - return __builtin_aarch64_fminv2df (__a, __b); -} - /* vminv */ __extension__ extern __inline float32_t @@ -19272,20 +19051,6 @@ vmaxq_f16 (float16x8_t __a, float16x8_t __b) return __builtin_aarch64_fmax_nanv8hf (__a, __b); } -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnm_f16 (float16x4_t __a, float16x4_t __b) -{ - return __builtin_aarch64_fmaxv4hf (__a, __b); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmaxnmq_f16 (float16x8_t __a, float16x8_t __b) -{ - return __builtin_aarch64_fmaxv8hf (__a, __b); -} - __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmin_f16 (float16x4_t __a, float16x4_t __b) @@ -19300,20 +19065,6 @@ vminq_f16 (float16x8_t __a, float16x8_t __b) return __builtin_aarch64_fmin_nanv8hf (__a, __b); } -__extension__ extern __inline float16x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnm_f16 (float16x4_t __a, float16x4_t __b) -{ - return __builtin_aarch64_fminv4hf (__a, __b); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vminnmq_f16 (float16x8_t __a, float16x8_t __b) -{ - return __builtin_aarch64_fminv8hf (__a, __b); -} - __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmul_f16 (float16x4_t __a, float16x4_t __b) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vmax.c b/gcc/testsuite/gcc.target/aarch64/neon/vmax.c new file mode 100644 index 00000000000..ac22958f096 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vmax.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vmax_u8: +** umax v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_u8, uint8x8_t) + +/* +** test_vmax_s8: +** smax v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_s8, int8x8_t) + +/* +** test_vmax_u16: +** umax v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_u16, uint16x4_t) + +/* +** test_vmax_s16: +** smax v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_s16, int16x4_t) + +/* +** test_vmax_f16: +** fmax v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_f16, float16x4_t) + +/* +** test_vmax_u32: +** umax v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_u32, uint32x2_t) + +/* +** test_vmax_s32: +** smax v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_s32, int32x2_t) + +/* +** test_vmax_f32: +** fmax v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_f32, float32x2_t) + +/* +** test_vmax_f64: +** fmax d0, (d0, d1|d1, d0) +** ret +*/ +TEST_UNIFORM_BINARY (vmax_f64, float64x1_t) + +/* +** test_vmaxq_u8: +** umax v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_u8, uint8x16_t) + +/* +** test_vmaxq_s8: +** smax v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_s8, int8x16_t) + +/* +** test_vmaxq_u16: +** umax v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_u16, uint16x8_t) + +/* +** test_vmaxq_s16: +** smax v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_s16, int16x8_t) + +/* +** test_vmaxq_f16: +** fmax v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_f16, float16x8_t) + +/* +** test_vmaxq_u32: +** umax v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_u32, uint32x4_t) + +/* +** test_vmaxq_s32: +** smax v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_s32, int32x4_t) + +/* +** test_vmaxq_f32: +** fmax v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_f32, float32x4_t) + +/* +** test_vmaxq_f64: +** fmax v0\.2d, (v0\.2d, v1\.2d|v1\.2d, v0\.2d) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vmaxnm.c b/gcc/testsuite/gcc.target/aarch64/neon/vmaxnm.c new file mode 100644 index 00000000000..e2bee718811 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vmaxnm.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vmaxnm_f16: +** fmaxnm v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxnm_f16, float16x4_t) + +/* +** test_vmaxnm_f32: +** fmaxnm v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxnm_f32, float32x2_t) + +/* +** test_vmaxnm_f64: +** fmaxnm d0, (d0, d1|d1, d0) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxnm_f64, float64x1_t) + +/* +** test_vmaxnmq_f16: +** fmaxnm v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxnmq_f16, float16x8_t) + +/* +** test_vmaxnmq_f32: +** fmaxnm v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxnmq_f32, float32x4_t) + +/* +** test_vmaxnmq_f64: +** fmaxnm v0\.2d, (v0\.2d, v1\.2d|v1\.2d, v0\.2d) +** ret +*/ +TEST_UNIFORM_BINARY (vmaxnmq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vmin.c b/gcc/testsuite/gcc.target/aarch64/neon/vmin.c new file mode 100644 index 00000000000..13b582c0449 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vmin.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vmin_u8: +** umin v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_u8, uint8x8_t) + +/* +** test_vmin_s8: +** smin v0\.8b, (v0\.8b, v1\.8b|v1\.8b, v0\.8b) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_s8, int8x8_t) + +/* +** test_vmin_u16: +** umin v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_u16, uint16x4_t) + +/* +** test_vmin_s16: +** smin v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_s16, int16x4_t) + +/* +** test_vmin_f16: +** fmin v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_f16, float16x4_t) + +/* +** test_vmin_u32: +** umin v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_u32, uint32x2_t) + +/* +** test_vmin_s32: +** smin v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_s32, int32x2_t) + +/* +** test_vmin_f32: +** fmin v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_f32, float32x2_t) + +/* +** test_vmin_f64: +** fmin d0, (d0, d1|d1, d0) +** ret +*/ +TEST_UNIFORM_BINARY (vmin_f64, float64x1_t) + +/* +** test_vminq_u8: +** umin v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_u8, uint8x16_t) + +/* +** test_vminq_s8: +** smin v0\.16b, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_s8, int8x16_t) + +/* +** test_vminq_u16: +** umin v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_u16, uint16x8_t) + +/* +** test_vminq_s16: +** smin v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_s16, int16x8_t) + +/* +** test_vminq_f16: +** fmin v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_f16, float16x8_t) + +/* +** test_vminq_u32: +** umin v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_u32, uint32x4_t) + +/* +** test_vminq_s32: +** smin v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_s32, int32x4_t) + +/* +** test_vminq_f32: +** fmin v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_f32, float32x4_t) + +/* +** test_vminq_f64: +** fmin v0\.2d, (v0\.2d, v1\.2d|v1\.2d, v0\.2d) +** ret +*/ +TEST_UNIFORM_BINARY (vminq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vminnm.c b/gcc/testsuite/gcc.target/aarch64/neon/vminnm.c new file mode 100644 index 00000000000..316bba1a5a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vminnm.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vminnm_f16: +** fminnm v0\.4h, (v0\.4h, v1\.4h|v1\.4h, v0\.4h) +** ret +*/ +TEST_UNIFORM_BINARY (vminnm_f16, float16x4_t) + +/* +** test_vminnm_f32: +** fminnm v0\.2s, (v0\.2s, v1\.2s|v1\.2s, v0\.2s) +** ret +*/ +TEST_UNIFORM_BINARY (vminnm_f32, float32x2_t) + +/* +** test_vminnm_f64: +** fminnm d0, (d0, d1|d1, d0) +** ret +*/ +TEST_UNIFORM_BINARY (vminnm_f64, float64x1_t) + +/* +** test_vminnmq_f16: +** fminnm v0\.8h, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ +TEST_UNIFORM_BINARY (vminnmq_f16, float16x8_t) + +/* +** test_vminnmq_f32: +** fminnm v0\.4s, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ +TEST_UNIFORM_BINARY (vminnmq_f32, float32x4_t) + +/* +** test_vminnmq_f64: +** fminnm v0\.2d, (v0\.2d, v1\.2d|v1\.2d, v0\.2d) +** ret +*/ +TEST_UNIFORM_BINARY (vminnmq_f64, float64x2_t) diff --git a/gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c index 3ec0a52b522..4bbd81f5a0d 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c @@ -21,9 +21,7 @@ test_abs_max_f16 (float16x4_t a, float16x4_t b) /* ** test_abs_maxnm_f16: -** fabs v1.4h, v1.4h -** fabs v0.4h, v0.4h -** fmaxnm v0.4h, v0.4h, v1.4h +** famax v0.4h, (v0.4h, v1.4h|v1.4h, v0.4h) ** ret */ float16x4_t @@ -47,9 +45,7 @@ test_abs_maxq_f16 (float16x8_t a, float16x8_t b) /* ** test_abs_maxnmq_f16: -** fabs v1.8h, v1.8h -** fabs v0.8h, v0.8h -** fmaxnm v0.8h, v0.8h, v1.8h +** famax v0.8h, (v0.8h, v1.8h|v1.8h, v0.8h) ** ret */ float16x8_t @@ -73,9 +69,7 @@ test_abs_max_f32 (float32x2_t a, float32x2_t b) /* ** test_abs_maxnm_f32: -** fabs v1.2s, v1.2s -** fabs v0.2s, v0.2s -** fmaxnm v0.2s, v0.2s, v1.2s +** famax v0.2s, (v0.2s, v1.2s|v1.2s, v0.2s) ** ret */ float32x2_t @@ -99,9 +93,7 @@ test_abs_maxq_f32 (float32x4_t a, float32x4_t b) /* ** test_abs_maxnmq_f32: -** fabs v1.4s, v1.4s -** fabs v0.4s, v0.4s -** fmaxnm v0.4s, v0.4s, v1.4s +** famax v0.4s, (v0.4s, v1.4s|v1.4s, v0.4s) ** ret */ float32x4_t @@ -125,9 +117,7 @@ test_abs_maxq_f64 (float64x2_t a, float64x2_t b) /* ** test_abs_maxnmq_f64: -** fabs v1.2d, v1.2d -** fabs v0.2d, v0.2d -** fmaxnm v0.2d, v0.2d, v1.2d +** famax v0.2d, (v0.2d, v1.2d|v1.2d, v0.2d) ** ret */ float64x2_t @@ -151,9 +141,7 @@ test_abs_min_f16 (float16x4_t a, float16x4_t b) /* ** test_abs_minnm_f16: -** fabs v1.4h, v1.4h -** fabs v0.4h, v0.4h -** fminnm v0.4h, v0.4h, v1.4h +** famin v0.4h, (v0.4h, v1.4h|v1.4h, v0.4h) ** ret */ float16x4_t @@ -177,9 +165,7 @@ test_abs_minq_f16 (float16x8_t a, float16x8_t b) /* ** test_abs_minnmq_f16: -** fabs v1.8h, v1.8h -** fabs v0.8h, v0.8h -** fminnm v0.8h, v0.8h, v1.8h +** famin v0.8h, (v0.8h, v1.8h|v1.8h, v0.8h) ** ret */ float16x8_t @@ -203,9 +189,7 @@ test_abs_min_f32 (float32x2_t a, float32x2_t b) /* ** test_abs_minnm_f32: -** fabs v1.2s, v1.2s -** fabs v0.2s, v0.2s -** fminnm v0.2s, v0.2s, v1.2s +** famin v0.2s, (v0.2s, v1.2s|v1.2s, v0.2s) ** ret */ float32x2_t @@ -229,9 +213,7 @@ test_abs_minq_f32 (float32x4_t a, float32x4_t b) /* ** test_abs_minnmq_f32: -** fabs v1.4s, v1.4s -** fabs v0.4s, v0.4s -** fminnm v0.4s, v0.4s, v1.4s +** famin v0.4s, (v0.4s, v1.4s|v1.4s, v0.4s) ** ret */ float32x4_t @@ -255,9 +237,7 @@ test_abs_minq_f64 (float64x2_t a, float64x2_t b) /* ** test_abs_minnmq_f64: -** fabs v1.2d, v1.2d -** fabs v0.2d, v0.2d -** fminnm v0.2d, v0.2d, v1.2d +** famin v0.2d, (v0.2d, v1.2d|v1.2d, v0.2d) ** ret */ float64x2_t