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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1430eb4854csm726433c88.15.2026.09.01.12.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 12:58:35 -0700 (PDT) From: Sumit Singh Dhami To: trini@konsulko.com, ilias.apalodimas@linaro.org, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, aswin.murugan@oss.qualcomm.com, balaji.selvanathan@oss.qualcomm.com, sumit.dhami@oss.qualcomm.com, u-boot@lists.u-boot-project.org, u-boot-qcom@groups.io Subject: [PATCH v1 1/3] sysreset: qcom-pshold: Configure PON reset type Date: Wed, 2 Sep 2026 01:27:46 +0530 Message-ID: <20260901195748.1192630-2-sumit.dhami@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260901195748.1192630-1-sumit.dhami@oss.qualcomm.com> References: <20260901195748.1192630-1-sumit.dhami@oss.qualcomm.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=F8JnsKhN c=1 sm=1 tr=0 ts=6a972e6c cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=LW9D_-4wNyH7aS83yREA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: q0THMptFdP4niTTY5cMbReYRtEKUPn1A X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDE3NSBTYWx0ZWRfX/m7PXW4txUbl 03YiG06T6FCZjdq3/8YPe4d6LedY7Buk7CznREbHRj3wxh5PVDct6Pf2XJJ8n3Nl5uw929H4Zcc WvXxQNfD905af0rSbaSQKbZCN9H1sgU= X-Proofpoint-ORIG-GUID: q0THMptFdP4niTTY5cMbReYRtEKUPn1A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDE3NSBTYWx0ZWRfX6lXzP7TMMcVL HukqmoVMeG+xyZg+ndlDwFl6Hw0XRamc0mqgv0qxUq58xWtEpab7aAigiVx2lUqcT8rk5hCR2Hb FP2m/tl7zhhJIlaxRNRKe9nioVGAMrJN6t8j61NQ6niav7AwdixtjoozsU+24Mssy4IpSK8YxWp P8M2d6Sf0vsC0O07jmSZ4KilIP2Fi7EdB6ZzGEt8QkHGWEOVYOWbb7+UXwvBMjK4/aSVRkz71Mv slz3hjIj2HPvvi0ZQRxp+ofYRChI4TXBAKn/TqpRkVZMd7oij0BV8DuF5CB/OelRp1NIbKvkBDS mwipE45i4wY8ry4uupZd4tOy9Dgfo7uOystv7HbUCExwJ/vIoXPB7NCL0t4b+CMFqlcbVkxwEVh t2zuuUMjtPOhmkSE84YduUdn8szpcU/aJnzqb0fV4GlTPzAfNrgTuKlgSonDQSSziOSpuhK6rDc /cOaF2SOs4pNsgPVWCg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_05,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 clxscore=1011 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010175 X-Mailman-Approved-At: Wed, 02 Sep 2026 04:20:49 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Configure the PMIC PON PBS reset type before deasserting MPM PS_HOLD. The PON PBS reset sequence requires PS_HOLD_RESET_CTL2 to be cleared, the requested reset type to be written to PS_HOLD_SW_CTL, and PS_HOLD_RESET_CTL2 to be enabled again before deasserting MPM_PS_HOLD. Signed-off-by: Sumit Singh Dhami --- drivers/sysreset/sysreset_qcom-pshold.c | 137 ++++++++++++++++++++++-- 1 file changed, 130 insertions(+), 7 deletions(-) diff --git a/drivers/sysreset/sysreset_qcom-pshold.c b/drivers/sysreset/sysreset_qcom-pshold.c index 45290478536..de7c0b388aa 100644 --- a/drivers/sysreset/sysreset_qcom-pshold.c +++ b/drivers/sysreset/sysreset_qcom-pshold.c @@ -13,15 +13,94 @@ #include #include #include +#include + +#define PON_PBS_RESET_TYPE_WARM 0x01 +#define PON_PBS_RESET_TYPE_HARD 0x07 + +/* + * Reset State of PON_PBS_PS_HOLD_RESET_CTL2 register + */ +#define PON_PBS_PS_HOLD_RESET_CTL2_S2_RESET_EN_BMSK 0x80 struct qcom_pshold_priv { phys_addr_t base; + + struct udevice *pmic; + u32 pbs_base; + bool have_pon; + + u32 pon_pbs_pshold_sw_ctl_offset; + u32 pon_pbs_pshold_reset_ctl2_offset; }; +static int qcom_pshold_pon_cfg(struct qcom_pshold_priv *priv, u8 reset_type) +{ + int ret; + + ret = pmic_reg_write(priv->pmic, + priv->pbs_base + + priv->pon_pbs_pshold_reset_ctl2_offset, + 0x00); + if (ret) + return ret; + + udelay(100); + + ret = pmic_reg_write(priv->pmic, + priv->pbs_base + priv->pon_pbs_pshold_sw_ctl_offset, + reset_type); + if (ret) + return ret; + + udelay(300); + + ret = pmic_reg_write(priv->pmic, + priv->pbs_base + priv->pon_pbs_pshold_reset_ctl2_offset, + PON_PBS_PS_HOLD_RESET_CTL2_S2_RESET_EN_BMSK); + if (ret) + return ret; + + udelay(100); + + return 0; +} + +static int qcom_pshold_read_pon_offset(struct udevice *dev, struct qcom_pshold_priv *priv) +{ + int ret; + + ret = dev_read_u32(dev, + "qcom,pbs-pshold-sw-ctl", + &priv->pon_pbs_pshold_sw_ctl_offset); + if (ret) + return ret; + + ret = dev_read_u32(dev, + "qcom,pbs-pshold-reset-ctl2", + &priv->pon_pbs_pshold_reset_ctl2_offset); + if (ret) + return ret; + + return 0; +} + static int qcom_pshold_request(struct udevice *dev, enum sysreset_t type) { struct qcom_pshold_priv *priv = dev_get_priv(dev); + if (priv->have_pon) { + u8 reset_type = (type == SYSRESET_WARM) ? + PON_PBS_RESET_TYPE_WARM : + PON_PBS_RESET_TYPE_HARD; + int ret; + + ret = qcom_pshold_pon_cfg(priv, reset_type); + if (ret) + debug("%s: failed to configure PON reset type: %d\n", + dev->name, ret); + } + writel(0, priv->base); mdelay(10000); @@ -35,9 +114,53 @@ static struct sysreset_ops qcom_pshold_ops = { static int qcom_pshold_probe(struct udevice *dev) { struct qcom_pshold_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + ofnode pmic_node; + int index, ret; + + priv->have_pon = false; priv->base = dev_read_addr(dev); - return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = dev_read_phandle_with_args(dev, "qcom,pon", NULL, 0, 0, &args); + if (ret) + return 0; + + index = ofnode_stringlist_search(args.node, "reg-names", "pbs"); + if (index < 0) { + debug("%s: referenced PON node has no 'pbs' reg\n", dev->name); + return 0; + } + + ret = ofnode_read_u32_index(args.node, "reg", index, &priv->pbs_base); + if (ret) { + debug("%s: failed to read PON 'pbs' reg: %d\n", dev->name, ret); + return 0; + } + + ret = qcom_pshold_read_pon_offset(dev, priv); + if (ret) { + debug("%s: failed to read PON offset configs: %d\n", dev->name, ret); + return 0; + } + + pmic_node = ofnode_get_parent(args.node); + if (!ofnode_valid(pmic_node)) { + debug("%s: failed to get PON's parent PMIC node\n", dev->name); + return 0; + } + + ret = uclass_get_device_by_ofnode(UCLASS_PMIC, pmic_node, &priv->pmic); + if (ret) { + debug("%s: failed to get PMIC device: %d\n", dev->name, ret); + return 0; + } + + priv->have_pon = true; + + return 0; } static const struct udevice_id qcom_pshold_ids[] = { @@ -46,10 +169,10 @@ static const struct udevice_id qcom_pshold_ids[] = { }; U_BOOT_DRIVER(qcom_pshold) = { - .name = "qcom_pshold", - .id = UCLASS_SYSRESET, - .of_match = qcom_pshold_ids, - .probe = qcom_pshold_probe, - .priv_auto = sizeof(struct qcom_pshold_priv), - .ops = &qcom_pshold_ops, + .name = "qcom_pshold", + .id = UCLASS_SYSRESET, + .of_match = qcom_pshold_ids, + .probe = qcom_pshold_probe, + .priv_auto = sizeof(struct qcom_pshold_priv), + .ops = &qcom_pshold_ops, }; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1430eb4854csm726433c88.15.2026.09.01.12.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 12:58:38 -0700 (PDT) From: Sumit Singh Dhami To: trini@konsulko.com, ilias.apalodimas@linaro.org, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, aswin.murugan@oss.qualcomm.com, balaji.selvanathan@oss.qualcomm.com, sumit.dhami@oss.qualcomm.com, u-boot@lists.u-boot-project.org, u-boot-qcom@groups.io Subject: [PATCH v1 2/3] arm: dts: qcom: Configure Lemans PS_HOLD reset Date: Wed, 2 Sep 2026 01:27:47 +0530 Message-ID: <20260901195748.1192630-3-sumit.dhami@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260901195748.1192630-1-sumit.dhami@oss.qualcomm.com> References: <20260901195748.1192630-1-sumit.dhami@oss.qualcomm.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=T968ifKQ c=1 sm=1 tr=0 ts=6a972e70 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=UJPxi1aDyaN00a8EuTAA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: o5nCaBKQROKQCsSS82b19kAfWm_iFU-A X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDE3NSBTYWx0ZWRfX64miUgAIkDDL 40fsqVelKHqgSH7ZQnrRXZ/fJpZBrTGjLM48roO+AqoTQb3go/gnY9MWu2wmxb8u1xAI6chBGau w/7MRWQ7VEM9JFrlGvclz9HOzBt1hFo= X-Proofpoint-GUID: o5nCaBKQROKQCsSS82b19kAfWm_iFU-A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDE3NSBTYWx0ZWRfX/heG2Yfz1/fJ 5R1cWDXpW6UfZue4M4ood/3ekrC3CBuwCe0P4ZFVxHICQvh/zsbmAIUzQBgTV7HeSu1Y3DVaGqn jlXWzzRru92P6gHt3/xL+fbrudly/H4vu6vHhAL86vdmvJT7KnGb+88e8VhzcPIAURl3iNQxLDO KZ6R4HSuzVUlfSPa2I4loPjtxy1hrumpfdxMiO4lYbJpiExzupPeYzJ4qvfN8JevrRAMtTpk3YN Ob55+vgp7hOAm+JD8V9/sVMDjVxIeCLBQyTF5He04hrRGYnFfLyhWaWr4/rDHyAya3j59jYZLg2 kQmlx2u4EJm2BVazjHPSG+nnbZs3iW59fupru0IohE0LQn+dWiUJTdVR7nL34771K5HKyb228qm CM0MDDP616msYWDzfkbRPFcS+60dh+82bjaMbH1JTfOvRLmxqZvnxdP7UompIwBRObq/tSe7Tsw nuQ4uTBpdIMEy2MwhLA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_05,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010175 X-Mailman-Approved-At: Wed, 02 Sep 2026 04:20:49 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Add the Qualcomm PS_HOLD sysreset node for the Lemans EVK. Link the reset driver to the PMIC PON peripheral and provide the PBS PS_HOLD control register offsets required to configure warm and hard resets before deasserting MPM_PS_HOLD. Signed-off-by: Sumit Singh Dhami --- arch/arm/dts/lemans-evk-u-boot.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/lemans-evk-u-boot.dtsi b/arch/arm/dts/lemans-evk-u-boot.dtsi index fd4eaa2fec8..0e676bf4b55 100644 --- a/arch/arm/dts/lemans-evk-u-boot.dtsi +++ b/arch/arm/dts/lemans-evk-u-boot.dtsi @@ -64,3 +64,15 @@ mode-edl = <0x80000000 0x00000001>; }; }; + +&soc { + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0 0x0c264000 0x0 0x4>; + qcom,pon = <&pmm8654au_0_pon>; + qcom,pbs-pshold-sw-ctl = <0x52>; + qcom,pbs-pshold-reset-ctl2 = <0x53>; + + bootph-all; + }; +}; From patchwork Tue Sep 1 19:57:48 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Singh Dhami X-Patchwork-Id: 2296322 X-Patchwork-Delegate: casey.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1430eb4854csm726433c88.15.2026.09.01.12.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 12:58:42 -0700 (PDT) From: Sumit Singh Dhami To: trini@konsulko.com, ilias.apalodimas@linaro.org, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, aswin.murugan@oss.qualcomm.com, balaji.selvanathan@oss.qualcomm.com, sumit.dhami@oss.qualcomm.com, u-boot@lists.u-boot-project.org, u-boot-qcom@groups.io Subject: [PATCH v1 3/3] configs: disable CMD_POWEROFF in snagboot config Date: Wed, 2 Sep 2026 01:27:48 +0530 Message-ID: <20260901195748.1192630-4-sumit.dhami@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260901195748.1192630-1-sumit.dhami@oss.qualcomm.com> References: <20260901195748.1192630-1-sumit.dhami@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDE3NSBTYWx0ZWRfX12jYTN9ffq8i GpyFxPagLSpORL2R2kfrVZM7oxOuyUvLUJsU75MAXQFGLY2Agf/L4zWvIri0CMhrIuKOW6pn7KB S0Ol6pMQN/k71OVPkOfh0gWR55pJvGQa+DhpSPmreLtuR/xU+Wq8wdp3XaXjvDmSc3/ORK/lGoQ yjPCNLzMQWdHL3bFJ/Npkb54YUXFpwIHKqvtOQdzyNzuGlr8YzNoIhxoniRu0fCn6yGHFDhNqCA uS53dxpNq2OfMAvxOT8JnSdqR9iwnoY5jStCpjFy/2umtxi2WTrJdRPoOd9jGE9sRgU58sXH47h KP9LDJi+wV3dKAK2qfWBQHoUP+xplItaczY+reR6h5U+d8JpyLvNqeiNphewT1sXtT+IVZa5mMi mNq1b5bOF5D95rhTkJ7vub3L2C5dSM+yj/u0I0UUEXO0aZJgb/zMjDo0Uqe1vgItnApH0VgwLzZ YRTgYwKhk16vpaAqFKQ== X-Authority-Analysis: v=2.4 cv=L6ItheT8 c=1 sm=1 tr=0 ts=6a972e74 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=eDiLCjgS2gUGnAqvYTQA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDE3NSBTYWx0ZWRfX+vwkkkrZj/AK vfXbXfjkKVEaUpi2jnyDJJ+rFpHD6kP5jVmfE2S0+uWd+3mHi7dpDURGYv6xWtb7fsKG+8gY6ME LQFVg6FXGlwLHfb0KifKinve3dH7oxw= X-Proofpoint-ORIG-GUID: i6mECGzQuQj2_orDzWqFlETHGFpHdvEG X-Proofpoint-GUID: i6mECGzQuQj2_orDzWqFlETHGFpHdvEG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_05,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010175 X-Mailman-Approved-At: Wed, 02 Sep 2026 04:20:49 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org CMD_POWEROFF requires do_poweroff(), normally provided by psci.c, but PSCI_RESET is disabled in snagboot mode, causing a link failure. Poweroff isn't needed for snagboot recovery, so disable it. Signed-off-by: Sumit Singh Dhami --- configs/qcom-snagboot.config | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom-snagboot.config b/configs/qcom-snagboot.config index d19ad453029..579bcc7732d 100644 --- a/configs/qcom-snagboot.config +++ b/configs/qcom-snagboot.config @@ -8,6 +8,7 @@ CONFIG_QCOM_SNAGBOOT_MODE=y # CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR is not set # CONFIG_IOMMU is not set # CONFIG_REBOOT_MODE_ENV_UPDATE is not set +# CONFIG_CMD_POWEROFF is not set # Use default environment instead of loading from storage # This ensures snagboot mode works even with corrupted environment