From patchwork Tue Sep 1 23:34:54 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 2296277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QX/ooPWK; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZMhD0jxmz1y1C for ; Wed, 02 Sep 2026 09:36:44 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3541E4BA79A9 for ; Tue, 1 Sep 2026 23:36:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3541E4BA79A9 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QX/ooPWK X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by sourceware.org (Postfix) with ESMTPS id 80B7C4BA2E2B for ; Tue, 1 Sep 2026 23:35:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 80B7C4BA2E2B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 80B7C4BA2E2B Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305755; cv=none; b=okww0tfOA/zVuBlC6TTFWlMgQd/awb9faJBHyCvTyAKZG4R9ex7DhWPe6cpxGfmrH8Io2NuEBmfy5bJcHWxtJ+GzKboYwRNDwYIj3bRvOk43XqAe0oKoe/pJb2+Lz4fgyYIqO+cf3/zJa5FlgiJQUfyMPg4QENwFaDvrYaxIZRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305755; c=relaxed/simple; bh=2oumOZT0NYTIffNLr9WWAOowyfHN7tFT9Xecpauo+/c=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=lnE/as00x2UzNM6RZ1u+SjZA1AJgquF7qXdNBpcj/A0UYtEWYgv6yHj5qjwkgrhgMbqZbLckAQpZ0Lb/k5xoaCFCY9NsIllzgwA9qT1HRb/wMqYeOe20vBefBWAs18JDJ/ZhM3NYfF1EwWGp4ANWckg+DEv/kkOjf3Z0KiPZ+MA= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QX/ooPWK DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 80B7C4BA2E2B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788305755; x=1819841755; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2oumOZT0NYTIffNLr9WWAOowyfHN7tFT9Xecpauo+/c=; b=QX/ooPWK1ajsskoKHAqwxQNvl6q+gokY9Zb8+ODvRmu+A+dzLuukc6VD eK4Y4uHhTLMnl9eP8VCyBkXIKa1mr7HHgdU/oqKHekeAyMNvhvHqgZ5na 2x1w1vGWokR3Ms4ULglV4mwFo0UHjwWRzvEIF8AZgLFzzyfRiFwLqsiGc 0nL6ZYiPj+QmIJAzRxoXagHFyodZgDdp827t00r05mk1pH2DOiZPbzimg b7Wwaz6y4LGbHdycbqTf1wJp1DxYKAD6IX47GNeGDoAybh7pVByZoTJ9d ks6BEVDPwemOMgr0V+8Nw4YxDUxxQubmQ273UvI9n5eTxg14jIrmgL3Vz A==; X-CSE-ConnectionGUID: dI0THXeZSYO+94dFTgTFiw== X-CSE-MsgGUID: mD4D9z5vRgaKyNDWznQB+Q== X-IronPort-AV: E=McAfee;i="6800,10657,11893"; a="76305049" X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="76305049" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2026 16:35:54 -0700 X-CSE-ConnectionGUID: 5BmIBYHmQNm3yF4+hydK9A== X-CSE-MsgGUID: dT1cpWqqRSmnI7c5H+P5gw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="271197192" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa004.fm.intel.com with ESMTP; 01 Sep 2026 16:35:52 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 1/3] RISC-V: Allow RVV register overlap for vwmaccus.vx Date: Wed, 2 Sep 2026 07:34:54 +0800 Message-ID: <20260901233549.3563543-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901233549.3563543-1-pan2.li@intel.com> References: <20260901233549.3563543-1-pan2.li@intel.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Like vwmacc[u].vx and vwmaccsu.vx, allow the rvv register overlap for the dual widen ternary vx insn vwmaccus.vx. After that, all the widen ternary vx insns are able to overlap, thus remove the xfail of the related test cases. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-37.c: Remove xfail. Signed-off-by: Pan Li --- gcc/config/riscv/vector.md | 18 +++++++++--------- .../gcc.target/riscv/rvv/base/pr112431-37.c | 6 +++--- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index af8a7294cc9..bbdbe8eddd1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6169,24 +6169,24 @@ (define_insn "@pred_widen_mul_plussu_scalar" (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plusus_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vd") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rvl") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" "Wc1, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (zero_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "register_operand" " r, r"))) (sign_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) + (match_operand: 4 "register_operand" "Wvr,Wvr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0")) (match_dup 2)))] "TARGET_VECTOR" "vwmaccus.vx\t%0,%3,%4%p1" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c index 66e81ea905a..6337ff875fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c @@ -97,7 +97,7 @@ foo9 (void *in, void *out) } /* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {vmv8r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ /* { dg-final { scan-assembler-not {csrr} } } */ From patchwork Tue Sep 1 23:34:55 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 2296276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=OU7SUy0U; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZMhC2JHyz1xvf for ; Wed, 02 Sep 2026 09:36:43 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4C45C4BA9001 for ; Tue, 1 Sep 2026 23:36:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4C45C4BA9001 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=OU7SUy0U X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by sourceware.org (Postfix) with ESMTPS id 06B204BA2E2C for ; Tue, 1 Sep 2026 23:35:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 06B204BA2E2C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 06B204BA2E2C Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305759; cv=none; b=AUduSgciiwPe5iukrjHJVP43aZneebr9882jF9pzgFAFFVgYErB1W0q+R0ZQDY4OHfNUC1vGUtkjnidUGPt5GbCks5yMu7HnldNBWFUAgdKjQOLkTlE2+seA7IEnNjcMe1m1VMjJrNWw5iOg82c1Vp+wHAosC6m3wy2IBkDzoiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305759; c=relaxed/simple; bh=CcxEi16K6NhIYTV/Th2Qxw3tDo2RwNK0PFlm3GKYx5A=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Pd7k5Q/w/4QfqGcg03ZoUVuOVAlcc8kbvTdUMr33Hui+xNmW0XZopNX/UEabtwMnPx4+thn+OYeW8arueee15ngSwFkU+u4Gkh1fpReQYICLQoyaOEDMgwPg/I2aDS/3MD8BlYwKd7QrpyjLGdT18i28UkkPHZrgDkrk7CEMfbU= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=OU7SUy0U DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 06B204BA2E2C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788305759; x=1819841759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CcxEi16K6NhIYTV/Th2Qxw3tDo2RwNK0PFlm3GKYx5A=; b=OU7SUy0UiW1pw5XMKx60gz/gwLxsQvG5yLme0WWrCG9G+2xDlcAK29Ga YotrEdca8KsNAGw57J+aVr6KgAWNBI8+WoxmgB6eubTtsQHkxY80ZgiKA 8wk7na3yDhDqLz++40G3EVTc26lhinD7fmboXcQrm1PaL1nUFExW12gLa upCiFnJvyZRqZxtcHRLVNy1ebhUFeZVCHoEoMNIiDy4DUkEZ3nTKFYghq 4by6OudmYJoPjKT+V7SBA4iBJniLsndDrRlf1r6KgS+ZFI+24zEHNXaaz /3Fq6ggnPA+Ex1YnU9udI3VSnCY2IyTVDgHm1aSJC2VDptxywS63ntT1I Q==; X-CSE-ConnectionGUID: i2SHugifSgK14wTwXpiH1w== X-CSE-MsgGUID: Y5Fncpq4QOqhA3F9faIV5w== X-IronPort-AV: E=McAfee;i="6800,10657,11893"; a="76305052" X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="76305052" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2026 16:35:58 -0700 X-CSE-ConnectionGUID: O9Zg4e8+R+26EbVgb/NbqA== X-CSE-MsgGUID: RjprAApzROqo7bhPRqoF4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="271197203" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa004.fm.intel.com with ESMTP; 01 Sep 2026 16:35:55 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 2/3] RISC-V: Add test cases for vwmaccus.vx reg overlap Date: Wed, 2 Sep 2026 07:34:55 +0800 Message-ID: <20260901233549.3563543-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901233549.3563543-1-pan2.li@intel.com> References: <20260901233549.3563543-1-pan2.li@intel.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf8.c: New test. Signed-off-by: Pan Li --- .../group_overlap/vwmaccus_vx-i16-m1.c | 58 +++++++++++++++++++ .../group_overlap/vwmaccus_vx-i16-m2.c | 50 ++++++++++++++++ .../group_overlap/vwmaccus_vx-i16-m4.c | 46 +++++++++++++++ .../group_overlap/vwmaccus_vx-i16-mf2.c | 21 +++++++ .../group_overlap/vwmaccus_vx-i16-mf4.c | 21 +++++++ .../group_overlap/vwmaccus_vx-i32-m1.c | 58 +++++++++++++++++++ .../group_overlap/vwmaccus_vx-i32-m2.c | 50 ++++++++++++++++ .../group_overlap/vwmaccus_vx-i32-m4.c | 46 +++++++++++++++ .../group_overlap/vwmaccus_vx-i32-mf2.c | 21 +++++++ .../autovec/group_overlap/vwmaccus_vx-i8-m1.c | 58 +++++++++++++++++++ .../autovec/group_overlap/vwmaccus_vx-i8-m2.c | 50 ++++++++++++++++ .../autovec/group_overlap/vwmaccus_vx-i8-m4.c | 46 +++++++++++++++ .../group_overlap/vwmaccus_vx-i8-mf2.c | 21 +++++++ .../group_overlap/vwmaccus_vx-i8-mf4.c | 21 +++++++ .../group_overlap/vwmaccus_vx-i8-mf8.c | 21 +++++++ 15 files changed, 588 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m1.c new file mode 100644 index 00000000000..f3c542f7862 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e16m1, + vint16m1_t, + vint32m2_t, + uint16_t, + __riscv_vle16_v_i16m1, + __riscv_vle32_v_i32m2, + __riscv_vwmaccus_vx_i32m2, + __riscv_vse32_v_i32m2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e16m1, + vint16m1_t, + vint32m2_t, + vint16m2_t, + uint16_t, + __riscv_vle32_v_i32m2, + __riscv_vreinterpret_v_i32m2_i16m2, + __riscv_vget_v_i16m2_i16m1, + __riscv_vwmaccus_vx_i32m2, + __riscv_vse32_v_i32m2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v6,s0,v27([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,s0,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v14,s0,v31([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v12,s0,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v2,s0,v25([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v26,s0,v24([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v10,s0,v29([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v30,s0,v23([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,s0,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,s0,v28([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v26,s0,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,s0,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v22,s0,v21([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,s0,v18([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v20,s0,v19([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v18,s0,v1([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v5([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m2.c new file mode 100644 index 00000000000..76be9321813 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e16m2, + vint16m2_t, + vint32m4_t, + uint16_t, + __riscv_vle16_v_i16m2, + __riscv_vle32_v_i32m4, + __riscv_vwmaccus_vx_i32m4, + __riscv_vse32_v_i32m4, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e16m2, + vint16m2_t, + vint32m4_t, + vint16m4_t, + uint16_t, + __riscv_vle32_v_i32m4, + __riscv_vreinterpret_v_i32m4_i16m4, + __riscv_vget_v_i16m4_i16m2, + __riscv_vwmaccus_vx_i32m4, + __riscv_vse32_v_i32m4, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v12,a2,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v28([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,a2,v24([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,a2,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,a2,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v20,a2,v2([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v10([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m4.c new file mode 100644 index 00000000000..0598c58ac50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m4.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e16m4, + vint16m4_t, + vint32m8_t, + uint16_t, + __riscv_vle16_v_i16m4, + __riscv_vle32_v_i32m8, + __riscv_vwmaccus_vx_i32m8, + __riscv_vse32_v_i32m8, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e16m4, + vint16m4_t, + vint32m8_t, + vint16m8_t, + uint16_t, + __riscv_vle32_v_i32m8, + __riscv_vreinterpret_v_i32m8_i16m8, + __riscv_vget_v_i16m8_i16m4, + __riscv_vwmaccus_vx_i32m8, + __riscv_vse32_v_i32m8, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v4([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf2.c new file mode 100644 index 00000000000..8432b660cb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e16m1, + vint16mf2_t, + vint32m1_t, + uint16_t, + __riscv_vle16_v_i16mf2, + __riscv_vle32_v_i32m1, + __riscv_vwmaccus_vx_i32m1, + __riscv_vse32_v_i32m1, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx} 16 } } */ +/* { dg-final { scan-assembler-not {vwmaccus\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf4.c new file mode 100644 index 00000000000..8f306e4fc89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e16m1, + vint16mf4_t, + vint32mf2_t, + uint16_t, + __riscv_vle16_v_i16mf4, + __riscv_vle32_v_i32mf2, + __riscv_vwmaccus_vx_i32mf2, + __riscv_vse32_v_i32mf2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx} 16 } } */ +/* { dg-final { scan-assembler-not {vwmaccus\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m1.c new file mode 100644 index 00000000000..0202db0e622 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e32m1, + vint32m1_t, + vint64m2_t, + uint32_t, + __riscv_vle32_v_i32m1, + __riscv_vle64_v_i64m2, + __riscv_vwmaccus_vx_i64m2, + __riscv_vse64_v_i64m2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e32m1, + vint32m1_t, + vint64m2_t, + vint32m2_t, + uint32_t, + __riscv_vle64_v_i64m2, + __riscv_vreinterpret_v_i64m2_i32m2, + __riscv_vget_v_i32m2_i32m1, + __riscv_vwmaccus_vx_i64m2, + __riscv_vse64_v_i64m2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v6,s0,v27([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,s0,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v14,s0,v31([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v12,s0,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v2,s0,v25([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v26,s0,v24([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v10,s0,v29([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v30,s0,v23([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,s0,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,s0,v28([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v26,s0,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,s0,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v22,s0,v21([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,s0,v18([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v20,s0,v19([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v18,s0,v1([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v5([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m2.c new file mode 100644 index 00000000000..4269b027a03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e32m2, + vint32m2_t, + vint64m4_t, + uint32_t, + __riscv_vle32_v_i32m2, + __riscv_vle64_v_i64m4, + __riscv_vwmaccus_vx_i64m4, + __riscv_vse64_v_i64m4, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e32m2, + vint32m2_t, + vint64m4_t, + vint32m4_t, + uint32_t, + __riscv_vle64_v_i64m4, + __riscv_vreinterpret_v_i64m4_i32m4, + __riscv_vget_v_i32m4_i32m2, + __riscv_vwmaccus_vx_i64m4, + __riscv_vse64_v_i64m4, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v12,a2,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v28([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,a2,v24([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,a2,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,a2,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v20,a2,v2([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v10([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m4.c new file mode 100644 index 00000000000..3452089ab08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m4.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e32m4, + vint32m4_t, + vint64m8_t, + uint32_t, + __riscv_vle32_v_i32m4, + __riscv_vle64_v_i64m8, + __riscv_vwmaccus_vx_i64m8, + __riscv_vse64_v_i64m8, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e32m4, + vint32m4_t, + vint64m8_t, + vint32m8_t, + uint32_t, + __riscv_vle64_v_i64m8, + __riscv_vreinterpret_v_i64m8_i32m8, + __riscv_vget_v_i32m8_i32m4, + __riscv_vwmaccus_vx_i64m8, + __riscv_vse64_v_i64m8, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v4([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-mf2.c new file mode 100644 index 00000000000..584557c7016 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e32m1, + vint32mf2_t, + vint64m1_t, + uint32_t, + __riscv_vle32_v_i32mf2, + __riscv_vle64_v_i64m1, + __riscv_vwmaccus_vx_i64m1, + __riscv_vse64_v_i64m1, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx} 16 } } */ +/* { dg-final { scan-assembler-not {vwmaccus\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m1.c new file mode 100644 index 00000000000..bffc1c62bd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e8m1, + vint8m1_t, + vint16m2_t, + uint8_t, + __riscv_vle8_v_i8m1, + __riscv_vle16_v_i16m2, + __riscv_vwmaccus_vx_i16m2, + __riscv_vse16_v_i16m2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e8m1, + vint8m1_t, + vint16m2_t, + vint8m2_t, + uint8_t, + __riscv_vle16_v_i16m2, + __riscv_vreinterpret_v_i16m2_i8m2, + __riscv_vget_v_i8m2_i8m1, + __riscv_vwmaccus_vx_i16m2, + __riscv_vse16_v_i16m2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v6,s0,v27([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,s0,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v14,s0,v31([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v12,s0,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v2,s0,v25([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v26,s0,v24([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v10,s0,v29([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v30,s0,v23([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,s0,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,s0,v28([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v26,s0,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,s0,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v22,s0,v21([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,s0,v18([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v20,s0,v19([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v18,s0,v1([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v5([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m2.c new file mode 100644 index 00000000000..e9d1dc07fa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e8m2, + vint8m2_t, + vint16m4_t, + uint8_t, + __riscv_vle8_v_i8m2, + __riscv_vle16_v_i16m4, + __riscv_vwmaccus_vx_i16m4, + __riscv_vse16_v_i16m4, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e8m2, + vint8m2_t, + vint16m4_t, + vint8m4_t, + uint8_t, + __riscv_vle16_v_i16m4, + __riscv_vreinterpret_v_i16m4_i8m4, + __riscv_vget_v_i8m4_i8m2, + __riscv_vwmaccus_vx_i16m4, + __riscv_vse16_v_i16m4, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v12,a2,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v28([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,a2,v24([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,a2,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v28,a2,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v20,a2,v2([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v10([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m4.c new file mode 100644 index 00000000000..c72725db0b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m4.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e8m4, + vint8m4_t, + vint16m8_t, + uint8_t, + __riscv_vle8_v_i8m4, + __riscv_vle16_v_i16m8, + __riscv_vwmaccus_vx_i16m8, + __riscv_vse16_v_i16m8, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4) + +DEF_GROUP_OVERLAP_TERNARY_5( + __riscv_vsetvlmax_e8m4, + vint8m4_t, + vint16m8_t, + vint8m8_t, + uint8_t, + __riscv_vle16_v_i16m8, + __riscv_vreinterpret_v_i16m8_i8m8, + __riscv_vget_v_i8m8_i8m4, + __riscv_vwmaccus_vx_i16m8, + __riscv_vse16_v_i16m8, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2) + +/* ternary_4: the accumulator occupies the whole destination register group and + is live when the narrowed source is read, so the source cannot be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v24,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v4([^0-9]|$)} 1 } } */ + +/* ternary_5: the narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the source would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v16,a2,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf2.c new file mode 100644 index 00000000000..72982bc6f72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e8m1, + vint8mf2_t, + vint16m1_t, + uint8_t, + __riscv_vle8_v_i8mf2, + __riscv_vle16_v_i16m1, + __riscv_vwmaccus_vx_i16m1, + __riscv_vse16_v_i16m1, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx} 16 } } */ +/* { dg-final { scan-assembler-not {vwmaccus\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf4.c new file mode 100644 index 00000000000..bc3aeffdf9f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e8m1, + vint8mf4_t, + vint16mf2_t, + uint8_t, + __riscv_vle8_v_i8mf4, + __riscv_vle16_v_i16mf2, + __riscv_vwmaccus_vx_i16mf2, + __riscv_vse16_v_i16mf2, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx} 16 } } */ +/* { dg-final { scan-assembler-not {vwmaccus\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf8.c new file mode 100644 index 00000000000..a4dfc322f01 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_4( + __riscv_vsetvlmax_e8m1, + vint8mf8_t, + vint16mf4_t, + uint8_t, + __riscv_vle8_v_i8mf8, + __riscv_vle16_v_i16mf4, + __riscv_vwmaccus_vx_i16mf4, + __riscv_vse16_v_i16mf4, + vwmaccus_vx, + LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx} 16 } } */ +/* { dg-final { scan-assembler-not {vwmaccus\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ From patchwork Tue Sep 1 23:34:56 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 2296275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Q0RNd5yj; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hZMgz580sz1xvf for ; Wed, 02 Sep 2026 09:36:30 +1000 (AEST) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3736F4BA79A0 for ; Tue, 1 Sep 2026 23:36:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3736F4BA79A0 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Q0RNd5yj X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by sourceware.org (Postfix) with ESMTPS id 5331F4BA7994 for ; Tue, 1 Sep 2026 23:36:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5331F4BA7994 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5331F4BA7994 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305761; cv=none; b=RiMH7OX+uJGaBAvk+TzeTblmcIh4MVOcv4lyQChXYhuc6FRxyQX/1is4aRzx5MdH77afuFIsz98DRqszaRj9UcrwScv7D27H+/vxx0L1HdLzRFTcZ+rEzcdEri/ZA/WCJXBRyWyrbq5UZFoBmR827+TFa0rScoeBIBtvZh6g8ps= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305761; c=relaxed/simple; bh=Lab2TU/g4/8VSTlA0glgh91x4cTGxhxnvVhGxikFeZ0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=iGTIM2OQztImQxCeBLExg64eGQNPK4fBuxWoduZJqc2pmTiwvmNo6KudAOyBPL+dZ1k9tQkbKl944d0QOk+TTAkyTwbTYQP8x957UXbVjJqgE/vli5BErU0pDc1C/+rlhdKA/y/K8rUz53HvtMQH0QfRZKpXxJB6lOA+adwZCj4= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Q0RNd5yj DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5331F4BA7994 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788305761; x=1819841761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lab2TU/g4/8VSTlA0glgh91x4cTGxhxnvVhGxikFeZ0=; b=Q0RNd5yjNOd1qH3f8PGyuU+oZOADf6LtbYmpceUmxh2vs7ZPFhm/Q0Vz C/edLu2lVH6uKVcQrSuO/wwbTrJCNkVodUPKeFQvtG+Xw/RYbVoHZVN+/ 7wJh2wALH0tAvo84fgQkSS6rlUUjUIBX0ShLQP59fIOZ6DRY+9k1kUUa6 J7AjFlow+xdwQpE9BluWQjTJ3j/co413yyYBhA7U6E+0lrj20BYE0bL8j KrmYJe/TYpdwjkKtqleHgvPt8cT6S+bB9m4EvZ6xEjdVJflVqmKl9ILAa OeuO/UVooiwv57aKiXV7Vn+CPsDjawtbyi8d0nG5p3gloKR2mBhcW6M9G A==; X-CSE-ConnectionGUID: 6ehj3czYSOiuNpvXQwCg8A== X-CSE-MsgGUID: 0s4DJmrVSQW89J7KBHzWZg== X-IronPort-AV: E=McAfee;i="6800,10657,11893"; a="76305057" X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="76305057" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2026 16:36:00 -0700 X-CSE-ConnectionGUID: fwXwO3XZQNWJAWGBlV/vug== X-CSE-MsgGUID: ZHQxZY8IQEG26xcAlVmL8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="271197210" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa004.fm.intel.com with ESMTP; 01 Sep 2026 16:35:58 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 3/3] RISC-V: Add more test cases for vwmaccus.vx Date: Wed, 2 Sep 2026 07:34:56 +0800 Message-ID: <20260901233549.3563543-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901233549.3563543-1-pan2.li@intel.com> References: <20260901233549.3563543-1-pan2.li@intel.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li For csrr not asm check when enable overlap enabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-57.c: New test. * gcc.target/riscv/rvv/base/pr112431-58.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-57.c | 62 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr112431-58.c | 62 +++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c new file mode 100644 index 00000000000..5c91a7b5f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n, uint8_t x) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v0, 1)); + v0 = __riscv_vwmaccus_vx_i16m4_tu (v0, x, v0_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v1, 1)); + v1 = __riscv_vwmaccus_vx_i16m4_tu (v1, x, v1_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v2, 1)); + v2 = __riscv_vwmaccus_vx_i16m4_tu (v2, x, v2_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v3, 1)); + v3 = __riscv_vwmaccus_vx_i16m4_tu (v3, x, v3_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v4, 1)); + v4 = __riscv_vwmaccus_vx_i16m4_tu (v4, x, v4_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v5, 1)); + v5 = __riscv_vwmaccus_vx_i16m4_tu (v5, x, v5_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v6_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v6, 1)); + v6 = __riscv_vwmaccus_vx_i16m4_tu (v6, x, v6_n, 4); + asm volatile("nop" ::: "memory"); + vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100; + vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100; + } +} + +/* The narrowed signed source is the highest-numbered half of the signed + accumulator, thus it overlaps the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c new file mode 100644 index 00000000000..a6da2bc4009 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n, uint16_t x) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint32m4_t v0 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v0_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v0, 1)); + v0 = __riscv_vwmaccus_vx_i32m4_tu (v0, x, v0_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v1 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v1_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v1, 1)); + v1 = __riscv_vwmaccus_vx_i32m4_tu (v1, x, v1_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v2 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v2_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v2, 1)); + v2 = __riscv_vwmaccus_vx_i32m4_tu (v2, x, v2_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v3 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v3_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v3, 1)); + v3 = __riscv_vwmaccus_vx_i32m4_tu (v3, x, v3_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v4 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v4_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v4, 1)); + v4 = __riscv_vwmaccus_vx_i32m4_tu (v4, x, v4_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v5 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v5_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v5, 1)); + v5 = __riscv_vwmaccus_vx_i32m4_tu (v5, x, v5_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v6 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v6_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v6, 1)); + v6 = __riscv_vwmaccus_vx_i32m4_tu (v6, x, v6_n, 4); + asm volatile("nop" ::: "memory"); + vint16m2_t v7_n = __riscv_vle16_v_i16m2 (in, 4);in+=100; + vint32m4_t v7 = __riscv_vwcvt_x_x_v_i32m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse32_v_i32m4 (out, 4, v0, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v1, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v2, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v3, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v4, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v5, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v6, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v7, 4);out+=100; + } +} + +/* The narrowed signed source is the highest-numbered half of the signed + accumulator, thus it overlaps the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */