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[37.65.175.141]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce1e3a9sm15515825e9.15.2026.08.31.13.08.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 13:08:56 -0700 (PDT) From: Valentin Haudiquet To: opensbi@lists.infradead.org Cc: troy.mitchell@linux.spacemit.com, xianbin.zhu@linux.spacemit.com, anup@brainfault.org, ganboing@gmail.com, samuel.holland@sifive.com, heinrich.schuchardt@canonical.com, Valentin Haudiquet Subject: [PATCH 1/3] platform: generic: spacemit: k3: de-vote cluster power-downs and ungate DMASYS before CCI enable Date: Mon, 31 Aug 2026 22:07:50 +0200 Message-ID: <20260831200832.404000-2-valentin.haudiquet@canonical.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831200832.404000-1-valentin.haudiquet@canonical.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> <20260831200832.404000-1-valentin.haudiquet@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_130900_435845_2B8AF070 X-CRM114-Status: GOOD ( 17.88 ) X-Spam-Score: -1.1 (-) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The v3 patch enables CCI-550 snoop/DVM requests for all seven slave interfaces before de-voting cluster power-downs. Clusters that are still voted for power-down cause the CCI status change-pending bu [...] Content analysis details: (-1.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [185.125.188.122 listed in list.dnswl.org] 3.3 RCVD_IN_SBL_CSS RBL: Received via a relay in Spamhaus SBL-CSS [37.65.175.141 listed in zen.spamhaus.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender -0.0 DMARC_PASS DMARC pass policy X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The v3 patch enables CCI-550 snoop/DVM requests for all seven slave interfaces before de-voting cluster power-downs. Clusters that are still voted for power-down cause the CCI status change-pending busy-wait to hang indefinitely when snoop/DVM is enabled on their slave interfaces. De-vote power-down for all four clusters and the boot hart's core BEFORE enabling CCI. Also deassert DMASYS reset and enable its clock before CCI: the DMA engine sits behind the AIDMA CCI slave interface, and if DMASYS is held in reset the CCI busy-wait hangs when enabling snoop/DVM on that interface. Add DMASYS_RESET and DMASYS_CLK_EN register definitions to k3.h. Signed-off-by: Valentin Haudiquet --- platform/generic/include/spacemit/k3.h | 5 +++ platform/generic/spacemit/k3.c | 50 ++++++++++++++++++++++---- 2 files changed, 48 insertions(+), 7 deletions(-) diff --git a/platform/generic/include/spacemit/k3.h b/platform/generic/include/spacemit/k3.h index f444d064..ed1637b9 100644 --- a/platform/generic/include/spacemit/k3.h +++ b/platform/generic/include/spacemit/k3.h @@ -124,4 +124,9 @@ #define PLAT_CCI_K3_CLUSTER3_0_IFACE_IX 5 #define PLAT_CCI_K3_CLUSTER3_1_IFACE_IX 6 +/* DMASYS reset and clock enable */ +#define DMASYS_RESET (0xd8440000 + 0x22c) +#define DMASYS_CLK_EN (0xd8440000 + 0x234) +#define DMASYS_RESET_DEASSERT BIT(0) +#define DMASYS_CLK_EN_BIT BIT(0) #endif /* __RISCV_SPACEMIT_K3_H__ */ diff --git a/platform/generic/spacemit/k3.c b/platform/generic/spacemit/k3.c index 967d09bf..12c991b6 100644 --- a/platform/generic/spacemit/k3.c +++ b/platform/generic/spacemit/k3.c @@ -56,14 +56,39 @@ static void spacemit_k3_hart_init(u32 hartid) } } -/* The boot hart is already running, so it is never started by the HSM. */ -static void spacemit_k3_keep_boot_hart_powered(void) +/* + * De-vote power-down for all four clusters. This must happen BEFORE + * CCI snoop/DVM enable: clusters still in power-down vote cause the + * CCI busy-wait to hang when enabling snoop/DVM on their slave interfaces. + */ +static void spacemit_k3_keep_all_clusters_powered(void) { u32 value; + int i; - value = readl((void *)(unsigned long)PMU_CX_CAPMP_IDLE_CFG0); - value &= ~CLUSTER_PWR_DOWN_VALUE; - writel(value, (void *)(unsigned long)PMU_CX_CAPMP_IDLE_CFG0); + static const u32 cluster_idle_regs[] = { + PMU_CX_CAPMP_IDLE_CFG0, /* cluster 0 (harts 0-3) */ + PMU_CX_CAPMP_IDLE_CFG4, /* cluster 1 (harts 4-7) */ + PMU_CX_CAPMP_IDLE_CFG8, /* cluster 2 (harts 8-11) */ + PMU_CX_CAPMP_IDLE_CFG12, /* cluster 3 (harts 12-15) */ + }; + + for (i = 0; i < 4; i++) { + value = readl((void *)(unsigned long)cluster_idle_regs[i]); + value &= ~CLUSTER_PWR_DOWN_VALUE; + writel(value, (void *)(unsigned long)cluster_idle_regs[i]); + } +} + +/* + * De-vote the boot hart's core-level power-down. The cluster-level + * de-vote for cluster 0 is already done by keep_all_clusters_powered(); + * this clears the per-core idle config so the boot hart is never + * powered down by the PMU. + */ +static void spacemit_k3_keep_boot_hart_powered(void) +{ + u32 value; value = readl((void *)(unsigned long)PMU_AP_CORE0_IDLE_CFG); value &= ~PMU_AP_IDLE_PWRDOWN_K3_MASK; @@ -88,10 +113,21 @@ static void spacemit_k3_pre_init(void) writel((u32)entry, (void *)(unsigned long)C3_RVBADDR_LO_ADDR); writel((u32)(entry >> 32), (void *)(unsigned long)C3_RVBADDR_HI_ADDR); + /* De-vote all cluster power-downs BEFORE CCI enable. */ + spacemit_k3_keep_all_clusters_powered(); + spacemit_k3_keep_boot_hart_powered(); + + /* + * Deassert DMASYS reset and enable its clock before CCI: the DMA + * engine sits behind the AIDMA CCI slave interface. If DMASYS is + * held in reset or its clock is gated, the CCI busy-wait hangs when + * enabling snoop/DVM on that interface. + */ + writel(DMASYS_RESET_DEASSERT, (void *)(unsigned long)DMASYS_RESET); + writel(DMASYS_CLK_EN_BIT, (void *)(unsigned long)DMASYS_CLK_EN); + for (i = 0; i < array_size(cci_map); i++) cci_enable_snoop_dvm_reqs(cci_map, i); - - spacemit_k3_keep_boot_hart_powered(); } static int spacemit_k3_early_init(bool cold_boot) From patchwork Mon Aug 31 20:07:51 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Haudiquet X-Patchwork-Id: 2295403 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=e5heOg9o; dkim=fail reason="signature verification failed" (4096-bit key; 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[37.65.175.141]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce1e3a9sm15515825e9.15.2026.08.31.13.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 13:08:58 -0700 (PDT) From: Valentin Haudiquet To: opensbi@lists.infradead.org Cc: troy.mitchell@linux.spacemit.com, xianbin.zhu@linux.spacemit.com, anup@brainfault.org, ganboing@gmail.com, samuel.holland@sifive.com, heinrich.schuchardt@canonical.com, Valentin Haudiquet Subject: [PATCH 2/3] platform: generic: spacemit: k3: override cold_boot_allowed for hart 0 only Date: Mon, 31 Aug 2026 22:07:51 +0200 Message-ID: <20260831200832.404000-3-valentin.haudiquet@canonical.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831200832.404000-1-valentin.haudiquet@canonical.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> <20260831200832.404000-1-valentin.haudiquet@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_130901_156342_EDBDB28B X-CRM114-Status: GOOD ( 10.63 ) X-Spam-Score: -1.1 (-) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Only hart 0 is powered at reset on K3. Without overriding cold_boot_allowed, the generic default checks a DTB hart mask which may allow non-hart-0 harts to attempt cold boot, breaking the coldboot lot [...] Content analysis details: (-1.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [185.125.188.123 listed in list.dnswl.org] 3.3 RCVD_IN_SBL_CSS RBL: Received via a relay in Spamhaus SBL-CSS [37.65.175.141 listed in zen.spamhaus.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender -0.0 DMARC_PASS DMARC pass policy X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Only hart 0 is powered at reset on K3. Without overriding cold_boot_allowed, the generic default checks a DTB hart mask which may allow non-hart-0 harts to attempt cold boot, breaking the coldboot lottery on a platform where only one hart is running. Add spacemit_k3_cold_boot_allowed() returning true only for hart 0, matching K1's pattern. Signed-off-by: Valentin Haudiquet --- platform/generic/spacemit/k3.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/platform/generic/spacemit/k3.c b/platform/generic/spacemit/k3.c index 12c991b6..f134427d 100644 --- a/platform/generic/spacemit/k3.c +++ b/platform/generic/spacemit/k3.c @@ -138,11 +138,17 @@ static int spacemit_k3_early_init(bool cold_boot) return generic_early_init(cold_boot); } +static bool spacemit_k3_cold_boot_allowed(u32 hartid) +{ + return !hartid; +} + static int spacemit_k3_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match) { spacemit_k3_hart_init(current_hartid()); generic_platform_ops.early_init = spacemit_k3_early_init; + generic_platform_ops.cold_boot_allowed = spacemit_k3_cold_boot_allowed; return 0; } From patchwork Mon Aug 31 20:07:52 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Haudiquet X-Patchwork-Id: 2295404 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[37.65.175.141]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce1e3a9sm15515825e9.15.2026.08.31.13.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 13:09:00 -0700 (PDT) From: Valentin Haudiquet To: opensbi@lists.infradead.org Cc: troy.mitchell@linux.spacemit.com, xianbin.zhu@linux.spacemit.com, anup@brainfault.org, ganboing@gmail.com, samuel.holland@sifive.com, heinrich.schuchardt@canonical.com, Valentin Haudiquet Subject: [PATCH 3/3] platform: generic: spacemit: k3: wake A100 core 8 for ESOS/RPMI services Date: Mon, 31 Aug 2026 22:07:52 +0200 Message-ID: <20260831200832.404000-4-valentin.haudiquet@canonical.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831200832.404000-1-valentin.haudiquet@canonical.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> <20260831200832.404000-1-valentin.haudiquet@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_130903_559409_544CB405 X-CRM114-Status: GOOD ( 18.29 ) X-Spam-Score: -1.1 (-) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The K3 SoC has two asymmetric CPU complexes: X100 (harts 0-7) and A100 (harts 8-15). ESOS -- the rcpu-side firmware already loaded in SPI NOR -- runs on A100 core 8 and provides RPMI services (clock, [...] Content analysis details: (-1.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [185.125.188.123 listed in list.dnswl.org] 3.3 RCVD_IN_SBL_CSS RBL: Received via a relay in Spamhaus SBL-CSS [37.65.175.141 listed in zen.spamhaus.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender -0.0 DMARC_PASS DMARC pass policy X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The K3 SoC has two asymmetric CPU complexes: X100 (harts 0-7) and A100 (harts 8-15). ESOS -- the rcpu-side firmware already loaded in SPI NOR -- runs on A100 core 8 and provides RPMI services (clock, voltage, device power, system reset, suspend) that the X100 side depends on during boot. Without waking core 8, all RPMI mailbox transactions time out and the system hangs early during Linux boot (at basic.target or cryptsetup.target, depending on which earlier fixes are present). Wake hart 8 during pre_init by writing its RVBADDR to a minimal assembly entry (_spacemit_k3_dummy_start) that does A100-specific CSR setup, restores C2 RVBADDR to the normal warm-boot entry, and enters WFI. The HSM can later start hart 8 normally -- the HSM hart_start happens post-boot from Linux, so there is no race with the dummy path writing RVBADDR concurrently. Add A100 performance CSR definitions (VEC_L1BYPASS, L2_PERF_DIST, CIU_CHR2_DEPD_DIS, CIU_CHR2_MER_DIS) to k3.h and the _spacemit_k3_dummy_start entry to k3_asm.S. Signed-off-by: Valentin Haudiquet --- platform/generic/include/spacemit/k3.h | 11 ++++ platform/generic/include/spacemit/k3_asm.h | 1 + platform/generic/spacemit/k3.c | 19 ++++++ platform/generic/spacemit/k3_asm.S | 75 ++++++++++++++++++++++ 4 files changed, 106 insertions(+) diff --git a/platform/generic/include/spacemit/k3.h b/platform/generic/include/spacemit/k3.h index ed1637b9..b50e9b1b 100644 --- a/platform/generic/include/spacemit/k3.h +++ b/platform/generic/include/spacemit/k3.h @@ -129,4 +129,15 @@ #define DMASYS_CLK_EN (0xd8440000 + 0x234) #define DMASYS_RESET_DEASSERT BIT(0) #define DMASYS_CLK_EN_BIT BIT(0) +/* + * A100 core performance CSRs. CIU_CHR2_DEPD_DIS and CIU_CHR2_MER_DIS + * are bitfields of CSR_ML2HINT (0x7f7), named after the hardware manual's + * CIU_CHR2 register description. + */ +#define CSR_PERF_CTRL 0x7d0 +#define VEC_L1BYPASS (_UL(1) << 32) +#define CSR_PREFETCH_CTRL 0x7d1 +#define L2_PERF_DIST (_UL(3) << 10) +#define CIU_CHR2_DEPD_DIS (_UL(1) << 3) +#define CIU_CHR2_MER_DIS (_UL(1) << 2) #endif /* __RISCV_SPACEMIT_K3_H__ */ diff --git a/platform/generic/include/spacemit/k3_asm.h b/platform/generic/include/spacemit/k3_asm.h index 70c00478..3f06b20e 100644 --- a/platform/generic/include/spacemit/k3_asm.h +++ b/platform/generic/include/spacemit/k3_asm.h @@ -11,6 +11,7 @@ #ifndef __ASSEMBLY__ void _spacemit_k3_warm_start(void); +void _spacemit_k3_dummy_start(void); #endif #endif /* __RISCV_SPACEMIT_K3_ASM_H__ */ diff --git a/platform/generic/spacemit/k3.c b/platform/generic/spacemit/k3.c index f134427d..650e9f98 100644 --- a/platform/generic/spacemit/k3.c +++ b/platform/generic/spacemit/k3.c @@ -128,6 +128,25 @@ static void spacemit_k3_pre_init(void) for (i = 0; i < array_size(cci_map); i++) cci_enable_snoop_dvm_reqs(cci_map, i); + + /* + * Wake hart 8 (first A100 core, cluster 2) so that ESOS -- already + * loaded in SPI NOR -- can provide RPMI services (clock, voltage, + * device power, system reset, suspend). Without this, all RPMI + * mailbox transactions time out. + * + * Core 8 jumps to _spacemit_k3_dummy_start which does minimal A100 + * setup, restores C2 RVBADDR to the normal warm-boot entry, and + * enters WFI. The K3 HSM can later start it normally -- the HSM + * hart_start for hart 8 happens much later (post-boot, from Linux), + * so there is no window where both the dummy path and HSM could + * write RVBADDR concurrently. + */ + writel((u32)(unsigned long)&_spacemit_k3_dummy_start, + (void *)(unsigned long)C2_RVBADDR_LO_ADDR); + writel((u32)((unsigned long)&_spacemit_k3_dummy_start >> 32), + (void *)(unsigned long)C2_RVBADDR_HI_ADDR); + writel(BIT(8), (void *)(unsigned long)PMU_CAP_CORE8_WAKEUP); } static int spacemit_k3_early_init(bool cold_boot) diff --git a/platform/generic/spacemit/k3_asm.S b/platform/generic/spacemit/k3_asm.S index 2da58857..9d1ea5c5 100644 --- a/platform/generic/spacemit/k3_asm.S +++ b/platform/generic/spacemit/k3_asm.S @@ -50,3 +50,78 @@ _spacemit_k3_warm_start: .word 0x62000073 /* hfence.gvma */ 1: j _start_warm + +/* + * Minimal entry point for the initial wake of an A100 core (hart 8) on + * cluster 2. Its sole purpose is to power up the cluster so that ESOS + * -- already loaded in SPI NOR -- can provide RPMI services (clock, voltage, + * device power, system reset, suspend). After setup the core enters WFI; + * the K3 HSM can later start it normally via the warm-boot vector. + * + * The PMA/L2/cache setup below mirrors _spacemit_k3_warm_start, plus + * A100-specific performance CSRs that ESOS needs. These are applied + * only here because upstream K3 support targets X100 harts (0-7) for + * Linux; A100 harts (8-15) are used solely for ESOS. When the HSM + * later starts hart 8 from Linux, it enters warm_start -- the perf CSR + * settings persist from this initial wake since it is a WFI exit, not + * a cold reset. + * + * The C2 RVBADDR is restored to _spacemit_k3_warm_start so that the next + * wake (from HSM hart_start) enters the standard OpenSBI warm-boot path. + */ + .align 3 + .globl _spacemit_k3_dummy_start +_spacemit_k3_dummy_start: + /* Disable all interrupts. */ + csrw 0x304, zero /* CSR_MIE */ + + /* Program PMA attributes before enabling the caches. */ + li t0, (PMACFG0_AUDIO_BUF_FIELD_MASK << \ + PMACFG0_AUDIO_BUF_FIELD_SHIFT) + csrc CSR_PMACFG0, t0 + li t0, (PMACFG0_AUDIO_BUF_ATTR_CACHEABLE << \ + PMACFG0_AUDIO_BUF_FIELD_SHIFT) + csrs CSR_PMACFG0, t0 + li t0, PMACFG0_XIP_FIELD_CLEAR + csrc CSR_PMACFG0, t0 + li t0, PMACFG0_XIP_ATTR_IO + csrs CSR_PMACFG0, t0 + sfence.vma + + /* A100-specific performance CSRs. */ + li t0, VEC_L1BYPASS + csrs CSR_PERF_CTRL, t0 + li t0, L2_PERF_DIST + csrs CSR_PREFETCH_CTRL, t0 + li t0, CIU_CHR2_DEPD_DIS + csrc CSR_ML2HINT, t0 + li t0, CIU_CHR2_MER_DIS + csrs CSR_ML2HINT, t0 + + /* Enable L1 snooping and L2 prefetch for this hart. */ + csrr t0, mhartid + andi t0, t0, (PLATFORM_MAX_CPUS_PER_CLUSTER - 1) + li t1, 1 + sll t1, t1, t0 + li t2, (ML2SETUP_IPRF | ML2SETUP_TPRF) + or t1, t1, t2 + csrs CSR_ML2SETUP, t1 + li t0, ML2HINT_TRACE_TOP_ICGEN + csrs CSR_ML2HINT, t0 + + /* Enable caches. */ + li t0, MSETUP_BOOT_FLAGS + csrs CSR_MSETUP, t0 + fence iorw, iorw /* A100 needs explicit fence after MSETUP */ + + /* Restore C2 RVBADDR to the normal warm-boot entry. */ + lla t0, _spacemit_k3_warm_start + li t1, C2_RVBADDR_LO_ADDR + sw t0, 0(t1) + li t1, C2_RVBADDR_HI_ADDR + srli t0, t0, 32 + sw t0, 0(t1) + + /* Enter WFI until the HSM starts this hart. */ +1: wfi + j 1b