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As a result, devices attached to SCMI performance domains can report failures when relinquishing their performance vote. The OPP framework use performance state 0 to indicate that no performance vote is required. For example, dev_pm_opp_set_rate(dev, 0) is commonly used (by firmware or linux) when a device is runtime suspended. A zero performance state does not require any SCMI performance request to be sent. Treat it as a no-op and return success instead of reporting an error. Reviewed-by: Abel Vesa Reviewed-by: Mukesh Savaliya Signed-off-by: Praveen Talari --- drivers/pmdomain/arm/scmi_perf_domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pmdomain/arm/scmi_perf_domain.c b/drivers/pmdomain/arm/scmi_perf_domain.c index 3693423459c9..e390f902a444 100644 --- a/drivers/pmdomain/arm/scmi_perf_domain.c +++ b/drivers/pmdomain/arm/scmi_perf_domain.c @@ -33,7 +33,7 @@ scmi_pd_set_perf_state(struct generic_pm_domain *genpd, unsigned int state) return 0; if (!state) - return -EINVAL; + return 0; ret = pd->perf_ops->level_set(pd->ph, pd->domain_id, state, false); if (ret) From patchwork Thu Aug 27 17:59:19 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 2293628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Thu, 27 Aug 2026 10:59:46 -0700 (PDT) X-Received: by 2002:a17:90b:380b:b0:380:f85c:94b4 with SMTP id 98e67ed59e1d1-396d0f2391cmr1736384a91.7.1787853586253; Thu, 27 Aug 2026 10:59:46 -0700 (PDT) Received: from hu-ptalari-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141a905cf38sm27437523c88.12.2026.08.27.10.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:59:45 -0700 (PDT) From: Praveen Talari Date: Thu, 27 Aug 2026 23:29:19 +0530 Subject: [PATCH v2 2/9] soc: qcom: geni-se: Populate clk_perf_tbl with SE source clock frequencies from perf OPP table Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-2-091697dbeb02@oss.qualcomm.com> References: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> In-Reply-To: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> To: konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: mukesh.savaliya@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, Praveen Talari X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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This does not allow computing a source clock and divider combination for a protocol requested frequency, unlike the Linux clock managed path which derives this from se->clk_perf_tbl via geni_se_clk_freq_match(), and then applies the matched source clock frequency with dev_pm_opp_set_rate(). Change this by treating the OPP table exposed on the perf domain device as representing the actual SE HW supported source clock frequencies, the same role clk_perf_tbl plays for the Linux clock managed path. Populate se->clk_perf_tbl and se->num_clk_levels by iterating over this OPP table in geni_se_domain_attach(), so that protocol drivers on the firmware managed (SA8255P) path can also use geni_se_clk_freq_match() to pick the closest supported source clock frequency and calculate the required divider, and apply it with dev_pm_opp_set_rate() the same way as it is done for the Linux clock managed path, instead of relying on a direct frequency/baudrate-to- perf-level mapping. Signed-off-by: Praveen Talari --- drivers/soc/qcom/qcom-geni-se.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 873bfbd6b2b7..447b9cc6babf 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1155,7 +1155,8 @@ EXPORT_SYMBOL_GPL(geni_se_set_perf_opp); * * This function attaches the power domains ("power" and "perf") required * in the SCMI auto-VM environment to the GENI Serial Engine device. It - * initializes se->pd_list with the attached domains. + * initializes se->pd_list with the attached domains, and populates + * se->clk_perf_tbl from the OPP table of the "perf" domain device. * * Return: 0 on success, or a negative error code on failure. */ @@ -1166,7 +1167,12 @@ int geni_se_domain_attach(struct geni_se *se) .pd_names = (const char*[]) { "power", "perf" }, .num_pd_names = 2, }; + struct device *perf_dev; + struct dev_pm_opp *opp; + unsigned int level; + int num_opps; int ret; + int i; ret = devm_pm_domain_attach_list(se->dev, &pd_data, &se->pd_list); @@ -1175,6 +1181,31 @@ int geni_se_domain_attach(struct geni_se *se) else if (ret < 0) return ret; + perf_dev = se->pd_list->pd_devs[DOMAIN_IDX_PERF]; + + num_opps = dev_pm_opp_get_opp_count(perf_dev); + if (num_opps < 0) + return num_opps; + if (num_opps == 0) + return -ENODEV; + + se->clk_perf_tbl = devm_kcalloc(se->dev, num_opps, + sizeof(*se->clk_perf_tbl), + GFP_KERNEL); + if (!se->clk_perf_tbl) + return -ENOMEM; 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Thu, 27 Aug 2026 10:59:52 -0700 (PDT) Received: from hu-ptalari-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141a905cf38sm27437523c88.12.2026.08.27.10.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:59:52 -0700 (PDT) From: Praveen Talari Date: Thu, 27 Aug 2026 23:29:20 +0530 Subject: [PATCH v2 3/9] soc: qcom: geni-se: Add helper to set SE clock rate via OPP Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-3-091697dbeb02@oss.qualcomm.com> References: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> In-Reply-To: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> To: konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: mukesh.savaliya@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, Praveen Talari X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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However, the device that owns the OPP table differs depending on how the SE resources are managed. For Linux clock managed platforms, the OPP table is associated with the SE device, whereas on firmware-managed platforms it is associated with the performance power-domain device. This requires protocol drivers to be aware of the underlying resource management model when requesting frequency changes. Introduce geni_se_set_rate(), a common helper that abstracts this difference and applies the requested frequency through the appropriate device. The helper automatically selects the performance-domain device when power domains are attached and falls back to the SE device otherwise. Acked-by: Mukesh Kumar Savaliya Signed-off-by: Praveen Talari --- drivers/soc/qcom/qcom-geni-se.c | 22 ++++++++++++++++++++++ include/linux/soc/qcom/geni-se.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 447b9cc6babf..04f58a6f26ff 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1149,6 +1149,28 @@ int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq) } EXPORT_SYMBOL_GPL(geni_se_set_perf_opp); +/** + * geni_se_set_rate() - Set the SE source clock rate via the OPP framework. + * @se: Pointer to the struct geni_se instance. + * @freq: The source clock frequency to set. + * + * Applies the given frequency through dev_pm_opp_set_rate(), targeting the + * perf domain device when the SE has power domains attached (firmware + * managed path), or se->dev otherwise (Linux clock managed path). + * + * Return: 0 on success, or a negative error code on failure. + */ +int geni_se_set_rate(struct geni_se *se, unsigned long freq) +{ + struct device *perf_dev = se->dev; + + if (se->pd_list && se->pd_list->pd_devs[DOMAIN_IDX_PERF]) + perf_dev = se->pd_list->pd_devs[DOMAIN_IDX_PERF]; + + return se->has_opp ? dev_pm_opp_set_rate(perf_dev, freq) : 0; +} +EXPORT_SYMBOL_GPL(geni_se_set_rate); + /** * geni_se_domain_attach() - Attach power domains to a GENI SE device. * @se: Pointer to the geni_se structure representing the GENI SE device. diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 29a53bbc0dd4..3b411cba9339 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -596,5 +596,7 @@ int geni_se_domain_attach(struct geni_se *se); int geni_se_set_perf_level(struct geni_se *se, unsigned long level); int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq); + +int geni_se_set_rate(struct geni_se *se, unsigned long freq); #endif #endif From patchwork Thu Aug 27 17:59:21 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 2293627 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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OPP resource management should be controlled by the consumer driver. Additionally, clocks are already disabled by geni_se_clks_off(), making the OPP rate reset unnecessary during resource deactivation. Signed-off-by: Praveen Talari Reviewed-by: Mukesh Kumar Savaliya --- drivers/soc/qcom/qcom-geni-se.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 04f58a6f26ff..d4f0544d73c4 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1039,8 +1039,8 @@ EXPORT_SYMBOL_GPL(geni_icc_disable); * geni_se_resources_deactivate() - Deactivate GENI SE device resources * @se: Pointer to the geni_se structure * - * Deactivates device resources for power saving: OPP rate to 0, pin control - * to sleep state, turns off clocks, and disables interconnect. Skips ACPI devices. + * Deactivates device resources for power saving: pin control to sleep + * state, turns off clocks, and disables interconnect. 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Thu, 27 Aug 2026 11:00:05 -0700 (PDT) Received: from hu-ptalari-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141a905cf38sm27437523c88.12.2026.08.27.10.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 11:00:05 -0700 (PDT) From: Praveen Talari Date: Thu, 27 Aug 2026 23:29:22 +0530 Subject: [PATCH v2 5/9] serial: qcom-geni: Use geni_se_set_rate() for source clock configuration Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-5-091697dbeb02@oss.qualcomm.com> References: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> In-Reply-To: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> To: konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: mukesh.savaliya@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, Praveen Talari X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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To work around this, firmware instead exposes the SE HW supported source clock frequencies as OPPs on the perf domain device. geni_se_domain_attach() now populates clk_perf_tbl from the performance-domain OPP table, allowing firmware-managed platforms to use geni_se_clk_freq_match(). Call geni_serial_set_rate() unconditionally from qcom_geni_serial_set_termios(), and use geni_se_set_rate() instead of dev_pm_opp_set_rate() so clock programming is handled centrally by the GENI core, independent of the underlying clock-control mechanism. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 3633723acef8..23ecd137c521 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -114,7 +114,6 @@ struct qcom_geni_device_data { bool console; enum geni_se_xfer_mode mode; int (*resources_init)(struct geni_se *se); - int (*set_rate)(struct geni_se *se, unsigned long baud); int (*power_on)(struct geni_se *se); int (*power_off)(struct geni_se *se); }; @@ -1474,7 +1473,10 @@ static int geni_serial_set_rate(struct geni_se *se, unsigned long baud) uport->uartclk = clk_rate; port->clk_rate = clk_rate; - dev_pm_opp_set_rate(uport->dev, clk_rate); + ret = geni_se_set_rate(&port->se, clk_rate); + if (ret) + return ret; + ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; @@ -1513,7 +1515,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, /* baud rate */ baud = uart_get_baud_rate(uport, termios, old, 300, 8000000); - ret = port->dev_data->set_rate(&port->se, baud); + ret = geni_serial_set_rate(&port->se, baud); if (ret) return; @@ -2039,15 +2041,19 @@ static void qcom_geni_serial_remove(struct platform_device *pdev) static int __maybe_unused qcom_geni_serial_runtime_suspend(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); + int ret; - return port->dev_data->power_off ? - port->dev_data->power_off(&port->se) : 0; + ret = port->dev_data->power_off ? + port->dev_data->power_off(&port->se) : 0; + if (ret) + return ret; + + return geni_se_set_rate(&port->se, 0); } static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); - struct uart_port *uport = &port->uport; int ret; if (port->dev_data->power_on) { @@ -2056,8 +2062,8 @@ static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *dev) return ret; } - if (port->se.has_opp && port->clk_rate) - return dev_pm_opp_set_rate(uport->dev, port->clk_rate); + if (port->clk_rate) + return geni_se_set_rate(&port->se, port->clk_rate); return 0; } @@ -2116,7 +2122,6 @@ static const struct qcom_geni_device_data qcom_geni_console_data = { .console = true, .mode = GENI_SE_FIFO, .resources_init = geni_se_resources_init, - .set_rate = geni_serial_set_rate, .power_on = geni_se_resources_activate, .power_off = geni_se_resources_deactivate, }; @@ -2125,7 +2130,6 @@ static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = { .console = true, .mode = GENI_SE_FIFO, .resources_init = geni_se_domain_attach, - .set_rate = geni_se_set_perf_level, }; #endif @@ -2133,7 +2137,6 @@ static const struct qcom_geni_device_data qcom_geni_uart_data = { .console = false, .mode = GENI_SE_DMA, .resources_init = geni_se_resources_init, - .set_rate = geni_serial_set_rate, .power_on = geni_se_resources_activate, .power_off = geni_se_resources_deactivate, }; @@ -2142,7 +2145,6 @@ static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data = { .console = false, .mode = GENI_SE_DMA, .resources_init = geni_se_domain_attach, - .set_rate = geni_se_set_perf_level, }; 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To work around this, firmware instead exposes the SE HW supported source clock frequencies as OPPs on the perf domain device. geni_se_domain_attach() now populates clk_perf_tbl from the performance-domain OPP table, allowing firmware-managed platforms to use geni_se_clk_freq_match(). Use geni_se_set_rate() instead of dev_pm_opp_set_rate() so clock programming is handled centrally by the GENI core, independent of the underlying clock-control mechanism. Acked-by: Mark Brown Signed-off-by: Praveen Talari Reviewed-by: Mukesh Kumar Savaliya --- drivers/spi/spi-geni-qcom.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 6566975eb24f..03ce9eff9c24 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -82,7 +81,6 @@ struct geni_spi_desc { int (*resources_init)(struct geni_se *se); - int (*set_rate)(struct geni_se *se, unsigned long clk_freq); int (*power_on)(struct geni_se *se); int (*power_off)(struct geni_se *se); }; @@ -150,9 +148,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz, dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, actual_hz, sclk_freq, *clk_idx, *clk_div); - ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); + ret = geni_se_set_rate(&mas->se, sclk_freq); if (ret) - dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); + dev_err(mas->dev, "geni_se_set_rate failed %d\n", ret); else mas->cur_sclk_hz = sclk_freq; @@ -847,7 +845,7 @@ static int setup_se_xfer(struct spi_transfer *xfer, } /* Speed and bits per word can be overridden per transfer */ - ret = mas->dev_data->set_rate(&mas->se, xfer->speed_hz); + ret = geni_spi_set_clock_and_bw(&mas->se, xfer->speed_hz); if (ret) return ret; @@ -1161,9 +1159,14 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) { struct spi_controller *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_controller_get_devdata(spi); + int ret; + + ret = mas->dev_data->power_off ? + mas->dev_data->power_off(&mas->se) : 0; + if (ret) + return ret; - return mas->dev_data->power_off ? - mas->dev_data->power_off(&mas->se) : 0; + return geni_se_set_rate(&mas->se, 0); } static int __maybe_unused spi_geni_runtime_resume(struct device *dev) @@ -1178,10 +1181,7 @@ static int __maybe_unused spi_geni_runtime_resume(struct device *dev) return ret; } - if (mas->se.has_opp) - return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 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Add the source clock index and frequency to the I2C clock map entries and use them while configuring the controller. Request the required source clock rate through dev_pm_opp_set_rate() and program SE_GENI_CLK_SEL with the matching source index. Signed-off-by: Praveen Talari --- drivers/i2c/busses/i2c-qcom-geni.c | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 658636c1ee0e..a3b7609e3cf9 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -165,8 +166,13 @@ struct geni_i2c_clk_fld { u8 t_high_cnt; u8 t_low_cnt; u8 t_cycle_cnt; + u8 src_indx; + u32 src_clk_freq; }; +#define CLK_19P2MHZ (19200 * HZ_PER_KHZ) +#define CLK_32MHZ (32 * HZ_PER_MHZ) + /* * Hardware uses the underlying formula to calculate time periods of * SCL clock cycle. Firmware uses some additional cycles excluded from the @@ -180,17 +186,17 @@ struct geni_i2c_clk_fld { * source_clock = 19.2 MHz */ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { - { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 }, - { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 }, - { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 }, + { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26, 0, CLK_19P2MHZ }, + { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22, 0, CLK_19P2MHZ }, + { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18, 0, CLK_19P2MHZ }, {} }; /* source_clock = 32 MHz */ static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { - { I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 }, - { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, - { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, + { I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38, 1, CLK_32MHZ }, + { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19, 1, CLK_32MHZ }, + { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15, 1, CLK_32MHZ }, {} }; @@ -198,7 +204,7 @@ static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) { const struct geni_i2c_clk_fld *itr; - if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) + if (clk_get_rate(gi2c->se.clk) == CLK_32MHZ) itr = geni_i2c_clk_map_32mhz; else itr = geni_i2c_clk_map_19p2mhz; @@ -218,8 +224,13 @@ static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; u32 val; + int ret; + + ret = dev_pm_opp_set_rate(se->dev, itr->src_clk_freq); + if (ret) + return ret; - writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); + writel_relaxed(itr->src_indx, gi2c->se.base + SE_GENI_CLK_SEL); val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); @@ -1228,6 +1239,8 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) } } + dev_pm_opp_set_rate(dev, 0); + return 0; } @@ -1236,6 +1249,12 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) int ret = 0; struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); + if (gi2c->clk_fld && gi2c->clk_fld->src_clk_freq) { + ret = dev_pm_opp_set_rate(dev, gi2c->clk_fld->src_clk_freq); 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Neither operation is required for resource initialization itself. Move clock frequency validation to probe and program the ICC bandwidth vote from qcom_geni_i2c_conf(), where the bus frequency is configured. This allows the driver to use geni_se_resources_init() directly and removes the I2C-specific resource initialization wrapper. Signed-off-by: Praveen Talari Reviewed-by: Mukesh Kumar Savaliya --- drivers/i2c/busses/i2c-qcom-geni.c | 31 ++++++++++--------------------- 1 file changed, 10 insertions(+), 21 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index a3b7609e3cf9..0b178701e1d1 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -242,7 +242,9 @@ static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) trace_geni_i2c_bus_setup(gi2c->se.dev, gi2c->clk_freq_out, itr->clk_div, itr->t_high_cnt, itr->t_low_cnt, itr->t_cycle_cnt); - return 0; + + return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, + Bps_to_icc(gi2c->clk_freq_out)); } static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) @@ -1111,24 +1113,6 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) return ret; } -static int geni_i2c_resources_init(struct geni_se *se) -{ - struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); - int ret; - - ret = geni_se_resources_init(&gi2c->se); - if (ret) - return ret; - - ret = geni_i2c_clk_map_idx(gi2c); - if (ret) - return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", - gi2c->clk_freq_out); - - return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, - Bps_to_icc(gi2c->clk_freq_out)); -} - static int geni_i2c_probe(struct platform_device *pdev) { struct geni_i2c_dev *gi2c; @@ -1199,6 +1183,11 @@ static int geni_i2c_probe(struct platform_device *pdev) if (ret < 0) return ret; + ret = geni_i2c_clk_map_idx(gi2c); + if (ret) + return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", + gi2c->clk_freq_out); + ret = i2c_add_adapter(&gi2c->adap); if (ret) return dev_err_probe(dev, ret, "Error adding i2c adapter\n"); @@ -1300,7 +1289,7 @@ static const struct dev_pm_ops geni_i2c_pm_ops = { }; static const struct geni_i2c_desc geni_i2c = { - .resources_init = geni_i2c_resources_init, + .resources_init = geni_se_resources_init, .set_rate = qcom_geni_i2c_conf, .power_on = geni_se_resources_activate, .power_off = geni_se_resources_deactivate, @@ -1309,7 +1298,7 @@ static const struct geni_i2c_desc geni_i2c = { static const struct geni_i2c_desc i2c_master_hub = { .no_dma_support = true, .tx_fifo_depth = 16, - .resources_init = geni_i2c_resources_init, + .resources_init = geni_se_resources_init, .set_rate = qcom_geni_i2c_conf, .power_on = geni_se_resources_activate, .power_off = geni_se_resources_deactivate, From patchwork Thu Aug 27 17:59:26 2026 Content-Type: text/plain; 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Source clock programming currently depends on platform-specific callbacks. Use geni_se_set_rate() for source clock programming and perform the source clock configuration from qcom_geni_i2c_conf(), allowing the GENI core to abstract the underlying resource-management mechanism from the I2C driver. This removes the need for platform-specific rate-setting callbacks and enables a common code path across all GENI I2C platforms. Signed-off-by: Praveen Talari --- drivers/i2c/busses/i2c-qcom-geni.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 0b178701e1d1..deb0d822290c 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -219,14 +218,14 @@ static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) return -EINVAL; } -static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) +static int qcom_geni_i2c_conf(struct geni_se *se) { struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; u32 val; int ret; - ret = dev_pm_opp_set_rate(se->dev, itr->src_clk_freq); + ret = geni_se_set_rate(&gi2c->se, itr->src_clk_freq); if (ret) return ret; @@ -985,7 +984,7 @@ static int geni_i2c_xfer(struct i2c_adapter *adap, return ret; } - ret = gi2c->dev_data->set_rate(&gi2c->se, gi2c->clk_freq_out); + ret = qcom_geni_i2c_conf(&gi2c->se); if (ret) return ret; @@ -1228,7 +1227,7 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) } } - dev_pm_opp_set_rate(dev, 0); + geni_se_set_rate(&gi2c->se, 0); return 0; } @@ -1239,7 +1238,7 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); if (gi2c->clk_fld && gi2c->clk_fld->src_clk_freq) { - ret = dev_pm_opp_set_rate(dev, gi2c->clk_fld->src_clk_freq); + ret = geni_se_set_rate(&gi2c->se, gi2c->clk_fld->src_clk_freq); if (ret) return ret; } @@ -1290,7 +1289,6 @@ static const struct dev_pm_ops geni_i2c_pm_ops = { static const struct geni_i2c_desc geni_i2c = { .resources_init = geni_se_resources_init, - .set_rate = qcom_geni_i2c_conf, .power_on = geni_se_resources_activate, .power_off = geni_se_resources_deactivate, }; @@ -1299,14 +1297,12 @@ static const struct geni_i2c_desc i2c_master_hub = { .no_dma_support = true, .tx_fifo_depth = 16, .resources_init = geni_se_resources_init, - .set_rate = qcom_geni_i2c_conf, .power_on = geni_se_resources_activate, .power_off = geni_se_resources_deactivate, }; static const struct geni_i2c_desc sa8255p_geni_i2c = { .resources_init = geni_se_domain_attach, - .set_rate = geni_se_set_perf_opp, }; #ifdef CONFIG_ACPI