From patchwork Thu Aug 27 09:19:19 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Mitchell X-Patchwork-Id: 2293277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=La7LWweG; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linux.spacemit.com header.i=@linux.spacemit.com header.a=rsa-sha256 header.s=mxsw2412 header.b=jFGcmE9/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hVwwr07fxz1xtd for ; Thu, 27 Aug 2026 19:20:43 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7EiqQ3EUMUP4sw2uiJkdUojZ84L3JW9TEerZ1d9WlIo=; b=La7LWweGk3uRTB x+eQdhjILBQVAhhgqtug7/IKOWm0Gx5OEoXllTSx65dHlkTLn1qpxlNSooX/LIne3IZiYl16ud2z6 FQrh8lMi0AfTHtx4iDgTz8mQfKx6cZobQnfRe06rMJQoFmbi2emby3A209lAbrmwCm7ERT21fmu4Y W63stc0C+Im4n50M4H5+AdC8lz4a50hOwIxb+CXvcG6iC7J+RDEnAYN1VjwdRK2D+qgYOvEcpqSG/ vyE9hK/pz7NiT1xToXagKMTk7j7+PRckcrp/WDw4UlUx1h69zUeqsq9EIFzD8QpBIuy6ltLYo4xa4 cXqu8DmH8blNwhYw+H5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHd-00000003jBq-1sAs; Thu, 27 Aug 2026 09:20:29 +0000 Received: from smtpbgsg2.qq.com ([54.254.200.128]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHW-00000003j7u-2IrI for opensbi@lists.infradead.org; Thu, 27 Aug 2026 09:20:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.spacemit.com; s=mxsw2412; t=1787822391; bh=wVw90sfs9PlVdeDg/k4db72/SMB8hfEVBNgToxEdYis=; h=From:Date:Subject:MIME-Version:Message-Id:To; b=jFGcmE9/eDsVD7HRsYDkkypdqDKdk99mwgK3nq0P6/F6UllUO6pG3YuMnwsNpDKVT qb8gjo8x0h2yic8AVG2XM27uGQMQqVnyaIfLAwzHLZL1ZCgAGq228Xef6WLAY2Qz2W x9XnGItrXfA7Qx//+eGFnecmwMq8oa2ewWRwyabU= X-QQ-mid: zesmtpgz8t1787822385t314a74ac X-QQ-Originating-IP: ywGuR3+rC0yRCgApzuyjOSZxn73YZWSB1nRSSGBU1z8= Received: from = ( [183.48.244.190]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 27 Aug 2026 17:19:41 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 8241214424296675875 EX-QQ-RecipientCnt: 7 From: Troy Mitchell Date: Thu, 27 Aug 2026 17:19:19 +0800 Subject: [PATCH v3 1/5] lib: sbi: select expected trap handler per hart MIME-Version: 1.0 Message-Id: <20260827-spacemit-k3-v3-1-5d8dbb68539d@linux.spacemit.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> In-Reply-To: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> To: opensbi@lists.infradead.org Cc: Xianbin Zhu , Anup Patel , Bo Gan , Samuel Holland , Heinrich Schuchardt , Troy Mitchell X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6243; i=troy.mitchell@linux.spacemit.com; h=from:subject:message-id; bh=Zn1ERjI4DSngVkikJVfH+uyhx4a8vAjUwA34Rcn//NU=; b=owGbwMvMwCU2g/N9w09jE33G02pJDFkTGBXu71IqjD8c8cPE5NQJnxPmzp8vqix5K+xrtsypQ 6/GQry5o5SFQYyLQVZMkaX7Ac+2Ap8o2wKBQl+YOaxMIEMYuDgFYCJsBxkZzltIqB+rVpmXN+uV 5If5h0+XBKTmtZXGMsrtii62XGGXy/A/1Uy/a/E8rt9af+fzu8783yH6OETW+2WlSMhXHvdv7PM ZAQ== X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=openpgp; fpr=3FE5535CF1B0E658E57DB59BAE1C2FBEA7DB42E1 X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: NQT7GHsdltgIT2uHjVSl3MCpL/triiMRlqBd0sCPoHz/CTy86ogOw2yT AtHrtfJJXkz4dGMB4C1jFn3S36dSY8FDz8Fio7k1ZYk1wljChYG4GUiGPl7+XtQxKMB/9hz KcZwxW63lXDa8py+N4iV8v8ogNxOIQlqb9/+BUNQnrtIjahfQ3D/yvQ1sQ879C+MQF1vfjn 6JeYfepO5b/iY3eHcWKxPwjqkeva18S0LzfiWrxdC+6xAg4RVXjOErl3rVCTfYejuefuTOO W2rWKCB/4yMrhepuic/0DEaLG7cECz0RK6doyQwO/s+vw/DxkARrtzvdvlmQT7pC/PzgkSy CCSReV/WspRTPXyvUrquoHT9FlAg+Sp44MwJr9gtDIHVdovR8bBJIOTS9DOSYxc0w6DfeyM 9vHya7CTSlZ4c+8+EMU+gSXB211PWJbVevFyew1nhMlJoa+fFj0jmywydC5kRBMOXy1J+us nS1OTEgRvszibkNmAUaxHRhpSd5OA1DeJi0PbZgnpuyEjydIsC0lVFaMP2ArPZEYlgRc7Uk a7Xx2ISWMqPMwn2+ir/GP+XrzHiZyVWMRXC5stUqbPW6fvKTIbmt0QDRuzDNR0BYy0BQLkZ p4J8vtudWRy4wCpkH5JyH77Hk9TPBn8LmDtsyzJaClgofftNmzTBIhMRiBwwjX4DCNIZPbW 6L4SXlNwh+GefK3tqFKODDUf8fHyTuT1pJ3HCND0h8xQ17OxEuLkYcpHW4NlA5UFbMgYhxq flmGhcdcYfL+9dZgoJ/s371PLgOSMg+YwfR5g8xX7Ks0Rqm6GfdTB3U6S7c8bJ+1RPk3TOM xFEJ7p17MlnoFvR364CGWYMkELvbJO26BEL715oxFPHL/oikDznCx9LVLl/ync3IcOiwCjI 82/59mQB67axh2yp1dcxp/EOA/PLL68qWPOfpP5x6KhGJ/k5B3h7lGzaLThz0ZmoWafIOJM 2B02cYDiHeFQq16bu915NbiklafPouFTCeelpqEsKu9htzq0pqmu9YwEgQWCHfErUpDy1Q9 wuF89XsggnoUGcaORdwS7mWV/Jsf0TMA4KnnAmD9delie3wNeO8jnOqe7m8DcK+ZOsL5slQ Mif6SU8vdR5lYxnfKfNXmshS3Ilb7byEP7oMRNepQR9 X-QQ-XMRINFO: Nq+8W0+stu50tPAe92KXseR0ZZmBTk3gLg== X-QQ-RECHKSPAM: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260827_022023_319592_D6BD8A5F X-CRM114-Status: GOOD ( 11.42 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The expected trap handler is selected once by the cold boot hart. This breaks heterogeneous systems where the cold boot hart implements H but another hart does not, because the H-aware handler accesse [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [54.254.200.128 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [54.254.200.128 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The expected trap handler is selected once by the cold boot hart. This breaks heterogeneous systems where the cold boot hart implements H but another hart does not, because the H-aware handler accesses mtval2 and mtinst. Select the handler from the current hart's MISA at each use so every hart uses only the CSRs it implements. Fixes: 1de66d170e71 ("lib: Optimize unpriv load/store implementation") Reported-by: Bo Gan Link: https://lore.kernel.org/r/e702f291-dde8-4b99-a65e-182d2b847720@gmail.com Suggested-by: Bo Gan Signed-off-by: Troy Mitchell Reviewed-by: Bo Gan --- include/sbi/sbi_csr_detect.h | 4 ++-- include/sbi/sbi_hart.h | 2 +- lib/sbi/sbi_hart.c | 9 +++++---- lib/sbi/sbi_illegal_atomic.c | 4 ++-- lib/sbi/sbi_unpriv.c | 6 +++--- 5 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/sbi/sbi_csr_detect.h b/include/sbi/sbi_csr_detect.h index 097c31c8..31e50db9 100644 --- a/include/sbi/sbi_csr_detect.h +++ b/include/sbi/sbi_csr_detect.h @@ -16,9 +16,9 @@ #define csr_read_allowed(csr_num, trap) \ ({ \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong tinfo asm("a3") = (ulong)trap; \ register ulong ttmp asm("a4"); \ - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ register ulong ret = 0; \ ((struct sbi_trap_info *)(trap))->cause = 0; \ asm volatile( \ @@ -35,9 +35,9 @@ #define csr_write_allowed(csr_num, trap, value) \ ({ \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong tinfo asm("a3") = (ulong)trap; \ register ulong ttmp asm("a4"); \ - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ ((struct sbi_trap_info *)(trap))->cause = 0; \ asm volatile( \ "add %[ttmp], %[tinfo], zero\n" \ diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 543393bb..6f4ee31e 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -135,7 +135,7 @@ struct sbi_scratch; int sbi_hart_reinit(struct sbi_scratch *scratch); int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot); -extern void (*sbi_hart_expected_trap)(void); +ulong sbi_hart_expected_trap_addr(void); unsigned int sbi_hart_mhpm_mask(struct sbi_scratch *scratch); void sbi_hart_delegation_dump(struct sbi_scratch *scratch, diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index bee88557..14e44955 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -25,7 +25,11 @@ extern void __sbi_expected_trap(void); extern void __sbi_expected_trap_hext(void); -void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap; +ulong sbi_hart_expected_trap_addr(void) +{ + return misa_extension('H') ? (ulong)&__sbi_expected_trap_hext : + (ulong)&__sbi_expected_trap; +} unsigned long hart_features_offset; @@ -712,9 +716,6 @@ int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot) csr_write(CSR_MIP, 0); if (cold_boot) { - if (misa_extension('H')) - sbi_hart_expected_trap = &__sbi_expected_trap_hext; - hart_features_offset = sbi_scratch_alloc_offset( sizeof(struct sbi_hart_features)); if (!hart_features_offset) diff --git a/lib/sbi/sbi_illegal_atomic.c b/lib/sbi/sbi_illegal_atomic.c index 977a9ad0..30f5118e 100644 --- a/lib/sbi/sbi_illegal_atomic.c +++ b/lib/sbi/sbi_illegal_atomic.c @@ -30,7 +30,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs) { \ register ulong tinfo asm("a3"); \ register ulong mstatus = 0; \ - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ type ret = 0; \ trap->cause = 0; \ asm volatile( \ @@ -57,7 +57,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs) { \ register ulong tinfo asm("a3"); \ register ulong mstatus = 0; \ - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ type ret = 0; \ trap->cause = 0; \ asm volatile( \ diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c index 60becedc..1550d111 100644 --- a/lib/sbi/sbi_unpriv.c +++ b/lib/sbi/sbi_unpriv.c @@ -33,9 +33,9 @@ union sbi_unpriv_data { type sbi_load_##type(const type *addr, \ struct sbi_trap_info *trap) \ { \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong tinfo asm("a3") = (ulong)trap; \ register ulong mstatus = 0; \ - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ type ret = 0; \ trap->cause = 0; \ asm volatile( \ @@ -58,9 +58,9 @@ union sbi_unpriv_data { void sbi_store_##type(type *addr, type val, \ struct sbi_trap_info *trap) \ { \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong tinfo asm("a3") = (ulong)trap; \ register ulong mstatus = 0; \ - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ trap->cause = 0; \ asm volatile( \ "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ @@ -207,7 +207,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap) register ulong tinfo asm("a3"); register ulong ttmp asm("a4"); register ulong mstatus = 0; - register ulong mtvec = (ulong)sbi_hart_expected_trap; + register ulong mtvec = sbi_hart_expected_trap_addr(); ulong insn = 0; trap->cause = 0; From patchwork Thu Aug 27 09:19:20 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Mitchell X-Patchwork-Id: 2293279 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=oqUMWyGS; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linux.spacemit.com header.i=@linux.spacemit.com header.a=rsa-sha256 header.s=mxsw2412 header.b=rZSIWxBc; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hVwwr1T0Gz1xvx for ; Thu, 27 Aug 2026 19:20:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uclPAWhZ8hoUCvKbBh9E25O4bCgdhiQ1RxGrH2FytA0=; b=oqUMWyGSXOvAU1 AjpTugInQzKcLEArj1yZVcPW8WIWmTWu7BEBrIqgFNENTvRvGPNCC2Pq8rIFJZKT5uYgBFuuK+AY6 mlp+oWQHxA2ujhGOi0TsVhj+19Sxb6yoRRV2YM+Mie4Zcdty+nlBouaU0kOxrlIYv8CYgKQ4OC0CX BZ0NUsE6/fO9bXmVViAY1awLb1sH51j5lyOKBgleJx2uVUsY80mA4/+lofDJC0yveJXDzqeoy6amc FixuzGMxV5OYl8cJRKEwG3ftbzM9Zyt+4jGY4J1bZpw94Z4uk33FZJi/lIrZqqnYTnYqRgT0qeUPa 6XPYh+ByDlPpUNmhN8FQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHi-00000003jEk-36te; Thu, 27 Aug 2026 09:20:34 +0000 Received: from smtpbgsg1.qq.com ([54.254.200.92]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHg-00000003j9j-0TWX for opensbi@lists.infradead.org; Thu, 27 Aug 2026 09:20:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.spacemit.com; s=mxsw2412; t=1787822394; bh=NQ8ZpCQCkawJpw387kJiozla274KmChfA8c0DFepuzc=; h=From:Date:Subject:MIME-Version:Message-Id:To; b=rZSIWxBc69PH8ozQPaX8irH/WquMTewXIja7Ns6BbKyr4RkEKWqP4DvQBKVtePIfy hpxkDEE+f+Ce1TJZhL3SWGjplhTVzhZBAhNcDJG3MaZJXppOLkAVCgGdk2G3vlJe86 qnnhIJN0c0G9vZkBBExOsStTp0IhhKvs0RDqxIt8= X-QQ-mid: zesmtpgz9t1787822389tb0f877f0 X-QQ-Originating-IP: xFkEMdyi44h8NNyRJzc5ewI5fnXOiIY/mySFW3JuEqs= Received: from = ( [183.48.244.190]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 27 Aug 2026 17:19:47 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6630494701391274169 EX-QQ-RecipientCnt: 7 From: Troy Mitchell Date: Thu, 27 Aug 2026 17:19:20 +0800 Subject: [PATCH v3 2/5] platform: generic: spacemit: k1: rename cache flush operation MIME-Version: 1.0 Message-Id: <20260827-spacemit-k3-v3-2-5d8dbb68539d@linux.spacemit.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> In-Reply-To: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> To: opensbi@lists.infradead.org Cc: Xianbin Zhu , Anup Patel , Bo Gan , Samuel Holland , Heinrich Schuchardt , Troy Mitchell X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1518; i=troy.mitchell@linux.spacemit.com; h=from:subject:message-id; bh=KKnxI5IvZqgL1LXOJO7MwhdWO7ZF545ykdO4TY3wRTk=; b=owGbwMvMwCU2g/N9w09jE33G02pJDFkTGJX8Z+xWYpcLtdC1kn6a65kRKJLRfFRlsdwfl/etq StP/97UUcrCIMbFICumyNL9gGdbgU+UbYFAoS/MHFYmkCEMXJwCMBGzu4wMOxrn33qSmzmrZdkS 14vL92YX3GurbOza8MrlyIRzO0J3bGb4H6dzXumZv/bsnEfZrW+yl9ins55ymRmxRNMpLWGP/EI VLgA= X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=openpgp; fpr=3FE5535CF1B0E658E57DB59BAE1C2FBEA7DB42E1 X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: NBq/fWjOSzI9T45ao2WH2Rwq1tMIWOWEfXbrVGqEas9ztQbS+iuoIUUn xPe1mvge5UN0VEHRvgpIM6fmkw7tL7urEYM2ExZ/s9+5l76Ve926K2mp2ETx/BpX4Jgt/wi c/KrdBn1xz5J3XveNYWkWzEQ69PZC4FwJzNnV7MH78WrHLIfB4QN8q/wpphvr4NRBAMzwBU kp0gwh5kHsZdbDfDa+hR0OPKGbnniugeoMfEVesJVH702ntkLU3HvyJ2+cAJwuGlSC/dGmV RbUIaJydKjSm1P3fee1h5Nby3+CAmPDZIHCsLoZ6xLyD+paxtHsQiMidMgQvv9eUkTkwgMK 22V0QRXFNo66CV0IVikQHlXxBUQXK2Nutsg8SkknQlvgq8ke1HoNURrzC8XI3E1tqN00fm7 iz1M8VyxqPjeQ9ex3/fq35PR8JVvwkf8/+bs32nEdStdR/LyT1EasdD8A+SQa6IVdISlxVU H/y1lz2VLPAhCS0HrCzcc3yCvsIW66JNLJNkTlOJW3Ko7m4Wkdvl2SfD/5eReP/ZNtd1jUN 7JeFNBZYUbyEWk6bf33ozParWku1lilKuzKEuSlVPhk6fStR4t92FIF7RG/HppBTQPEfnfC PNwNU5WYcUtKGuBs2Kqmi4hnqfsautHMbbRJAif26o5qSNS9rk//EijmCKp2vMHRO/EdCTr 2eqm60WljXwq4rDIvRhwg1RoA3K0lNyPsBu/S6dK9B8vqd5SsJkPgrgDnS29HItZTlhmrfV 70Hemf1vivw6gsXELabpaIiGTKPpw8RvGZkj0jbE8OSQn/7p42LQgozY8EImELnreOAt1d4 zg8NCx5aBNqpRW2KANjSv6WPiwZzHfp0SPsOr+8goAWeOmLtJGcewpzOWMMW15QRPD1XFqX o+OM8UAqY9DKqBZek7Devqnem6yyaErCJdkjx6CTiGFjazKyHT9GPiHY/7j0iLl4cY/Yqje aECF5vbgy+sF8GK3BUu2yrsKM2OvyUinmKLynw+YqKrPjJ8oq3oCHTnt5gP1lHj8O2NBkET uz2v4BtD6bdzNJcTUhMTCaMbYQgw6emcCCCKFzKSpGNEXBeLlusajB1p1phCP+qphCT0e14 wWsxZohLFtr7Y7x7f3B3aceKKAgMVKYmZ/etL3LVeQr/z6XIpiix5A= X-QQ-XMRINFO: NyFYKkN4Ny6FuXrnB5Ye7Aabb3ujjtK+gg== X-QQ-RECHKSPAM: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260827_022032_580396_006A04E4 X-CRM114-Status: UNSURE ( 8.97 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Xianbin Zhu MRAOP_ICACHE_INVALID is used to flush the local D-cache before a hart stops, so the name incorrectly describes I-cache invalidation. Rename it to MRAOP_CACHE_FLUSH without changing its encoded value. Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [54.254.200.92 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy 0.0 RCVD_IN_MSPIKE_H5 RBL: Excellent reputation (+5) [54.254.200.92 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Xianbin Zhu MRAOP_ICACHE_INVALID is used to flush the local D-cache before a hart stops, so the name incorrectly describes I-cache invalidation. Rename it to MRAOP_CACHE_FLUSH without changing its encoded value. Signed-off-by: Xianbin Zhu Co-developed-by: Troy Mitchell Signed-off-by: Troy Mitchell --- lib/utils/hsm/fdt_hsm_spacemit.c | 2 +- platform/generic/include/spacemit/k1.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/utils/hsm/fdt_hsm_spacemit.c b/lib/utils/hsm/fdt_hsm_spacemit.c index 868e49bf..99c52335 100644 --- a/lib/utils/hsm/fdt_hsm_spacemit.c +++ b/lib/utils/hsm/fdt_hsm_spacemit.c @@ -92,7 +92,7 @@ static int spacemit_hart_stop(void) asm volatile ("fence iorw, iorw"); /* flush local dcache */ - csr_write(CSR_MRAOP, MRAOP_ICACHE_INVALID); + csr_write(CSR_MRAOP, MRAOP_CACHE_FLUSH); asm volatile ("fence iorw, iorw"); /* disable dcache */ diff --git a/platform/generic/include/spacemit/k1.h b/platform/generic/include/spacemit/k1.h index 7095bc08..ac727b04 100644 --- a/platform/generic/include/spacemit/k1.h +++ b/platform/generic/include/spacemit/k1.h @@ -20,8 +20,8 @@ /* ECC enable */ #define MSETUP_ECCE BIT(16) -/* icache invalidation */ -#define MRAOP_ICACHE_INVALID GENMASK(1, 0) +/* cache flush */ +#define MRAOP_CACHE_FLUSH GENMASK(1, 0) #define PMU_AP_BASE 0xd4282800 From patchwork Thu Aug 27 09:19:21 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Mitchell X-Patchwork-Id: 2293280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=tc1LkKpj; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linux.spacemit.com header.i=@linux.spacemit.com header.a=rsa-sha256 header.s=mxsw2412 header.b=rgjIn/I4; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hVwww19Mqz1xy0 for ; Thu, 27 Aug 2026 19:20:48 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uxqf4u9SwZt/Noaj0G5iVYGgAXAjPWGZYdNjl4E7JGw=; b=tc1LkKpji2BFtl nQiv6fKuVfe89Ex1wXf3ZF3f20xz5rE5x8uDoOsi9Lfd0MEJ3qv3BbWbz6KtcY40ifIgKRvPl7Ok1 LiGJdqt+ClaEpy8oNHuXeF67DVTJQsXhEtB697dcqlDbzlnfswqxHmYhhXU6q73Y1YSDrPd1p/p2a Q0tEnxTsHBe793mPF59u3WkH+by+vNNvi4rFwezhAlHkaLtDuXyapn2LLfl7STOjcUlLaHOxXSRil tEZN5vRrzm9TD0j9agCf4OIl3hJLmumxt+7yOC/HbWWNAmHGAT6jXOC5/yY3egd7sVdJ3gf/wJMhi z1CLq9kn+y4kWZzR6Q/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHo-00000003jHu-3dB6; Thu, 27 Aug 2026 09:20:40 +0000 Received: from smtpbguseast3.qq.com ([54.243.244.52]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHk-00000003j9t-033t for opensbi@lists.infradead.org; Thu, 27 Aug 2026 09:20:39 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.spacemit.com; s=mxsw2412; t=1787822398; bh=gZhUlOtx+40vljDnWa3grPFjDvNRaXAjawL7GTfVGN8=; h=From:Date:Subject:MIME-Version:Message-Id:To; b=rgjIn/I4WqXX4QV3Ok0L37FdE8OYyfJWUvnEG4feDjBJjf5uh+GQjBf6pq2gitGAg qMUWipX/H36rjOhfElYzHMi0Kd3pLsoNYG3SBHsB07QWnfRx9t63v/5stHLbIcwdaq ODgbZfniS3thpc914YpDQzY+nfXVnKSNQ1HSnaAw= X-QQ-mid: zesmtpgz9t1787822393taf8334f5 X-QQ-Originating-IP: SRUSFoiranbySerlCjeYFxGpPXPpzOAzquFjTbaYNO0= Received: from = ( [183.48.244.190]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 27 Aug 2026 17:19:51 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 18410997541741688107 EX-QQ-RecipientCnt: 7 From: Troy Mitchell Date: Thu, 27 Aug 2026 17:19:21 +0800 Subject: [PATCH v3 3/5] platform: generic: spacemit: k1: move hart init to nascent hook MIME-Version: 1.0 Message-Id: <20260827-spacemit-k3-v3-3-5d8dbb68539d@linux.spacemit.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> In-Reply-To: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> To: opensbi@lists.infradead.org Cc: Xianbin Zhu , Anup Patel , Bo Gan , Samuel Holland , Heinrich Schuchardt , Troy Mitchell X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1889; i=troy.mitchell@linux.spacemit.com; h=from:subject:message-id; bh=bLvPHNeA9VO+U4Hb6Myt/OCxjtrEsU6YOtleOY/qizk=; b=owGbwMvMwCU2g/N9w09jE33G02pJDFkTGJXXPIxd8v7M9QlWd9s32b2fIS3Vt31aea8bv8X1J zx7todJdZSyMIhxMciKKbJ0P+DZVuATZVsgUOgLM4eVCWQIAxenAEzk0lZGhvaJHtq91npxs3R9 3JPWzVsq87Ly99wJlztjNyibfvlSeIbhn4rz25dT4z4KLpn4Jnpa+9wP3P9zzrLn73hxMuxX2qW vtWwA X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=openpgp; fpr=3FE5535CF1B0E658E57DB59BAE1C2FBEA7DB42E1 X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: OEqAExJEtBsfXDgnyInLVNDM7+Pyx5rb0+MwDTMZQB82zslPfvP2s1i5 0pfgRD1rpa9KaRxJiM63fsAlaJltoQSwZHHUpswKHHelWUdtgujjAPDqnTmJsf58f3vKS0l 87XFHeAWnCGe2WrXewsbhUG8Wq7JAMAP4JIxYfQgh0R8Ms1VGhG1t0O5pacVeyKHn9VwoLp K8Hzh0vrD5278P3tsbfrvVeK5qYpc5J95+5RER1jvJRM8H2FUM2hkc/pQRRc0WmDzNSUrpy rKvaWZkq7OnL4aediyK7A91lwpmHZ5IDQr3vuT3w6Yt1fPZOhRYyiWCOhW2KGULY8a/uaAU Nrltiy/csnsQOlja8za9W4r6SAhTHTkzivnRok9LTNRp0hYp8qDKL5oZUn5Ck43T84qzYhb 5mG/iHMcjP8s2j1XU8Vu3cz9aY3M4rM7E1wnpadaO/ohaWylcTWAxyVvZczeh0aorHl9Fgb HEQ1Ebp0NT0Fz0EP8B+Quzjvhou6k5dQKMUcIOuwLM8naozcQHJyDpf39BdsrWe2rR3G0B8 EmM4pXyufSxLLrrj044sB4my+sosElRHuAL9naLnIguIB2pnYdV+tAem2ueAYSMVmDbf211 pOSYO7rFS4ift9Bu7es6EE+wJ0AmGM1jlmuGqPX+blNInyoVgONWslFNXLstPcJa96Uql2K xAAg0dSWBYz4nWoEYKRzgzhlzAu6xKo8oExhrYm5G9YJ4V37i68xcM+maxdS1EjdRRGPowV HCS+xzAp0gMKW8RFCY5k3ybj2tT0eZ/CCeqmbOc0XgLngN7Das0ELQYecmBhkE5PkQrAqwW RawRs1lOLoUvoHVngYFHIi+u8A+h3Bb1RmM/PwfI8zhkJBORm2g3JTsOzoZC6FydEmMAdvA MMsTKe189J8IP4nsVAof8c3Pz8vpU0N81Qd20ptV2PcwKTC7g42AB7IGUhO+C0IZ7h9gfCd ADMZRxaHzo53AL7k30HFTd7De6i2yoAq2dgQxuFV17qdPuGrUU2V8clGE6SEMGqhGBcsRhV CBxogIJiNLh/BH/oRuMH2n/TXOD0yGn/z0qaQVaMnlse6pWSr6sFEE56j1i4Mi3lSyBlgpZ XkknoZ8Ubhm/6PGRiI4btecjeP8vnJA2gO6XLwX5KLJ X-QQ-XMRINFO: NyFYKkN4Ny6FuXrnB5Ye7Aabb3ujjtK+gg== X-QQ-RECHKSPAM: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260827_022036_605609_7C8774FE X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: cold_boot_allowed() is a policy query and should not modify per-hart state. The K1 callback currently programs ML2SETUP as a side effect. Move the ML2SETUP programming to nascent_init(), which runs on every hart before common initialization. Chain generic_nascent_init() to keep the generic per-hart setup intact. Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [54.243.244.52 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy 0.0 RCVD_IN_MSPIKE_H5 RBL: Excellent reputation (+5) [54.243.244.52 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org cold_boot_allowed() is a policy query and should not modify per-hart state. The K1 callback currently programs ML2SETUP as a side effect. Move the ML2SETUP programming to nascent_init(), which runs on every hart before common initialization. Chain generic_nascent_init() to keep the generic per-hart setup intact. Fixes: 1f84ec2ac22e ("platform: generic: spacemit: add K1") Reported-by: Bo Gan Link: https://lore.kernel.org/r/56220293-88e3-451f-833e-8251656a83d9@gmail.com Signed-off-by: Troy Mitchell Reviewed-by: Bo Gan --- platform/generic/spacemit/k1.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/platform/generic/spacemit/k1.c b/platform/generic/spacemit/k1.c index 7ee5f17a..19a9b27c 100644 --- a/platform/generic/spacemit/k1.c +++ b/platform/generic/spacemit/k1.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -86,16 +87,23 @@ static int spacemit_k1_early_init(bool cold_boot) return 0; } -static bool spacemit_cold_boot_allowed(u32 hartid) +static int spacemit_k1_nascent_init(void) { - csr_set(CSR_ML2SETUP, 1 << (hartid % PLATFORM_MAX_CPUS_PER_CLUSTER)); + csr_set(CSR_ML2SETUP, + 1 << (current_hartid() % PLATFORM_MAX_CPUS_PER_CLUSTER)); + + return generic_nascent_init(); +} +static bool spacemit_cold_boot_allowed(u32 hartid) +{ return !hartid; } static int spacemit_k1_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match) { + generic_platform_ops.nascent_init = spacemit_k1_nascent_init; generic_platform_ops.early_init = spacemit_k1_early_init; generic_platform_ops.cold_boot_allowed = spacemit_cold_boot_allowed; From patchwork Thu Aug 27 09:19:22 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Mitchell X-Patchwork-Id: 2293281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=LOaYMupf; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linux.spacemit.com header.i=@linux.spacemit.com header.a=rsa-sha256 header.s=mxsw2412 header.b=D22TGB7d; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hVwx53VdLz1xtd for ; Thu, 27 Aug 2026 19:20:57 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=i5UG/9LDBQABi3DeNqZ+rFjR3pdtvzdiP4C9C99kbIE=; b=LOaYMupf1+3M+K O0dAJc+1EZl6ddnIVrtBk8R/vvYRjScNS4qHZGXuTJVNKyrQ1AIisGvTGNndgsVqSWnhkht94axVH pXPVm+56k7zO1bCq+auX7jpaOpT5EAkorJjjFe8hFC0saVO/ugHJXPSQrx0ewqyfefaqJSn/gUTqX 0GzliJfEofKNhMkVFItEzbTShuS1y5APY6efk0aJ1TIVF0VgjdcBuf1SHdgqwaDYGksGMCbejSPCH lub1S0yFRvVAWe0XvK0zBO6z8hD0q1KR6HygWoL1+6dC/HXzHl56MSWoj573+0otMKk4iKu7z0OMm 9fetXGmNT199x1Qs1+Lg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHz-00000003jNH-0615; Thu, 27 Aug 2026 09:20:51 +0000 Received: from smtpbgsg2.qq.com ([54.254.200.128]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHw-00000003jGN-1iTf for opensbi@lists.infradead.org; Thu, 27 Aug 2026 09:20:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.spacemit.com; s=mxsw2412; t=1787822402; bh=Xx/5ajFGP7qIlOIa7fRzcn6GBWuFzUv4y/HMXZz8AVo=; h=From:Date:Subject:MIME-Version:Message-Id:To; b=D22TGB7d/ASDj//CVaoAx53sdvoFqPjAOTcGndP7XFBDjIwwVnJqPxNlT+ApfjUn2 aWGWGzXsm2u+CdykTPj/eEfJCIqvdGEtfZqDBkigKborbIxyEOK9kecz3Oj/Piknul aqq4VruYp+nzQ3hc9s9Gl4V3yIzKzRuz3tss33SQ= X-QQ-mid: esmtpgz10t1787822397te83433bb X-QQ-Originating-IP: oF+YfWXL9/lgW0hFINNu7NPv6aslP+1MER1sPlzcCXY= Received: from = ( [183.48.244.190]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 27 Aug 2026 17:19:55 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6692813601542871560 EX-QQ-RecipientCnt: 7 From: Troy Mitchell Date: Thu, 27 Aug 2026 17:19:22 +0800 Subject: [PATCH v3 4/5] platform: generic: spacemit: k1: refactor platform support MIME-Version: 1.0 Message-Id: <20260827-spacemit-k3-v3-4-5d8dbb68539d@linux.spacemit.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> In-Reply-To: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> To: opensbi@lists.infradead.org Cc: Xianbin Zhu , Anup Patel , Bo Gan , Samuel Holland , Heinrich Schuchardt , Troy Mitchell X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15129; i=troy.mitchell@linux.spacemit.com; h=from:subject:message-id; bh=ikHNXupmAMt03x3ODGF/E4NamiEuwgYrJuJZRUxOKM8=; b=kA0DAAoWmAnvgPkzNC8ByyZiAGqQASShZkwHnjEvf20Lv5WCSMGBJdyCm1wLUdUBUpU8KPw9L oh1BAAWCgAdFiEEi+AMtnBMWj1wEHFNmAnvgPkzNC8FAmqQASQACgkQmAnvgPkzNC88KwD9FOlE jlpGM1oXCBa7wX8iT7zmuncgC+MxMAYLxmdW87UA/ibrkY1jdyeg9pk/z7DckHWaEVg8hwx4GxT hOdvT8eMP X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=openpgp; fpr=3FE5535CF1B0E658E57DB59BAE1C2FBEA7DB42E1 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: NqEoO4JFgyuDe/52MRp8HlNXfaVGy6y8uqyA3GxxslkWypgY5J6E9n1n fXcf6QZNXlE5jFsKQAQQDI0okX5D9/o/Au27q8pISk82naLBvFaE6ZdqfP+3Q6tdc6XArKf xCznbrd99prprRCzvT0UwkCBxvfTBE5e7+V9wdhjRmuJ3GnTd2wW93X7TsAinCyPgLP+mg3 OLzSmHTluIUSu4uyuYh/h1W5CQnpLzg7zaKrP13AbIUmm4C61gq/o60n/benbpBJ5fQixsS /Y+XPP2efOpkHRYThpn8j1Mqd4pLEvGJBBd078sABK3K/vFNCaWUc//MFuypBOHf92HA71F UKLJHHRG3sImr8tx6y+PZYXrE3//qL0R+ViuFPdsq5NBnA+ZYumTVwDJu5IkjAlrr6RKUr/ GKbcbkbB/gbXhJ6zskvJUvVYfmKEGnwnLOuV1ryC/oguRpUZtcXUG7BH2yvrS8bzGyR70YX JdwWDl8Z79AtDdIRJAKwUNfqkGhuunfehNhqNvVfFhlUFk69t1e1BTbxQKIwFYJ4/mlEGVb AgjEpfrrs4+pb/OiFg9MotoSFHJeGy2QWUnQQxNPjwL2g8E81oE6EcmKc+aGEiPrZxNbOLZ K3ijXEdEjw8WYO9Xu1nFBFgUKPWJ4AePRXpf0dwmBooL5XuZQTJa5gmqwwh3i2kASaK3+b3 HSsE4hS3+kNYhNQODRagFWSWgCur6nszUedfWV8tARvcPCqrk1fflUd40ZI6r78bDvHPauI XOlzBNUKlRHySTtnI27J6f2vX42SVK05Sivd9uf1ToIGc7WssrY9x3Pf/XRSG9jvAlTT+LM L9gMUeoAB67jCp9dzJaFkhZWu0ACgewspO8uZ89+5wAf5eCOmmCSkdehu0kdkcn2+x5WZVy FTufEgy1JQ0wa0KhgJjTdstHYmbxuwV36CcGW7IMAblNo46IqSneAPghofxksfcgHZ0H+S2 P8A1TC/svkGG7vk8BrzkUxTR0+iAXp9bV/7+8qXGigN7reaLQa7LsqqdBjHML9liyFnvb7t nKwFDYDYFhM465G9R51B9EVDdnxb5zRePJdf3obU9YcU9L9VwUwXyWFh146DIGNMV1PR4gn EgtTArBAO1Irbt1AVpcOM+WIg8o2RN1ra8pFccxeolQ X-QQ-XMRINFO: NI4Ajvh11aEjEMj13RCX7UuhPEoou2bs1g== X-QQ-RECHKSPAM: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260827_022048_855357_080814AF X-CRM114-Status: GOOD ( 18.35 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Xianbin Zhu K3 shares cache-control CSRs, PMU idle fields, cluster sizing, and the CCI-550 programming sequence with K1. Keeping these definitions and the CCI helper in K1-specific files would either duplicate th [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [54.254.200.128 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [54.254.200.128 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Xianbin Zhu K3 shares cache-control CSRs, PMU idle fields, cluster sizing, and the CCI-550 programming sequence with K1. Keeping these definitions and the CCI helper in K1-specific files would either duplicate them or make K3 depend on K1 support. Add a hidden PLATFORM_SPACEMIT option and move the shared definitions to spacemit/common.h. Move cci_enable_snoop_dvm_reqs() to spacemit.c while keeping each SoC's CCI topology and boot flow in its own platform driver. Rename the PMU idle fields to match the K1 and K3 User Manuals. Keep the K1 power-down mask at 0x1b, so K1 power-management behavior remains unchanged. Keep the K1 HSM implementation K1-specific and switch it to the shared definitions. This is a non-functional refactoring that prepares the common support used by K3. Signed-off-by: Xianbin Zhu Co-developed-by: Troy Mitchell Signed-off-by: Troy Mitchell --- lib/utils/hsm/fdt_hsm_spacemit.c | 10 +-- platform/generic/Kconfig | 4 ++ platform/generic/include/spacemit/common.h | 86 +++++++++++++++++++++++++ platform/generic/include/spacemit/k1.h | 94 +++++----------------------- platform/generic/include/spacemit/spacemit.h | 14 +++++ platform/generic/spacemit/k1.c | 33 ++-------- platform/generic/spacemit/objects.mk | 1 + platform/generic/spacemit/spacemit.c | 36 +++++++++++ 8 files changed, 169 insertions(+), 109 deletions(-) diff --git a/lib/utils/hsm/fdt_hsm_spacemit.c b/lib/utils/hsm/fdt_hsm_spacemit.c index 99c52335..6348f6a3 100644 --- a/lib/utils/hsm/fdt_hsm_spacemit.c +++ b/lib/utils/hsm/fdt_hsm_spacemit.c @@ -10,6 +10,7 @@ #include #include #include +#include #include static const u64 cpu_wakeup_reg[] = { @@ -42,9 +43,9 @@ static inline void spacemit_set_cpu_power(u32 hartid, bool enable) value = readl(cpu_idle_base); if (enable) - value &= ~PMU_AP_IDLE_PWRDOWN_MASK; + value &= ~PMU_AP_IDLE_PWRDOWN_K1_MASK; else - value |= PMU_AP_IDLE_PWRDOWN_MASK; + value |= PMU_AP_IDLE_PWRDOWN_K1_MASK; writel(value, cpu_idle_base); } @@ -87,7 +88,7 @@ static int spacemit_hart_stop(void) csr_write(CSR_STIMECMP, GENMASK_ULL(63, 0)); csr_clear(CSR_MIE, MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | MIP_SEIP | MIP_MEIP); - /* disable data preftch */ + /* disable data prefetch */ csr_clear(CSR_MSETUP, MSETUP_PFE); asm volatile ("fence iorw, iorw"); @@ -102,8 +103,7 @@ static int spacemit_hart_stop(void) /* * Core4-7 do not have dedicated bits in ML2SETUP; * instead, they reuse the same bits as core0-3. - * - * Thereforspacemit_deassert_cpue, use modulo with PLATFORM_MAX_CPUS_PER_CLUSTER + * Therefore, use modulo with PLATFORM_MAX_CPUS_PER_CLUSTER * to select the proper bit. */ csr_clear(CSR_ML2SETUP, 1 << (current_hartid() % PLATFORM_MAX_CPUS_PER_CLUSTER)); diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index d594b140..958610d3 100644 --- a/platform/generic/Kconfig +++ b/platform/generic/Kconfig @@ -100,9 +100,13 @@ config PLATFORM_THEAD select THEAD_C9XX_PMU default n +config PLATFORM_SPACEMIT + bool + config PLATFORM_SPACEMIT_K1 bool "Spacemit K1 support" select FDT_HSM_SPACEMIT + select PLATFORM_SPACEMIT default n config CPU_MIPS_P8700 diff --git a/platform/generic/include/spacemit/common.h b/platform/generic/include/spacemit/common.h new file mode 100644 index 00000000..317bb3e9 --- /dev/null +++ b/platform/generic/include/spacemit/common.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2025 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + +#ifndef __RISCV_SPACEMIT_COMMON_H__ +#define __RISCV_SPACEMIT_COMMON_H__ + +#include + +#define CSR_MSETUP 0x7c0 +#define CSR_ML2SETUP 0x7f0 + +/* dcache enable */ +#define MSETUP_DE BIT(0) +/* icache enable */ +#define MSETUP_IE BIT(1) +/* branch prediction enable */ +#define MSETUP_BPE BIT(4) +/* prefetch functionality enable */ +#define MSETUP_PFE BIT(5) +/* misaligned memory access enable */ +#define MSETUP_MME BIT(6) +/* ECC enable */ +#define MSETUP_ECCE BIT(16) + +#define PMU_AP_BASE 0xd4282800 + +#define PMU_AP_CORE0_WAKEUP (PMU_AP_BASE + 0x12c) +#define PMU_AP_CORE1_WAKEUP (PMU_AP_BASE + 0x130) +#define PMU_AP_CORE2_WAKEUP (PMU_AP_BASE + 0x134) +#define PMU_AP_CORE3_WAKEUP (PMU_AP_BASE + 0x138) +#define PMU_AP_CORE4_WAKEUP (PMU_AP_BASE + 0x324) +#define PMU_AP_CORE5_WAKEUP (PMU_AP_BASE + 0x328) +#define PMU_AP_CORE6_WAKEUP (PMU_AP_BASE + 0x32c) +#define PMU_AP_CORE7_WAKEUP (PMU_AP_BASE + 0x330) + +#define PMU_AP_CORE0_IDLE_CFG (PMU_AP_BASE + 0x124) +#define PMU_AP_CORE1_IDLE_CFG (PMU_AP_BASE + 0x128) +#define PMU_AP_CORE2_IDLE_CFG (PMU_AP_BASE + 0x160) +#define PMU_AP_CORE3_IDLE_CFG (PMU_AP_BASE + 0x164) +#define PMU_AP_CORE4_IDLE_CFG (PMU_AP_BASE + 0x304) +#define PMU_AP_CORE5_IDLE_CFG (PMU_AP_BASE + 0x308) +#define PMU_AP_CORE6_IDLE_CFG (PMU_AP_BASE + 0x30c) +#define PMU_AP_CORE7_IDLE_CFG (PMU_AP_BASE + 0x310) + +/* boot entry for X100 clusters (C0, C1) */ +#define C0_RVBADDR_LO_ADDR 0xd4282db0 +#define C0_RVBADDR_HI_ADDR 0xd4282db4 +#define C1_RVBADDR_LO_ADDR 0xd4282eb0 +#define C1_RVBADDR_HI_ADDR 0xd4282eb4 + +/* CCI-550 base and slave interface layout */ +#define CCI_550_PLATFORM_CCI_ADDR 0xd8500000 +#define CCI_550_STATUS 0x000c +#define CCI_550_STATUS_CHANGE_PENDING BIT(0) +#define CCI_550_SLAVE_IFACE0_OFFSET 0x1000 +#define CCI_550_SLAVE_IFACE_OFFSET(idx) \ + (CCI_550_SLAVE_IFACE0_OFFSET + ((0x1000) * (idx))) +#define CCI_550_SNOOP_CTRL 0x0000 +#define CCI_550_SNOOP_CTRL_ENABLE_SNOOPS BIT(0) +#define CCI_550_SNOOP_CTRL_ENABLE_DVMS BIT(1) + +/* + * PMU AP per-core idle control register bits (PMU_AP_COREn_IDLE_CFG). + * Bit definitions are identical in K1 and K3 User Manuals. + * These replace the original ad-hoc names from k1.h (which incorrectly + * called bit 1 SRAM_PWRDWN, bit 3 WAKE_MCE, and bit 4 MC_SW_REQ). + */ +/* bit 0: CORE_IDLE - gate core clock externally when core enters WFI */ +#define PMU_AP_IDLE_CORE_IDLE BIT(0) +/* bit 1: CORE_PWRDWN - power off core on WFI (requires CORE_IDLE set) */ +#define PMU_AP_IDLE_CORE_PWRDWN BIT(1) +/* bit 2: Core L1 SRAM Power Down - reserved/not used in K1 and K3 */ +#define PMU_AP_IDLE_CORE_L1_SRAM_PWRDWN BIT(2) +/* bit 3: MASK_GIC_NIRQ_TO_CORE - mask nIRQ from GIC, auto-cleared by HW on power-down entry */ +#define PMU_AP_IDLE_MASK_GIC_NIRQ BIT(3) +/* bit 4: MASK_GIC_NFIQ_TO_CORE - mask nFIQ from GIC, auto-cleared by HW on power-down entry */ +#define PMU_AP_IDLE_MASK_GIC_NFIQ BIT(4) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 + +#endif /* __RISCV_SPACEMIT_COMMON_H__ */ diff --git a/platform/generic/include/spacemit/k1.h b/platform/generic/include/spacemit/k1.h index ac727b04..662b42e5 100644 --- a/platform/generic/include/spacemit/k1.h +++ b/platform/generic/include/spacemit/k1.h @@ -1,88 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2025 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + #ifndef __RISCV_SPACEMIT_K1_H__ #define __RISCV_SPACEMIT_K1_H__ -#define CSR_MSETUP 0x7c0 -#define CSR_MHCR 0x7c1 -#define CSR_MRAOP 0x7c2 -#define CSR_MHINT 0x7c5 -#define CSR_ML2SETUP 0x7f0 +#include -/* decache enable */ -#define MSETUP_DE BIT(0) -/* icache enable */ -#define MSETUP_IE BIT(1) -/* branch prediction enable */ -#define MSETUP_BPE BIT(4) -/* prefetch functionality enable */ -#define MSETUP_PFE BIT(5) -/* misaligned memory access enable */ -#define MSETUP_MME BIT(6) -/* ECC enable */ -#define MSETUP_ECCE BIT(16) +#define CSR_MRAOP 0x7c2 -/* cache flush */ #define MRAOP_CACHE_FLUSH GENMASK(1, 0) -#define PMU_AP_BASE 0xd4282800 - -#define PMU_AP_CORE0_WAKEUP (PMU_AP_BASE + 0x12c) -#define PMU_AP_CORE1_WAKEUP (PMU_AP_BASE + 0x130) -#define PMU_AP_CORE2_WAKEUP (PMU_AP_BASE + 0x134) -#define PMU_AP_CORE3_WAKEUP (PMU_AP_BASE + 0x138) -#define PMU_AP_CORE4_WAKEUP (PMU_AP_BASE + 0x324) -#define PMU_AP_CORE5_WAKEUP (PMU_AP_BASE + 0x328) -#define PMU_AP_CORE6_WAKEUP (PMU_AP_BASE + 0x32c) -#define PMU_AP_CORE7_WAKEUP (PMU_AP_BASE + 0x330) - -#define PMU_AP_CORE0_IDLE_CFG (PMU_AP_BASE + 0x124) -#define PMU_AP_CORE1_IDLE_CFG (PMU_AP_BASE + 0x128) -#define PMU_AP_CORE2_IDLE_CFG (PMU_AP_BASE + 0x160) -#define PMU_AP_CORE3_IDLE_CFG (PMU_AP_BASE + 0x164) -#define PMU_AP_CORE4_IDLE_CFG (PMU_AP_BASE + 0x304) -#define PMU_AP_CORE5_IDLE_CFG (PMU_AP_BASE + 0x308) -#define PMU_AP_CORE6_IDLE_CFG (PMU_AP_BASE + 0x30c) -#define PMU_AP_CORE7_IDLE_CFG (PMU_AP_BASE + 0x310) - -/* power down */ -#define PMU_AP_IDLE_PWRDWN BIT(0) -/* sram power down */ -#define PMU_AP_IDLE_SRAM_PWRDWN BIT(1) -/* enable wake up the memory controller */ -#define PMU_AP_IDLE_WAKE_MCE BIT(3) -/* disable memory controller software req */ -#define PMU_AP_IDLE_MC_SW_REQ BIT(4) - -#define PMU_AP_IDLE_PWRDOWN_MASK (PMU_AP_IDLE_PWRDWN | PMU_AP_IDLE_SRAM_PWRDWN | \ - PMU_AP_IDLE_WAKE_MCE | PMU_AP_IDLE_MC_SW_REQ) -/* cci */ -#define C0_RVBADDR_LO_ADDR 0xd4282db0 -#define C0_RVBADDR_HI_ADDR 0xd4282db4 -#define C1_RVBADDR_LO_ADDR 0xd4282eb0 -#define C1_RVBADDR_HI_ADDR 0xd4282eb4 - -#define CCI_550_PLATFORM_CCI_ADDR 0xd8500000 - -/* relative to cci base */ -#define CCI_550_STATUS 0x000c -/* status register bits */ -#define CCI_550_STATUS_CHANGE_PENDING BIT(0) - -/* slave interface registers */ -#define CCI_550_SLAVE_IFACE0_OFFSET 0x1000 -#define CCI_550_SLAVE_IFACE_OFFSET(idx) (CCI_550_SLAVE_IFACE0_OFFSET + ((0x1000) * (idx))) - -/* relative to slave interface base */ -#define CCI_550_SNOOP_CTRL 0x0000 -/* snoop control register bits */ -#define CCI_550_SNOOP_CTRL_ENABLE_SNOOPS BIT(0) -#define CCI_550_SNOOP_CTRL_ENABLE_DVMS BIT(1) +#define PMU_AP_IDLE_PWRDOWN_K1_MASK (PMU_AP_IDLE_CORE_IDLE | \ + PMU_AP_IDLE_CORE_PWRDWN | \ + PMU_AP_IDLE_MASK_GIC_NIRQ | \ + PMU_AP_IDLE_MASK_GIC_NFIQ) -/* clusters and CPU mapping */ -#define PLATFORM_MAX_CPUS 8 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 #define CPU_TO_CLUSTER(cpu) ((cpu) / PLATFORM_MAX_CPUS_PER_CLUSTER) -#define PLAT_CCI_CLUSTER0_IFACE_IX 0 -#define PLAT_CCI_CLUSTER1_IFACE_IX 1 +#define PLAT_CCI_K1_CLUSTER0_IFACE_IX 0 +#define PLAT_CCI_K1_CLUSTER1_IFACE_IX 1 -#endif +#endif /* __RISCV_SPACEMIT_K1_H__ */ diff --git a/platform/generic/include/spacemit/spacemit.h b/platform/generic/include/spacemit/spacemit.h new file mode 100644 index 00000000..671cfd05 --- /dev/null +++ b/platform/generic/include/spacemit/spacemit.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2025 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + +#ifndef __RISCV_SPACEMIT_H__ +#define __RISCV_SPACEMIT_H__ + +void cci_enable_snoop_dvm_reqs(const int *cci_map, unsigned int master_id); + +#endif diff --git a/platform/generic/spacemit/k1.c b/platform/generic/spacemit/k1.c index 19a9b27c..323239e0 100644 --- a/platform/generic/spacemit/k1.c +++ b/platform/generic/spacemit/k1.c @@ -12,37 +12,16 @@ #include #include #include +#include + +#define PLATFORM_MAX_CPUS 8 /* only use 0-1 cluster in SpacemiT K1 */ static const int cci_map[] = { - PLAT_CCI_CLUSTER0_IFACE_IX, - PLAT_CCI_CLUSTER1_IFACE_IX, + PLAT_CCI_K1_CLUSTER0_IFACE_IX, + PLAT_CCI_K1_CLUSTER1_IFACE_IX, }; -static void cci_enable_snoop_dvm_reqs(unsigned int master_id) -{ - int slave_if_id = cci_map[master_id]; - - /* - * Enable Snoops and DVM messages, no need for Read/Modify/Write as - * rest of bits are write ignore - */ - writel(CCI_550_SNOOP_CTRL_ENABLE_DVMS | CCI_550_SNOOP_CTRL_ENABLE_SNOOPS, - (void *)(u64)CCI_550_PLATFORM_CCI_ADDR + - CCI_550_SLAVE_IFACE_OFFSET(slave_if_id) + CCI_550_SNOOP_CTRL); - - /* - * Wait for the completion of the write to the Snoop Control Register - * before testing the change_pending bit - */ - mb(); - - /* Wait for the dust to settle down */ - while ((readl((void *)(u64)CCI_550_PLATFORM_CCI_ADDR + CCI_550_STATUS) & - CCI_550_STATUS_CHANGE_PENDING)) - ; -} - static void spacemit_k1_pre_init(void) { unsigned int clusterid, cluster_enabled = 0; @@ -62,7 +41,7 @@ static void spacemit_k1_pre_init(void) if (!(cluster_enabled & (1 << clusterid))) { cluster_enabled |= 1 << clusterid; - cci_enable_snoop_dvm_reqs(clusterid); + cci_enable_snoop_dvm_reqs(cci_map, clusterid); } } } diff --git a/platform/generic/spacemit/objects.mk b/platform/generic/spacemit/objects.mk index dcb37867..8309ad1f 100644 --- a/platform/generic/spacemit/objects.mk +++ b/platform/generic/spacemit/objects.mk @@ -2,5 +2,6 @@ # SPDX-License-Identifier: BSD-2-Clause # +platform-objs-$(CONFIG_PLATFORM_SPACEMIT) += spacemit/spacemit.o carray-platform_override_modules-$(CONFIG_PLATFORM_SPACEMIT_K1) += spacemit_k1 platform-objs-$(CONFIG_PLATFORM_SPACEMIT_K1) += spacemit/k1.o diff --git a/platform/generic/spacemit/spacemit.c b/platform/generic/spacemit/spacemit.c new file mode 100644 index 00000000..a215c1ad --- /dev/null +++ b/platform/generic/spacemit/spacemit.c @@ -0,0 +1,36 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + +#include +#include +#include + +void cci_enable_snoop_dvm_reqs(const int *cci_map, unsigned int master_id) +{ + int slave_if_id = cci_map[master_id]; + + /* + * Enable Snoops and DVM messages, no need for Read/Modify/Write as + * rest of bits are write ignore + */ + writel(CCI_550_SNOOP_CTRL_ENABLE_DVMS | CCI_550_SNOOP_CTRL_ENABLE_SNOOPS, + (void *)(unsigned long)CCI_550_PLATFORM_CCI_ADDR + + CCI_550_SLAVE_IFACE_OFFSET(slave_if_id) + CCI_550_SNOOP_CTRL); + + /* + * Wait for the completion of the write to the Snoop Control Register + * before testing the change_pending bit + */ + mb(); + + /* Wait for the dust to settle down */ + while (readl((void *)(unsigned long)CCI_550_PLATFORM_CCI_ADDR + CCI_550_STATUS) & + CCI_550_STATUS_CHANGE_PENDING) + ; +} From patchwork Thu Aug 27 09:19:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Mitchell X-Patchwork-Id: 2293282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=b7WqF1Su; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linux.spacemit.com header.i=@linux.spacemit.com header.a=rsa-sha256 header.s=mxsw2412 header.b=nuORd13/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hVwxF0XgKz1xvx for ; Thu, 27 Aug 2026 19:21:05 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=s7HScjGusqcqaWZLjJAd9cfb4uh2y5NJ4xOt/U+1Zxk=; b=b7WqF1Su6ysrLU 7764wJY0vfioRVMDjA3HQoKIrfPvL28Cw1X+5TZTLwlg50wqxsZ9pdnBjfV6tdVR7QmRRvXxzvUlx AyeK1e1PytwpmRxrU8zL2ieAt7NFrh0M6gS9KN2RueoXCsGTaDAX9JoBjZJnOMoYNBf0taRM82Lbv q//Djx4CcSWWI9cn42USR7YXtlxsEfOxygyxEnmEK3Vq/8Qyh4Hh2SwLWG4QnQEy93cAG6X3OehO6 eRM7RMnhhyU592P4zGweNanzGxEQRPHgXdDLZ5KIO8b54/CZjcHwsuoLjTNJF+YCQdXBbHwoHh94M cMAl9gjqR1GI6L1ytr8A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWI5-00000003jPu-3vXB; Thu, 27 Aug 2026 09:20:57 +0000 Received: from smtpbguseast1.qq.com ([54.204.34.129]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzWHz-00000003jGv-1mOd for opensbi@lists.infradead.org; Thu, 27 Aug 2026 09:20:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.spacemit.com; s=mxsw2412; t=1787822408; bh=JadZrYiUWDTfhM1yeb5p8sAqtYIEivEfCdNWZ3ydRbs=; h=From:Date:Subject:MIME-Version:Message-Id:To; b=nuORd13/UkMTfq73fONDuxKy20Nr/FFkeo/80N3qdvhkxAVTE2b/fxXujJ+Fyoxyb Mnk2MPrbCWD0Lz9c3cYntMeiD7bOwPfOxlw7R8hSHm6l1ebh9LoMNyrd3YeM80XsfN 4eoQrX80ViEMjDbyqgXXX6iUZna/WO6xQ0ZrWSY4= X-QQ-mid: zesmtpgz8t1787822402t536be674 X-QQ-Originating-IP: 9exyCKnF5fPxO0CEKS5VmstQGPgM3UN6ZWjDLMCXWQI= Received: from = ( [183.48.244.190]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 27 Aug 2026 17:20:00 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 3216477611556918320 EX-QQ-RecipientCnt: 7 From: Troy Mitchell Date: Thu, 27 Aug 2026 17:19:23 +0800 Subject: [PATCH v3 5/5] platform: generic: spacemit: k3: add platform support MIME-Version: 1.0 Message-Id: <20260827-spacemit-k3-v3-5-5d8dbb68539d@linux.spacemit.com> References: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> In-Reply-To: <20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com> To: opensbi@lists.infradead.org Cc: Xianbin Zhu , Anup Patel , Bo Gan , Samuel Holland , Heinrich Schuchardt , Troy Mitchell X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=23892; i=troy.mitchell@linux.spacemit.com; h=from:subject:message-id; bh=Urg7fyoI3zRZ7hlXSASCRAm7uAOTxdR6OBjOSMp4XtY=; b=owGbwMvMwCU2g/N9w09jE33G02pJDFkTGNWENx2ze/+mZP9Ci9e87A7+26ztVp30P2zA6ef9f N9xE6PyjlIWBjEuBlkxRZbuBzzbCnyibAsECn1h5rAygQxh4OIUgIn8MWBkOHGJN1DbaWo4q1bk Ur0vTwU9JWPmVh0ySfjwbONW3cDGRQz/7DcI16+1umM3weTWYcvi9P3sYnYvA1PWp8rvev+xzOE NLwA= X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=openpgp; fpr=3FE5535CF1B0E658E57DB59BAE1C2FBEA7DB42E1 X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: NraQz1liAV4N+iPObqCvYAPOgRKos+GMTzA7kWN87xOnNgU4FJ6Tvpvb 3rRHh4u9ONcIUNZCSI8bhEjT4PS98V3kolYGhS/7eCwOPWi7A4JT0S3n/mIJgx+Dejcbtzz hoHDLlgyN4GGfz/3rbDaIZfuj+5gU75oPrUiOCtyYlCzaHRqEhABluDGT9wO3YH9Jgsw4/b GdvU/3rIIfmhDev8l2YNbhelNn9sPiwNJz2S7wjcO7QLXiTJBEA6LUmrSZU+WBDZEY0otFF lDL2ywMbLlenNKEv6obaZJNIkzKTZK84TZkirGnbGSDG0ofYAXWsqCTuE3VzFU56Hv5mScB luPfW2RgW6qiMYZfgwPZKOR4T22FyGmgS/IudF8cq1mWqhGNgiONK1O4VQ6hln8vEeWYVUS Zj/oLequSkgrTKPtluG9tDTZnPjqZzRAgRm8A2UpKrZuOaGTOe26WpBGJZQlenpCeHEJKYo jSoHysUkSjfhH8z9samXjirCQ+X95soVS8/HxnerSyoGzYCm40RYZVL9I+JUi0bVazG/FuX cyZ6DqPjcjCr+gljvrrDfjkSNxJbh8Yf2Yiqjl2IpuwUGpOkkSGy9nHMtX3jStp7PyqQqIH QAN+zaX+F4y3MXveQrGFoWYFdt974blcY2SpH9eJySuW9NQ6nD2M5afe20BXBvxJwaaZL9N 9of9Yw3cKvqueWj/WBkn+lbECYDNmDN6r2dYDQZ2XmikpZv6/fB5EFLT/whmlHVaAN+sVM3 KovbOYe9g0vC85WI3rDFplmThs8MXKTJy8Ln/1vqwA4hYEs6aOwTH5eX2xkr/Y6CEo71y9D 7WyarmO/1akbEMQREZjtxKdUaAjeF9HuO1xsuLWR1oN9rBG2e2t/WX3pZ4fqUtR8MvYwP/7 D8gud7khSpLCk0lGtnwvzScNHiA8p/oP8N8qKoTJgDYXUluNMt4aZK6EGsg++bbEAoBWD61 C5PArvFKd4viWsS+oImsTDYpTfm1UyY4z4DoK63erAf0aL3rP85i2p+sYCa/q0lCgHcGdTJ cS1aaV4SloeWXLuHBA6emGiLeFzaYEP8y+pZKS64ko7edkxBP9ouS/aQETVt84bA1WTl3Vb zGi/8rzWqIFPGKxMi5MiRabWcebOM17eiXM5OSJu/HVbDym3Ajl4436aArazCADiQ== X-QQ-XMRINFO: OWPUhxQsoeAVwkVaQIEGSKwwgKCxK/fD5g== X-QQ-RECHKSPAM: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260827_022052_049626_B2CC804C X-CRM114-Status: GOOD ( 25.51 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Xianbin Zhu SpacemiT K3 has 16 harts split across four clusters, with eight X100 harts in C0/C1 and eight A100 harts in C2/C3. Only hart 0 is powered at reset, so secondary harts cannot reach the OpenSBI warm-boo [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [54.204.34.129 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [54.204.34.129 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Xianbin Zhu SpacemiT K3 has 16 harts split across four clusters, with eight X100 harts in C0/C1 and eight A100 harts in C2/C3. Only hart 0 is powered at reset, so secondary harts cannot reach the OpenSBI warm-boot path until the platform removes their PMU power-down votes and wakes them. Add a start-only HSM backend which performs those operations for the requested hart. This lets the common HSM state machine start secondary harts on demand instead of waking every hart during cold boot. ESOS can remain loaded for the other RPMI services described by the platform DT. Select the HSM backend from the root compatible, preserving K1's existing start and stop behavior. The Boot ROM maps the audio buffer region as I/O although later firmware uses it as normal memory. Restore its cacheable PMA attribute and mark the XIP region as I/O before enabling caches. The boot hart performs the per-hart setup during early platform discovery, while secondary harts do the same in their assembly entry before reaching common warm-boot code. This also enables MISA.H on X100 before common code selects its trap entry; A100 does not implement H. Fence the PMA and guest translation changes before continuing. Use assembler-safe constants shared by the C and warm-entry assembly paths. Since K1 and K3 are RV64-only, omit the SpacemiT platform objects from RV32 generic builds. Program the four cluster warm-boot vectors once and enable CCI-550 snoop and DVM requests before any secondary hart is started. Signed-off-by: Xianbin Zhu Co-developed-by: Troy Mitchell Signed-off-by: Troy Mitchell --- lib/utils/hsm/fdt_hsm_spacemit.c | 113 +++++++++++++++++++------ platform/generic/Kconfig | 7 ++ platform/generic/configs/defconfig | 1 + platform/generic/include/spacemit/common.h | 18 ++-- platform/generic/include/spacemit/k3.h | 127 +++++++++++++++++++++++++++++ platform/generic/include/spacemit/k3_asm.h | 16 ++++ platform/generic/spacemit/k3.c | 122 +++++++++++++++++++++++++++ platform/generic/spacemit/k3_asm.S | 52 ++++++++++++ platform/generic/spacemit/objects.mk | 4 + 9 files changed, 430 insertions(+), 30 deletions(-) diff --git a/lib/utils/hsm/fdt_hsm_spacemit.c b/lib/utils/hsm/fdt_hsm_spacemit.c index 6348f6a3..4f76b99e 100644 --- a/lib/utils/hsm/fdt_hsm_spacemit.c +++ b/lib/utils/hsm/fdt_hsm_spacemit.c @@ -9,11 +9,13 @@ #include #include +#include #include #include #include +#include -static const u64 cpu_wakeup_reg[] = { +static const u64 k1_cpu_wakeup_reg[] = { PMU_AP_CORE0_WAKEUP, PMU_AP_CORE1_WAKEUP, PMU_AP_CORE2_WAKEUP, @@ -24,7 +26,7 @@ static const u64 cpu_wakeup_reg[] = { PMU_AP_CORE7_WAKEUP, }; -static const u64 cpu_idle_reg[] = { +static const u64 k1_cpu_idle_reg[] = { PMU_AP_CORE0_IDLE_CFG, PMU_AP_CORE1_IDLE_CFG, PMU_AP_CORE2_IDLE_CFG, @@ -35,10 +37,11 @@ static const u64 cpu_idle_reg[] = { PMU_AP_CORE7_IDLE_CFG, }; -static inline void spacemit_set_cpu_power(u32 hartid, bool enable) +static inline void spacemit_k1_set_cpu_power(u32 hartid, bool enable) { unsigned int value; - unsigned int *cpu_idle_base = (unsigned int *)(unsigned long)cpu_idle_reg[hartid]; + unsigned int *cpu_idle_base = + (unsigned int *)(unsigned long)k1_cpu_idle_reg[hartid]; value = readl(cpu_idle_base); @@ -50,31 +53,32 @@ static inline void spacemit_set_cpu_power(u32 hartid, bool enable) writel(value, cpu_idle_base); } -static void spacemit_wakeup_cpu(u32 mpidr) +static void spacemit_k1_wakeup_cpu(u32 mpidr) { unsigned int *cpu_reset_base; unsigned int cur_hartid = current_hartid(); - cpu_reset_base = (unsigned int *)(unsigned long)cpu_wakeup_reg[cur_hartid]; + cpu_reset_base = + (unsigned int *)(unsigned long)k1_cpu_wakeup_reg[cur_hartid]; writel(1 << mpidr, cpu_reset_base); } -static void spacemit_assert_cpu(void) +static void spacemit_k1_assert_cpu(void) { - spacemit_set_cpu_power(current_hartid(), false); + spacemit_k1_set_cpu_power(current_hartid(), false); } -static void spacemit_deassert_cpu(unsigned int hartid) +static void spacemit_k1_deassert_cpu(unsigned int hartid) { - spacemit_set_cpu_power(hartid, true); + spacemit_k1_set_cpu_power(hartid, true); } /* Start (or power-up) the given hart */ -static int spacemit_hart_start(unsigned int hartid, unsigned long saddr) +static int spacemit_k1_hart_start(unsigned int hartid, unsigned long saddr) { - spacemit_deassert_cpu(hartid); - spacemit_wakeup_cpu(hartid); + spacemit_k1_deassert_cpu(hartid); + spacemit_k1_wakeup_cpu(hartid); return 0; } @@ -83,10 +87,11 @@ static int spacemit_hart_start(unsigned int hartid, unsigned long saddr) * Stop (or power-down) the current hart from running. This call * doesn't expect to return if success. */ -static int spacemit_hart_stop(void) +static int spacemit_k1_hart_stop(void) { csr_write(CSR_STIMECMP, GENMASK_ULL(63, 0)); - csr_clear(CSR_MIE, MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | MIP_SEIP | MIP_MEIP); + csr_clear(CSR_MIE, MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | + MIP_SEIP | MIP_MEIP); /* disable data prefetch */ csr_clear(CSR_MSETUP, MSETUP_PFE); @@ -106,31 +111,93 @@ static int spacemit_hart_stop(void) * Therefore, use modulo with PLATFORM_MAX_CPUS_PER_CLUSTER * to select the proper bit. */ - csr_clear(CSR_ML2SETUP, 1 << (current_hartid() % PLATFORM_MAX_CPUS_PER_CLUSTER)); + csr_clear(CSR_ML2SETUP, + 1 << (current_hartid() % PLATFORM_MAX_CPUS_PER_CLUSTER)); asm volatile ("fence iorw, iorw"); - spacemit_assert_cpu(); + spacemit_k1_assert_cpu(); wfi(); return SBI_ENOTSUPP; } -static const struct sbi_hsm_device spacemit_hsm_ops = { +static const struct sbi_hsm_device spacemit_k1_hsm_ops = { .name = "spacemit-hsm", - .hart_start = spacemit_hart_start, - .hart_stop = spacemit_hart_stop, + .hart_start = spacemit_k1_hart_start, + .hart_stop = spacemit_k1_hart_stop, }; -static int spacemit_hsm_probe(const void *fdt, int nodeoff, const struct fdt_match *match) +static const unsigned long k3_cluster_idle_reg[] = { + PMU_CX_CAPMP_IDLE_CFG0, PMU_CX_CAPMP_IDLE_CFG1, + PMU_CX_CAPMP_IDLE_CFG2, PMU_CX_CAPMP_IDLE_CFG3, + PMU_CX_CAPMP_IDLE_CFG4, PMU_CX_CAPMP_IDLE_CFG5, + PMU_CX_CAPMP_IDLE_CFG6, PMU_CX_CAPMP_IDLE_CFG7, + PMU_CX_CAPMP_IDLE_CFG8, PMU_CX_CAPMP_IDLE_CFG9, + PMU_CX_CAPMP_IDLE_CFG10, PMU_CX_CAPMP_IDLE_CFG11, + PMU_CX_CAPMP_IDLE_CFG12, PMU_CX_CAPMP_IDLE_CFG13, + PMU_CX_CAPMP_IDLE_CFG14, PMU_CX_CAPMP_IDLE_CFG15, +}; + +static const unsigned long k3_core_idle_reg[] = { + PMU_AP_CORE0_IDLE_CFG, PMU_AP_CORE1_IDLE_CFG, + PMU_AP_CORE2_IDLE_CFG, PMU_AP_CORE3_IDLE_CFG, + PMU_AP_CORE4_IDLE_CFG, PMU_AP_CORE5_IDLE_CFG, + PMU_AP_CORE6_IDLE_CFG, PMU_AP_CORE7_IDLE_CFG, + PMU_CAP_CORE8_IDLE_CFG, PMU_CAP_CORE9_IDLE_CFG, + PMU_CAP_CORE10_IDLE_CFG, PMU_CAP_CORE11_IDLE_CFG, + PMU_CAP_CORE12_IDLE_CFG, PMU_CAP_CORE13_IDLE_CFG, + PMU_CAP_CORE14_IDLE_CFG, PMU_CAP_CORE15_IDLE_CFG, +}; + +static const unsigned long k3_core_wakeup_reg[] = { + PMU_AP_CORE0_WAKEUP, PMU_AP_CORE1_WAKEUP, + PMU_AP_CORE2_WAKEUP, PMU_AP_CORE3_WAKEUP, + PMU_AP_CORE4_WAKEUP, PMU_AP_CORE5_WAKEUP, + PMU_AP_CORE6_WAKEUP, PMU_AP_CORE7_WAKEUP, + PMU_CAP_CORE8_WAKEUP, PMU_CAP_CORE9_WAKEUP, + PMU_CAP_CORE10_WAKEUP, PMU_CAP_CORE11_WAKEUP, + PMU_CAP_CORE12_WAKEUP, PMU_CAP_CORE13_WAKEUP, + PMU_CAP_CORE14_WAKEUP, PMU_CAP_CORE15_WAKEUP, +}; + +static int spacemit_k3_hart_start(u32 hartid, ulong saddr) +{ + u32 value; + + if (hartid >= array_size(k3_core_wakeup_reg)) + return SBI_EINVAL; + + value = readl((void *)k3_cluster_idle_reg[hartid]); + value &= ~CLUSTER_PWR_DOWN_VALUE; + writel(value, (void *)k3_cluster_idle_reg[hartid]); + + value = readl((void *)k3_core_idle_reg[hartid]); + value &= ~PMU_AP_IDLE_PWRDOWN_K3_MASK; + writel(value, (void *)k3_core_idle_reg[hartid]); + + writel(BIT(hartid), (void *)k3_core_wakeup_reg[hartid]); + + return 0; +} + +/* K3 uses this only to power on a hart which has not entered OpenSBI yet. */ +static const struct sbi_hsm_device spacemit_k3_hsm_ops = { + .name = "spacemit-k3-hsm", + .hart_start = spacemit_k3_hart_start, +}; + +static int spacemit_hsm_probe(const void *fdt, int nodeoff, + const struct fdt_match *match) { - sbi_hsm_set_device(&spacemit_hsm_ops); + sbi_hsm_set_device(match->data); return 0; } static const struct fdt_match spacemit_hsm_match[] = { - { .compatible = "spacemit,k1" }, + { .compatible = "spacemit,k1", .data = &spacemit_k1_hsm_ops }, + { .compatible = "spacemit,k3", .data = &spacemit_k3_hsm_ops }, { }, }; diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index 958610d3..a00b4d13 100644 --- a/platform/generic/Kconfig +++ b/platform/generic/Kconfig @@ -109,6 +109,13 @@ config PLATFORM_SPACEMIT_K1 select PLATFORM_SPACEMIT default n +config PLATFORM_SPACEMIT_K3 + bool "Spacemit K3 support" + select FDT_HSM + select FDT_HSM_SPACEMIT + select PLATFORM_SPACEMIT + default n + config CPU_MIPS_P8700 bool default n diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig index 341f6b25..58d40898 100644 --- a/platform/generic/configs/defconfig +++ b/platform/generic/configs/defconfig @@ -15,6 +15,7 @@ CONFIG_PLATFORM_THEAD=y CONFIG_PLATFORM_MIPS_P8700_EYEQ7H=y CONFIG_PLATFORM_MIPS_P8700_BOSTON=y CONFIG_PLATFORM_SPACEMIT_K1=y +CONFIG_PLATFORM_SPACEMIT_K3=y CONFIG_FDT_CACHE=y CONFIG_FDT_CACHE_ANDES_LLCACHE=y CONFIG_FDT_CACHE_SIFIVE_CCACHE=y diff --git a/platform/generic/include/spacemit/common.h b/platform/generic/include/spacemit/common.h index 317bb3e9..7a75ff3f 100644 --- a/platform/generic/include/spacemit/common.h +++ b/platform/generic/include/spacemit/common.h @@ -9,23 +9,27 @@ #ifndef __RISCV_SPACEMIT_COMMON_H__ #define __RISCV_SPACEMIT_COMMON_H__ +#include + +#ifndef __ASSEMBLY__ #include +#endif #define CSR_MSETUP 0x7c0 #define CSR_ML2SETUP 0x7f0 /* dcache enable */ -#define MSETUP_DE BIT(0) +#define MSETUP_DE _BITUL(0) /* icache enable */ -#define MSETUP_IE BIT(1) +#define MSETUP_IE _BITUL(1) /* branch prediction enable */ -#define MSETUP_BPE BIT(4) +#define MSETUP_BPE _BITUL(4) /* prefetch functionality enable */ -#define MSETUP_PFE BIT(5) +#define MSETUP_PFE _BITUL(5) /* misaligned memory access enable */ -#define MSETUP_MME BIT(6) +#define MSETUP_MME _BITUL(6) /* ECC enable */ -#define MSETUP_ECCE BIT(16) +#define MSETUP_ECCE _BITUL(16) #define PMU_AP_BASE 0xd4282800 @@ -74,7 +78,7 @@ #define PMU_AP_IDLE_CORE_IDLE BIT(0) /* bit 1: CORE_PWRDWN - power off core on WFI (requires CORE_IDLE set) */ #define PMU_AP_IDLE_CORE_PWRDWN BIT(1) -/* bit 2: Core L1 SRAM Power Down - reserved/not used in K1 and K3 */ +/* bit 2: Core L1 SRAM Power Down - reserved in K1, used in K3 */ #define PMU_AP_IDLE_CORE_L1_SRAM_PWRDWN BIT(2) /* bit 3: MASK_GIC_NIRQ_TO_CORE - mask nIRQ from GIC, auto-cleared by HW on power-down entry */ #define PMU_AP_IDLE_MASK_GIC_NIRQ BIT(3) diff --git a/platform/generic/include/spacemit/k3.h b/platform/generic/include/spacemit/k3.h new file mode 100644 index 00000000..f444d064 --- /dev/null +++ b/platform/generic/include/spacemit/k3.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2026 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + +#ifndef __RISCV_SPACEMIT_K3_H__ +#define __RISCV_SPACEMIT_K3_H__ + +#include + +/* PMA configuration CSR */ +#define CSR_PMACFG0 0x7de + +/* + * PMACFG0 audio buffer region field: bits [55:48]. + * The Boot ROM maps this region as I/O. Restore it to a cacheable + * attribute so later firmware can use it for data or instructions. + */ +#define PMACFG0_AUDIO_BUF_FIELD_MASK _UL(0xff) +#define PMACFG0_AUDIO_BUF_FIELD_SHIFT 48 +#define PMACFG0_AUDIO_BUF_ATTR_CACHEABLE _UL(0x20) + +/* + * PMACFG0 XIP region field: bits [23:16]. + * Lower 12 bits are zero so GAS emits a single lui instruction. + */ +#define PMACFG0_XIP_FIELD_CLEAR _UL(0x00ff0000) +#define PMACFG0_XIP_ATTR_IO _UL(0x00220000) + +#define CSR_ML2HINT 0x7f7 +#define MISA_EXT_H _BITUL(7) + +/* Enable instruction prefetch in L2 cache on miss */ +#define ML2SETUP_IPRF _BITUL(16) +/* Enable TLB prefetch in L2 cache */ +#define ML2SETUP_TPRF _BITUL(18) +/* Enable top-of-clk of trace */ +#define ML2HINT_TRACE_TOP_ICGEN _BITUL(26) + +#define MSETUP_BOOT_FLAGS (MSETUP_DE | MSETUP_IE | \ + MSETUP_BPE | MSETUP_PFE | \ + MSETUP_MME | MSETUP_ECCE) + +/* A100 cores: hart 8-11 belong to C2 cluster, hart 12-15 to C3 cluster */ +#define PMU_CAP_CORE8_WAKEUP (PMU_AP_BASE + 0x360) +#define PMU_CAP_CORE9_WAKEUP (PMU_AP_BASE + 0x364) +#define PMU_CAP_CORE10_WAKEUP (PMU_AP_BASE + 0x368) +#define PMU_CAP_CORE11_WAKEUP (PMU_AP_BASE + 0x36c) +#define PMU_CAP_CORE12_WAKEUP (PMU_AP_BASE + 0x22c) +#define PMU_CAP_CORE13_WAKEUP (PMU_AP_BASE + 0x230) +#define PMU_CAP_CORE14_WAKEUP (PMU_AP_BASE + 0x234) +#define PMU_CAP_CORE15_WAKEUP (PMU_AP_BASE + 0x238) + +/* A100 per-core idle config registers (harts 8-15) */ +#define PMU_CAP_CORE8_IDLE_CFG (PMU_AP_BASE + 0x340) +#define PMU_CAP_CORE9_IDLE_CFG (PMU_AP_BASE + 0x344) +#define PMU_CAP_CORE10_IDLE_CFG (PMU_AP_BASE + 0x348) +#define PMU_CAP_CORE11_IDLE_CFG (PMU_AP_BASE + 0x34c) +#define PMU_CAP_CORE12_IDLE_CFG (PMU_AP_BASE + 0x20c) +#define PMU_CAP_CORE13_IDLE_CFG (PMU_AP_BASE + 0x210) +#define PMU_CAP_CORE14_IDLE_CFG (PMU_AP_BASE + 0x214) +#define PMU_CAP_CORE15_IDLE_CFG (PMU_AP_BASE + 0x218) + +/* CX CAPMP cluster idle config registers */ +#define PMU_CX_CAPMP_IDLE_CFG0 (PMU_AP_BASE + 0x120) +#define PMU_CX_CAPMP_IDLE_CFG1 (PMU_AP_BASE + 0x0e4) +#define PMU_CX_CAPMP_IDLE_CFG2 (PMU_AP_BASE + 0x150) +#define PMU_CX_CAPMP_IDLE_CFG3 (PMU_AP_BASE + 0x154) +#define PMU_CX_CAPMP_IDLE_CFG4 (PMU_AP_BASE + 0x314) +#define PMU_CX_CAPMP_IDLE_CFG5 (PMU_AP_BASE + 0x318) +#define PMU_CX_CAPMP_IDLE_CFG6 (PMU_AP_BASE + 0x31c) +#define PMU_CX_CAPMP_IDLE_CFG7 (PMU_AP_BASE + 0x320) +#define PMU_CX_CAPMP_IDLE_CFG8 (PMU_AP_BASE + 0x350) +#define PMU_CX_CAPMP_IDLE_CFG9 (PMU_AP_BASE + 0x354) +#define PMU_CX_CAPMP_IDLE_CFG10 (PMU_AP_BASE + 0x358) +#define PMU_CX_CAPMP_IDLE_CFG11 (PMU_AP_BASE + 0x35c) +#define PMU_CX_CAPMP_IDLE_CFG12 (PMU_AP_BASE + 0x21c) +#define PMU_CX_CAPMP_IDLE_CFG13 (PMU_AP_BASE + 0x220) +#define PMU_CX_CAPMP_IDLE_CFG14 (PMU_AP_BASE + 0x224) +#define PMU_CX_CAPMP_IDLE_CFG15 (PMU_AP_BASE + 0x228) + +#define PMU_AP_IDLE_PWRDOWN_K3_MASK (PMU_AP_IDLE_CORE_IDLE | \ + PMU_AP_IDLE_CORE_PWRDWN | \ + PMU_AP_IDLE_CORE_L1_SRAM_PWRDWN | \ + PMU_AP_IDLE_MASK_GIC_NIRQ | \ + PMU_AP_IDLE_MASK_GIC_NFIQ) + +/* + * PMU CX per-cluster idle control bits (PMU_CX_CAPMPn_IDLE_CFG). + */ +/* bit 0: MP Idle - gate cluster clocks externally on WFI */ +#define PMU_CX_IDLE_MP_IDLE BIT(0) +/* bit 1: MP Power Down - power off cluster logic when idle */ +#define PMU_CX_IDLE_MP_PWRDWN BIT(1) +/* bit 2: L2 Cache SRAM Power Down */ +#define PMU_CX_IDLE_L2_SRAM_PWRDWN BIT(2) +/* bit 3: SCU SRAM Power Down - not used, SCU SRAM does not support retention */ +#define PMU_CX_IDLE_MP_SCU_SRAM_PWRDWN BIT(3) +/* bit 7: ACNACTM Hardware Control - HW controls ACNACTM port on MP low power entry */ +#define PMU_CX_IDLE_ACNACTM_HW_CTRL BIT(7) + +#define CLUSTER_PWR_DOWN_VALUE (PMU_CX_IDLE_MP_IDLE | \ + PMU_CX_IDLE_MP_PWRDWN | \ + PMU_CX_IDLE_L2_SRAM_PWRDWN | \ + PMU_CX_IDLE_MP_SCU_SRAM_PWRDWN | \ + PMU_CX_IDLE_ACNACTM_HW_CTRL) + +/* boot entry for A100 clusters */ +#define C2_RVBADDR_LO_ADDR (0xd4282c00 + 0x3e8) +#define C2_RVBADDR_HI_ADDR (0xd4282c00 + 0x3ec) +#define C3_RVBADDR_LO_ADDR (0xd4282c00 + 0x260) +#define C3_RVBADDR_HI_ADDR (0xd4282c00 + 0x264) + +#define PLATFORM_A100_FIRST_ID 8 + +#define PLAT_CCI_K3_AIDMA_IFACE_IX 0 +#define PLAT_CCI_K3_CLUSTER0_IFACE_IX 1 +#define PLAT_CCI_K3_CLUSTER1_IFACE_IX 2 +#define PLAT_CCI_K3_CLUSTER2_0_IFACE_IX 3 +#define PLAT_CCI_K3_CLUSTER2_1_IFACE_IX 4 +#define PLAT_CCI_K3_CLUSTER3_0_IFACE_IX 5 +#define PLAT_CCI_K3_CLUSTER3_1_IFACE_IX 6 + +#endif /* __RISCV_SPACEMIT_K3_H__ */ diff --git a/platform/generic/include/spacemit/k3_asm.h b/platform/generic/include/spacemit/k3_asm.h new file mode 100644 index 00000000..70c00478 --- /dev/null +++ b/platform/generic/include/spacemit/k3_asm.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2026 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + +#ifndef __RISCV_SPACEMIT_K3_ASM_H__ +#define __RISCV_SPACEMIT_K3_ASM_H__ + +#ifndef __ASSEMBLY__ +void _spacemit_k3_warm_start(void); +#endif + +#endif /* __RISCV_SPACEMIT_K3_ASM_H__ */ diff --git a/platform/generic/spacemit/k3.c b/platform/generic/spacemit/k3.c new file mode 100644 index 00000000..967d09bf --- /dev/null +++ b/platform/generic/spacemit/k3.c @@ -0,0 +1,122 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2026 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static const int cci_map[] = { + PLAT_CCI_K3_AIDMA_IFACE_IX, + PLAT_CCI_K3_CLUSTER0_IFACE_IX, + PLAT_CCI_K3_CLUSTER1_IFACE_IX, + PLAT_CCI_K3_CLUSTER2_0_IFACE_IX, + PLAT_CCI_K3_CLUSTER2_1_IFACE_IX, + PLAT_CCI_K3_CLUSTER3_0_IFACE_IX, + PLAT_CCI_K3_CLUSTER3_1_IFACE_IX, +}; + +/* + * The boot hart reaches this function before caches are enabled. Secondary + * harts perform the same setup in _spacemit_k3_warm_start before entering + * the common warm-boot path. + */ +static void spacemit_k3_hart_init(u32 hartid) +{ + csr_clear(CSR_PMACFG0, + PMACFG0_AUDIO_BUF_FIELD_MASK << + PMACFG0_AUDIO_BUF_FIELD_SHIFT); + csr_set(CSR_PMACFG0, + PMACFG0_AUDIO_BUF_ATTR_CACHEABLE << + PMACFG0_AUDIO_BUF_FIELD_SHIFT); + csr_clear(CSR_PMACFG0, PMACFG0_XIP_FIELD_CLEAR); + csr_set(CSR_PMACFG0, PMACFG0_XIP_ATTR_IO); + __sbi_sfence_vma_all(); + + csr_set(CSR_ML2SETUP, + _BITUL(hartid % PLATFORM_MAX_CPUS_PER_CLUSTER) | + ML2SETUP_IPRF | ML2SETUP_TPRF); + csr_set(CSR_ML2HINT, ML2HINT_TRACE_TOP_ICGEN); + csr_set(CSR_MSETUP, MSETUP_BOOT_FLAGS); + + if (hartid < PLATFORM_A100_FIRST_ID) { + /* MISA.H is writable on X100 and not implemented on A100. */ + csr_set(CSR_MISA, MISA_EXT_H); + __sbi_hfence_gvma_all(); + } +} + +/* The boot hart is already running, so it is never started by the HSM. */ +static void spacemit_k3_keep_boot_hart_powered(void) +{ + u32 value; + + value = readl((void *)(unsigned long)PMU_CX_CAPMP_IDLE_CFG0); + value &= ~CLUSTER_PWR_DOWN_VALUE; + writel(value, (void *)(unsigned long)PMU_CX_CAPMP_IDLE_CFG0); + + value = readl((void *)(unsigned long)PMU_AP_CORE0_IDLE_CFG); + value &= ~PMU_AP_IDLE_PWRDOWN_K3_MASK; + writel(value, (void *)(unsigned long)PMU_AP_CORE0_IDLE_CFG); +} + +/* Program global state before the HSM starts any secondary hart. */ +static void spacemit_k3_pre_init(void) +{ + unsigned long entry = (unsigned long)&_spacemit_k3_warm_start; + int i; + + writel((u32)entry, (void *)(unsigned long)C0_RVBADDR_LO_ADDR); + writel((u32)(entry >> 32), (void *)(unsigned long)C0_RVBADDR_HI_ADDR); + + writel((u32)entry, (void *)(unsigned long)C1_RVBADDR_LO_ADDR); + writel((u32)(entry >> 32), (void *)(unsigned long)C1_RVBADDR_HI_ADDR); + + writel((u32)entry, (void *)(unsigned long)C2_RVBADDR_LO_ADDR); + writel((u32)(entry >> 32), (void *)(unsigned long)C2_RVBADDR_HI_ADDR); + + writel((u32)entry, (void *)(unsigned long)C3_RVBADDR_LO_ADDR); + writel((u32)(entry >> 32), (void *)(unsigned long)C3_RVBADDR_HI_ADDR); + + for (i = 0; i < array_size(cci_map); i++) + cci_enable_snoop_dvm_reqs(cci_map, i); + + spacemit_k3_keep_boot_hart_powered(); +} + +static int spacemit_k3_early_init(bool cold_boot) +{ + if (cold_boot) + spacemit_k3_pre_init(); + + return generic_early_init(cold_boot); +} + +static int spacemit_k3_platform_init(const void *fdt, int nodeoff, + const struct fdt_match *match) +{ + spacemit_k3_hart_init(current_hartid()); + generic_platform_ops.early_init = spacemit_k3_early_init; + + return 0; +} + +static const struct fdt_match spacemit_k3_match[] = { + { .compatible = "spacemit,k3" }, + { /* sentinel */ } +}; + +const struct fdt_driver spacemit_k3 = { + .match_table = spacemit_k3_match, + .init = spacemit_k3_platform_init, +}; diff --git a/platform/generic/spacemit/k3_asm.S b/platform/generic/spacemit/k3_asm.S new file mode 100644 index 00000000..2da58857 --- /dev/null +++ b/platform/generic/spacemit/k3_asm.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2026 SpacemiT + * Authors: + * Xianbin Zhu + * Troy Mitchell + */ + +#define __ASSEMBLY__ +#include +#include + + .section .entry, "ax", %progbits + .align 3 + .globl _spacemit_k3_warm_start +_spacemit_k3_warm_start: + /* Program PMA attributes before enabling the caches. */ + li t0, (PMACFG0_AUDIO_BUF_FIELD_MASK << \ + PMACFG0_AUDIO_BUF_FIELD_SHIFT) + csrc CSR_PMACFG0, t0 + li t0, (PMACFG0_AUDIO_BUF_ATTR_CACHEABLE << \ + PMACFG0_AUDIO_BUF_FIELD_SHIFT) + csrs CSR_PMACFG0, t0 + li t0, PMACFG0_XIP_FIELD_CLEAR + csrc CSR_PMACFG0, t0 + li t0, PMACFG0_XIP_ATTR_IO + csrs CSR_PMACFG0, t0 + sfence.vma + + /* Enable L1 snooping and L2 prefetch for this hart. */ + csrr t0, mhartid + andi t0, t0, (PLATFORM_MAX_CPUS_PER_CLUSTER - 1) + li t1, 1 + sll t1, t1, t0 + li t2, (ML2SETUP_IPRF | ML2SETUP_TPRF) + or t1, t1, t2 + csrs CSR_ML2SETUP, t1 + li t0, ML2HINT_TRACE_TOP_ICGEN + csrs CSR_ML2HINT, t0 + + li t0, MSETUP_BOOT_FLAGS + csrs CSR_MSETUP, t0 + + /* Enable H before common code selects the per-hart trap entry. */ + csrr t0, mhartid + li t1, PLATFORM_A100_FIRST_ID + bgeu t0, t1, 1f + li t0, MISA_EXT_H + csrs misa, t0 + .word 0x62000073 /* hfence.gvma */ +1: + j _start_warm diff --git a/platform/generic/spacemit/objects.mk b/platform/generic/spacemit/objects.mk index 8309ad1f..eac3199c 100644 --- a/platform/generic/spacemit/objects.mk +++ b/platform/generic/spacemit/objects.mk @@ -2,6 +2,10 @@ # SPDX-License-Identifier: BSD-2-Clause # +ifeq ($(PLATFORM_RISCV_XLEN), 64) platform-objs-$(CONFIG_PLATFORM_SPACEMIT) += spacemit/spacemit.o carray-platform_override_modules-$(CONFIG_PLATFORM_SPACEMIT_K1) += spacemit_k1 platform-objs-$(CONFIG_PLATFORM_SPACEMIT_K1) += spacemit/k1.o +carray-platform_override_modules-$(CONFIG_PLATFORM_SPACEMIT_K3) += spacemit_k3 +platform-objs-$(CONFIG_PLATFORM_SPACEMIT_K3) += spacemit/k3.o spacemit/k3_asm.o +endif