From patchwork Wed Aug 26 18:42:15 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yonggang Luo X-Patchwork-Id: 2292926 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=joIL65oG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists1p.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4hVYSW0gLCz1xtN for ; Thu, 27 Aug 2026 04:43:23 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzIaM-0006pB-Td; Wed, 26 Aug 2026 14:42:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzIaM-0006ns-5v for qemu-ppc@nongnu.org; Wed, 26 Aug 2026 14:42:54 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wzIaK-00029L-Cw for qemu-ppc@nongnu.org; Wed, 26 Aug 2026 14:42:53 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-ca97d139d5fso1135231a12.0 for ; Wed, 26 Aug 2026 11:42:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787769771; x=1788374571; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=IukQGcRHMsVbGXSG1mzI1R3dLtKOyYm2L7shctiJxkE=; b=joIL65oGCWHBM68YknwbarQ86NWE6PJIuU0usv3GZ34DvI+Lh3RO03h0F//fDJMmq+ wIJeZTcRYV5n/2ofIyOL8f4/3ZkKE9jC+zkaZPajjUbW0BBjsw5xxB6IYCYwpCUGqpEG QZMIzmwduYHcHLwZrUvaurVCFhoTJp/1FyMWYNKEXAdrbk0ePIu8dyE9Mk4jPG5OWkmK OZW7SAq2d2APxke/IF9OWMKvyqpc1lLBRBJFHN5V6ZTjoDs45WkxIQFtREHBM1ZEb+7d t48/YBYKs1uhGmkwukbiy7Q9PivS+KfASN+k6hkOUyJ7BUQzT4Dyj5oT6nqDevhmF5YF Dh5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787769771; x=1788374571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=IukQGcRHMsVbGXSG1mzI1R3dLtKOyYm2L7shctiJxkE=; b=QQ+fuGZy0WCyoQXkkb5UIUTRuaNogiXh8SNWPM7ANYmC56XoyibkKt3GANhoIF9WHi eCCqq39aeYu9x+d5u3I1LcJ5w7bmoV5eSIDVeWWFpUqTbrYcgIzlilrZKHsVzDV1W5SH dbR4II5E0Cqtlo/AKL7RDk+Tm4bKpltUAkQtngHKFZ036LCY2QgwL0ZIrnEQJeL2ytsB 3+P9/c15gCtxYFhu75XxtfUA7kuZvbRWKT5ngPosclkmrU4dMsmBWYehE0tMNuFgvn3M cb3Lpets4fXCrr35Pg0aPCj8XpIu9r9BKHLcqJnEatb/SsG3HYsVnOx4BfB5Hx/JmVgE MKug== X-Forwarded-Encrypted: i=1; AHgh+Rq4UxSjnaAgBnNrUlzHHT5RPy5KZVm66tdEQhniii/HMMiBxF5mlFu6T1J+nAw0o3juxsjE8dIA8w==@nongnu.org X-Gm-Message-State: AFuF++l4olGwz6DsAREaWwfieNDIDdZmBtqUk5TLzscBkxUsa4w9nifh wtEMjL1EfcDIqJs5/a4Jo/ciFZG6aIk8TxC+oI95SfAEZnIkTZsQwfKYxyNnwf/3wDY= X-Gm-Gg: AR+sD13UIkn+K+UWHuaIWFUElw1YpM9LdYqaoLYfKW1mzigNMg1xQTXXPNNjJrhFEwp lOL9Y0mVUmOy2dWao2IEAO8erB4vG0Y8r9DlDtcYKsYhlPQ4lZEd+kewl4oG6MGhMiyqDbrS5je yRNIAVbSIXmA69JNADTHBrvSgy9SBEo/83po7gEVKwGyX5fb1ciU55UeAvuwrPvMmEyJQiYG4z/ +Hinmu3LEB9NLIannFYBXv6vXjsGVrVxON/L8P3HeSJlSXxD3tZG+7XjHV9TEEQQkhG0qPHQJAN vHtd70v9NdQOfS1QObhbBUm74D48nsUHR0zkPEOWP8d1OjMelM27e+K5j8UHeAZzqoVlssB8z3h FXoFbPCNkHwKatN+5UAyAAkv6Yx5SFM06zz1nVMzFBMJsFW+FBy/ruIBZWPfl17AXv2fV/FU+bs /fTf2UCQHD69jIeMC2PwX3mYmUuJPktyY4jS2Fg1N79bcg3nt4GjIcN1IaFzQnzW5pt/3DKkT58 8r4fuVgb9InHG//ZqhQqw== X-Received: by 2002:a05:6a21:a382:b0:3cc:22bb:8911 with SMTP id adf61e73a8af0-3cf833389c9mr19772223637.6.1787769770909; Wed, 26 Aug 2026 11:42:50 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.42.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:42:50 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 01/13] accel: use a shared TYPE_ACCEL_CPU parent Date: Thu, 27 Aug 2026 02:42:15 +0800 Message-ID: <20260826184229.1145-2-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - TYPE_ACCEL_CPU was "accel-" CPU_RESOLVING_TYPE, so each arch compiled a different parent (accel-arm-cpu, accel-riscv-cpu, ...). Common code registered only one of those names from target_cpu_type() at MODULE_INIT_QOM. - A combined binary still registers every linked AccelCPU subclass. RISC-V tcg-accel-riscv-cpu has parent accel-riscv-cpu even when the selected target is ARM, so the old one-parent type_init does not cover the other family. Creating the parent in the subclass register path would hide that, but it keeps per-arch parents that AccelCPUClass does not need. - AccelCPUClass is arch-independent. The parent only supplies class_size and ACCEL_CPU_CLASS(). Make TYPE_ACCEL_CPU the fixed abstract type accel-cpu and register it once next to TYPE_ACCEL. - Leaf names still encode the CPU type so accel_init_cpu_interfaces() can look up "-accel-" CPU_RESOLVING_TYPE (for example tcg-accel-arm-cpu). ACCEL_CPU_NAME() keeps that string; it is no longer derived from the parent type name. - Drop register_accel_target_type(). Subclasses keep type_register_static() with .parent = TYPE_ACCEL_CPU. Signed-off-by: Yonggang Luo --- accel/accel-common.c | 21 ++++++--------------- include/accel/accel-cpu-target.h | 3 +-- include/accel/accel-cpu.h | 2 ++ 3 files changed, 9 insertions(+), 17 deletions(-) diff --git a/accel/accel-common.c b/accel/accel-common.c index 00a400243f0..c4c365f38c7 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -126,21 +126,12 @@ static const TypeInfo accel_types[] = { .instance_size = sizeof(AccelState), .abstract = true, }, + { + .name = TYPE_ACCEL_CPU, + .parent = TYPE_OBJECT, + .abstract = true, + .class_size = sizeof(AccelCPUClass), + }, }; DEFINE_TYPES(accel_types) - -static void register_accel_target_type(void) -{ - g_autofree char *name = g_strconcat("accel-", target_cpu_type(), NULL); - const TypeInfo accel_cpu_type = { - .name = name, - .parent = TYPE_OBJECT, - .abstract = true, - .class_size = sizeof(AccelCPUClass), - }; - - type_register_static(&accel_cpu_type); -} - -type_init(register_accel_target_type); diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-target.h index 6feb344e29b..cf33ebd79fc 100644 --- a/include/accel/accel-cpu-target.h +++ b/include/accel/accel-cpu-target.h @@ -24,8 +24,7 @@ #include "accel/accel-cpu.h" #include "cpu.h" -#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE -#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) +#define ACCEL_CPU_NAME(name) (name "-accel-" CPU_RESOLVING_TYPE) DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) #endif /* ACCEL_CPU_H */ diff --git a/include/accel/accel-cpu.h b/include/accel/accel-cpu.h index 9e7eede7c3c..5cfc2b24223 100644 --- a/include/accel/accel-cpu.h +++ b/include/accel/accel-cpu.h @@ -12,6 +12,8 @@ #include "qom/object.h" #include "hw/core/cpu.h" +#define TYPE_ACCEL_CPU "accel-cpu" + typedef struct AccelCPUClass { ObjectClass parent_class; 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Wed, 26 Aug 2026 11:42:59 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:42:58 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 02/13] hw/riscv/virt: register TYPE_TARGET_SPECIFIC Date: Thu, 27 Aug 2026 02:42:16 +0800 Message-ID: <20260826184229.1145-3-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=luoyonggang@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hide the RISC-V virt machine when the selected target is not RISC-V in a combined qemu-system binary. Signed-off-by: Yonggang Luo --- hw/riscv/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2d242ef71a5..b767c5434a0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -22,6 +22,7 @@ #include "qemu/units.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "hw/core/boards.h" #include "hw/core/loader.h" @@ -1718,6 +1719,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) MachineClass *mc = MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); + TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_riscv; mc->desc = "RISC-V VirtIO board"; mc->init = virt_machine_init; mc->max_cpus = VIRT_CPUS_MAX; @@ -1790,6 +1792,7 @@ static const TypeInfo virt_machine_typeinfo = { .instance_size = sizeof(RISCVVirtState), .interfaces = (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_SPECIFIC }, { } }, }; From patchwork Wed Aug 26 18:42:17 2026 Content-Type: text/plain; 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Wed, 26 Aug 2026 11:43:09 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:43:07 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 03/13] hw/arm/virt: register TYPE_TARGET_SPECIFIC on the abstract parent Date: Thu, 27 Aug 2026 02:42:17 +0800 Message-ID: <20260826184229.1145-4-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hide the ARM virt machine when the selected target is not ARM in a combined qemu-system binary. Versioned virt types already implement TYPE_TARGET_SPECIFIC; register it on the abstract parent as well. Signed-off-by: Yonggang Luo --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index daba9af79f1..c2ace7706f1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -4161,6 +4161,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) MachineClass *mc = MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); + TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm; mc->init = machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by KVM. * The value may be reduced later when we have more information about the @@ -4431,6 +4432,7 @@ static const TypeInfo virt_machine_info = { .instance_finalize = virt_instance_finalize, .interfaces = (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_SPECIFIC }, { } }, }; From patchwork Wed Aug 26 18:42:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yonggang Luo X-Patchwork-Id: 2292928 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Wed, 26 Aug 2026 11:43:18 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:43:17 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 04/13] machine: allow -M name to differ from QOM type Date: Thu, 27 Aug 2026 02:42:18 +0800 Message-ID: <20260826184229.1145-5-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - Add machine_class_set_name() so boards can keep a stable -M name when the QOM type is uniquified. machine_class_base_init still defaults the name to the QOM type without -machine. - Document that MachineClass::name is the -M name, not the QOM type. - Sort -M help by MachineClass::name so order matches the printed names when QOM types are prefixed (arm-virt-11.1-machine vs virt-11.1). Signed-off-by: Yonggang Luo --- hw/core/machine.c | 6 ++++++ include/hw/core/boards.h | 12 +++++++++++- system/vl.c | 8 +++----- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 73b4d82b4a1..082f95e4349 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1209,6 +1209,12 @@ static void machine_class_init(ObjectClass *oc, const void *data) "Memory size configuration"); } +void machine_class_set_name(MachineClass *mc, const char *name) +{ + g_free(mc->name); + mc->name = g_strdup(name); +} + static void machine_class_base_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); diff --git a/include/hw/core/boards.h b/include/hw/core/boards.h index c963e956157..cb6a37235a2 100644 --- a/include/hw/core/boards.h +++ b/include/hw/core/boards.h @@ -37,6 +37,16 @@ const char *machine_default_cpu_type(const MachineState *ms); * @mc: Machine class */ const char *machine_class_default_cpu_type(MachineClass *mc); +/** + * machine_class_set_name: Set the -M name when it differs from the QOM type + * @mc: Machine class + * @name: Name used by -M lookup, help, and migration + * + * machine_class_base_init sets MachineClass::name from the QOM type with + * the -machine suffix removed. Call this from board class_init when the + * CLI name must stay stable after the QOM type is uniquified. + */ +void machine_class_set_name(MachineClass *mc, const char *name); void machine_add_audiodev_property(MachineClass *mc); void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp); @@ -270,7 +280,7 @@ struct MachineClass { /*< public >*/ const char *family; /* NULL iff @name identifies a standalone machtype */ - char *name; + char *name; /* -M name; default is QOM type without -machine */ const char *alias; const char *desc; const char *deprecation_reason; diff --git a/system/vl.c b/system/vl.c index 83b9425de9b..4b1fcd2031f 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1538,10 +1538,9 @@ static gint machine_class_cmp(gconstpointer a, gconstpointer b, gpointer d) if (mc1->family == NULL) { if (mc2->family == NULL) { /* Compare standalone machine types against each other; they sort - * in increasing order. + * in increasing order by the name shown in -M help. */ - return strcmp(object_class_get_name(OBJECT_CLASS(mc1)), - object_class_get_name(OBJECT_CLASS(mc2))); + return strcmp(mc1->name, mc2->name); } /* Standalone machine types sort after families. */ @@ -1560,8 +1559,7 @@ static gint machine_class_cmp(gconstpointer a, gconstpointer b, gpointer d) } /* Within the same family, machine types sort in decreasing order. */ - return strcmp(object_class_get_name(OBJECT_CLASS(mc2)), - object_class_get_name(OBJECT_CLASS(mc1))); + return strcmp(mc2->name, mc1->name); } static void machine_help_func(const QDict *qdict) From patchwork Wed Aug 26 18:42:19 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yonggang Luo X-Patchwork-Id: 2292939 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=eF+BoHcX; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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Wed, 26 Aug 2026 11:43:27 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:43:26 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 05/13] hw/riscv/virt: use unique QOM name Date: Thu, 27 Aug 2026 02:42:19 +0800 Message-ID: <20260826184229.1145-6-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=luoyonggang@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use TYPE_RISCV_VIRT_MACHINE so the RISC-V virt QOM type does not collide with ARM virt in a combined qemu-system binary. Keep the -M / help / migration name as virt via machine_class_set_name(). Signed-off-by: Yonggang Luo --- hw/riscv/virt.c | 3 ++- include/hw/riscv/virt.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b767c5434a0..9019a0a04d6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1721,6 +1721,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_riscv; mc->desc = "RISC-V VirtIO board"; + machine_class_set_name(mc, "virt"); mc->init = virt_machine_init; mc->max_cpus = VIRT_CPUS_MAX; mc->default_cpu_type = TYPE_RISCV_CPU_BASE; @@ -1784,7 +1785,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) } static const TypeInfo virt_machine_typeinfo = { - .name = MACHINE_TYPE_NAME("virt"), + .name = TYPE_RISCV_VIRT_MACHINE, .parent = TYPE_MACHINE, .class_init = virt_machine_class_init, .instance_init = virt_machine_instance_init, diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 36a2def4109..5559783aebb 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -30,7 +30,7 @@ #define VIRT_SOCKETS_MAX_BITS 2 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) -#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") +#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("riscv-virt") typedef struct RISCVVirtState RISCVVirtState; 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Wed, 26 Aug 2026 11:43:35 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 06/13] hw/arm/virt: use unique QOM name Date: Thu, 27 Aug 2026 02:42:20 +0800 Message-ID: <20260826184229.1145-7-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set TYPE_VIRT_MACHINE to MACHINE_TYPE_NAME("arm-virt") so ARM virt no longer collides with other virt-machine types in one process. Keep the -M / help / migration name as virt-* via machine_class_set_name(). Signed-off-by: Yonggang Luo --- hw/arm/virt.c | 3 ++- include/hw/arm/virt.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c2ace7706f1..ee71974e67a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -124,13 +124,14 @@ static void arm_virt_compat_default_set(MachineClass *mc) MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \ MACHINE_VER_DEPRECATION(__VA_ARGS__); \ + machine_class_set_name(mc, "virt-" MACHINE_VER_STR(__VA_ARGS__)); \ if (latest) { \ mc->alias = "virt"; \ } \ } \ static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \ { \ - .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ + .name = MACHINE_VER_TYPE_NAME("arm-virt", __VA_ARGS__), \ .parent = TYPE_VIRT_MACHINE, \ .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ .interfaces = type_target_specific, \ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 22e66d1a113..383ee320948 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -215,7 +215,7 @@ struct VirtMachineState { #define VIRT_ECAM_ID(high) (high ? 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Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 07/13] hw/arm/virt: prefix ACPI helpers with arm_virt_ Date: Thu, 27 Aug 2026 02:42:21 +0800 Message-ID: <20260826184229.1145-8-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - virt_acpi_setup and virt_is_acpi_enabled are generic names also used by RISC-V and LoongArch virt. A combined binary cannot export two functions with the same C symbol. - Rename the ARM helpers to arm_virt_acpi_setup and arm_virt_is_acpi_enabled. Leave the trace event virt_acpi_setup unchanged; it is a separate identifier. Signed-off-by: Yonggang Luo Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/virt-acpi-build.c | 4 ++-- hw/arm/virt.c | 12 ++++++------ include/hw/arm/virt.h | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index f6386088b6f..a4a0d2c9997 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -1556,7 +1556,7 @@ static const VMStateDescription vmstate_virt_acpi_build = { }, }; -void virt_acpi_setup(VirtMachineState *vms) +void arm_virt_acpi_setup(VirtMachineState *vms) { AcpiBuildTables tables; AcpiBuildState *build_state; @@ -1567,7 +1567,7 @@ void virt_acpi_setup(VirtMachineState *vms) return; } - if (!virt_is_acpi_enabled(vms)) { + if (!arm_virt_is_acpi_enabled(vms)) { trace_virt_acpi_setup(); return; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ee71974e67a..56d7154fed9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -771,7 +771,7 @@ static void fdt_add_cpu_nodes(VirtMachineState *vms) &bottom_node, CPU_TOPOLOGY_LEVEL_SOCKET); if (cache_at_topo_level) { - if (bottom_node == 1 && !virt_is_acpi_enabled(vms)) + if (bottom_node == 1 && !arm_virt_is_acpi_enabled(vms)) error_setg( &error_fatal, "Cannot share L1 at socket_id %d." @@ -811,7 +811,7 @@ static void fdt_add_cpu_nodes(VirtMachineState *vms) top_cluster, bottom_cluster, cpu, &cluster_offset); - if (bottom_cluster == 1 && !virt_is_acpi_enabled(vms)) { + if (bottom_cluster == 1 && !arm_virt_is_acpi_enabled(vms)) { error_setg(&error_fatal, "Cannot share L1 at socket_id %d, cluster_id %d. " "DT limitation on sharing at cache level = 1.", @@ -2038,7 +2038,7 @@ static void create_smmuv3_dev_dtb(VirtMachineState *vms, DeviceState *dev, hwaddr base = platform_bus_get_mmio_addr(pbus, sbdev, 0); MachineState *ms = MACHINE(vms); - if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms))) { + if (!(vms->bootinfo.firmware_loaded && arm_virt_is_acpi_enabled(vms))) { if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { error_setg(errp, "SMMUv3 with accel=on not supported for DT"); return; @@ -2448,7 +2448,7 @@ void virt_machine_done(Notifier *notifier, void *data) pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus, &error_abort); - virt_acpi_setup(vms); + arm_virt_acpi_setup(vms); virt_build_smbios(vms); } @@ -3212,7 +3212,7 @@ static void machvirt_init(MachineState *machine) create_pcie(vms); create_cxl_host_reg_region(vms); - if (aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { + if (aarch64 && firmware_loaded && arm_virt_is_acpi_enabled(vms)) { vms->acpi_dev = create_acpi_ged(vms); vms->generic_error_notifier.notify = virt_generic_error_req; notifier_list_add(&acpi_generic_error_notifiers, @@ -3562,7 +3562,7 @@ static void virt_set_oem_table_id(Object *obj, const char *value, } -bool virt_is_acpi_enabled(const VirtMachineState *vms) +bool arm_virt_is_acpi_enabled(const VirtMachineState *vms) { if (vms->acpi == ON_OFF_AUTO_OFF) { return false; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 383ee320948..2ee61cc5a06 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -218,8 +218,8 @@ struct VirtMachineState { #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("arm-virt") OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE) -void virt_acpi_setup(VirtMachineState *vms); -bool virt_is_acpi_enabled(const VirtMachineState *vms); +void arm_virt_acpi_setup(VirtMachineState *vms); +bool arm_virt_is_acpi_enabled(const VirtMachineState *vms); #define CLIDR_CTYPE_NO_CACHE 0x00 #define CLIDR_CTYPE_I_CACHE 0x01 From patchwork Wed Aug 26 18:42:22 2026 Content-Type: text/plain; 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Wed, 26 Aug 2026 11:43:53 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:43:52 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 08/13] hw/riscv/virt: prefix ACPI helpers with riscv_virt_ Date: Thu, 27 Aug 2026 02:42:22 +0800 Message-ID: <20260826184229.1145-9-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - virt_acpi_setup and virt_is_acpi_enabled collide with ARM virt when both architectures are linked into one qemu-system binary. - Rename the RISC-V helpers to riscv_virt_acpi_setup and riscv_virt_is_acpi_enabled. Leave file-local virt_acpi_build* names unchanged. Signed-off-by: Yonggang Luo Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/virt-acpi-build.c | 2 +- hw/riscv/virt.c | 6 +++--- include/hw/riscv/virt.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 59c454f4f94..832261391d5 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -1017,7 +1017,7 @@ static const VMStateDescription vmstate_virt_acpi_build = { }, }; -void virt_acpi_setup(RISCVVirtState *s) +void riscv_virt_acpi_setup(RISCVVirtState *s) { AcpiBuildTables tables; AcpiBuildState *build_state; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 9019a0a04d6..c53370a35f5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1293,8 +1293,8 @@ static void virt_machine_done(Notifier *notifier, void *data) virt_build_smbios(s); - if (virt_is_acpi_enabled(s)) { - virt_acpi_setup(s); + if (riscv_virt_is_acpi_enabled(s)) { + riscv_virt_acpi_setup(s); } } @@ -1652,7 +1652,7 @@ static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); } -bool virt_is_acpi_enabled(RISCVVirtState *s) +bool riscv_virt_is_acpi_enabled(RISCVVirtState *s) { return s->acpi != ON_OFF_AUTO_OFF; } diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 5559783aebb..38ad8b0097e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -133,9 +133,9 @@ enum { #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 1 + FDT_APLIC_INT_CELLS) -bool virt_is_acpi_enabled(RISCVVirtState *s); +bool riscv_virt_is_acpi_enabled(RISCVVirtState *s); bool virt_is_iommu_sys_enabled(RISCVVirtState *s); -void virt_acpi_setup(RISCVVirtState *vms); +void riscv_virt_acpi_setup(RISCVVirtState *vms); /* * The virt machine physical address space used by some of the devices From patchwork Wed Aug 26 18:42:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yonggang Luo X-Patchwork-Id: 2292938 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Wed, 26 Aug 2026 11:44:02 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:44:01 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 09/13] hw/loongarch/virt: prefix ACPI helper with loongarch_virt_ Date: Thu, 27 Aug 2026 02:42:23 +0800 Message-ID: <20260826184229.1145-10-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - virt_acpi_setup is the same C symbol used by ARM and RISC-V virt. Rename it now so a later combined binary does not need meson -D prefixes for LoongArch. - Rename the file-local virt_is_acpi_enabled to loongarch_virt_is_acpi_enabled to match. Signed-off-by: Yonggang Luo Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Song Gao --- hw/loongarch/virt-acpi-build.c | 6 +++--- hw/loongarch/virt.c | 2 +- include/hw/loongarch/virt.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c index a0b445f297b..bbbac289b49 100644 --- a/hw/loongarch/virt-acpi-build.c +++ b/hw/loongarch/virt-acpi-build.c @@ -674,7 +674,7 @@ static const VMStateDescription vmstate_acpi_build = { }, }; -static bool virt_is_acpi_enabled(LoongArchVirtMachineState *lvms) +static bool loongarch_virt_is_acpi_enabled(LoongArchVirtMachineState *lvms) { if (lvms->acpi == ON_OFF_AUTO_OFF) { return false; @@ -682,7 +682,7 @@ static bool virt_is_acpi_enabled(LoongArchVirtMachineState *lvms) return true; } -void virt_acpi_setup(LoongArchVirtMachineState *lvms) +void loongarch_virt_acpi_setup(LoongArchVirtMachineState *lvms) { AcpiBuildTables tables; AcpiBuildState *build_state; @@ -692,7 +692,7 @@ void virt_acpi_setup(LoongArchVirtMachineState *lvms) return; } - if (!virt_is_acpi_enabled(lvms)) { + if (!loongarch_virt_is_acpi_enabled(lvms)) { ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); return; } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 6693dea647b..74c9668b6e6 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -242,7 +242,7 @@ static void virt_done(Notifier *notifier, void *data) LoongArchVirtMachineState *lvms = container_of(notifier, LoongArchVirtMachineState, machine_done); virt_build_smbios(lvms); - virt_acpi_setup(lvms); + loongarch_virt_acpi_setup(lvms); virt_fdt_setup(lvms); } diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index d39a9bbf5dd..72268466def 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -132,7 +132,7 @@ struct LoongArchVirtMachineState { #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") OBJECT_DECLARE_SIMPLE_TYPE(LoongArchVirtMachineState, LOONGARCH_VIRT_MACHINE) -void virt_acpi_setup(LoongArchVirtMachineState *lvms); +void loongarch_virt_acpi_setup(LoongArchVirtMachineState *lvms); void virt_fdt_setup(LoongArchVirtMachineState *lvms); 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Wed, 26 Aug 2026 11:44:10 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 10/13] target/riscv: uniquify TCG crc32, crc32c, and wfi helper names Date: Thu, 27 Aug 2026 02:42:24 +0800 Message-ID: <20260826184229.1145-11-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=luoyonggang@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - ARM already exports helper_crc32, helper_crc32c, helper_wfi, and the matching helper_info_* objects. RISC-V used the same DEF_HELPER names, which collide in a combined qemu-system link. - Rename the RISC-V helpers to riscv_crc32, riscv_crc32c, and riscv_wfi so the generated C symbols are unique without meson -D prefixes. Signed-off-by: Yonggang Luo --- target/riscv/helper.h | 6 +++--- target/riscv/tcg/bitmanip_helper.c | 4 ++-- target/riscv/tcg/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/tcg/insn_trans/trans_xlrbr.c.inc | 4 ++-- target/riscv/tcg/op_helper.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 542b7c264fc..dd4623d2a79 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -84,8 +84,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) /* Floating Point - Half Precision */ DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) @@ -135,7 +135,7 @@ DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(ctr_clear, void, env) -DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(riscv_wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) diff --git a/target/riscv/tcg/bitmanip_helper.c b/target/riscv/tcg/bitmanip_helper.c index 1156a87dd31..18ad2fae1c9 100644 --- a/target/riscv/tcg/bitmanip_helper.c +++ b/target/riscv/tcg/bitmanip_helper.c @@ -132,7 +132,7 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2) return do_xperm(rs1, rs2, 3); } -target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32)(target_ulong rs1, target_ulong sz) { for (target_ulong i = 0; i < sz; i++) { rs1 = crc32_table[rs1 & 0xFF] ^ (rs1 >> 8); @@ -141,7 +141,7 @@ target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz) return rs1; } -target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32c)(target_ulong rs1, target_ulong sz) { for (target_ulong i = 0; i < sz; i++) { rs1 = crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8); diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/riscv/tcg/insn_trans/trans_privileged.c.inc index a8eaccef67e..0df78e89745 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -144,7 +144,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) #ifndef CONFIG_USER_ONLY decode_save_opc(ctx, 0); gen_update_pc(ctx, ctx->cur_insn_len); - gen_helper_wfi(tcg_env); + gen_helper_riscv_wfi(tcg_env); return true; #else return false; diff --git a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc index 01da2b6ce1d..795231f0839 100644 --- a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc +++ b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc @@ -29,11 +29,11 @@ static bool gen_crc(DisasContext *ctx, arg_r2 *a, #define TRANS_CRC32(NAME, SIZE) \ static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32, tcg_constant_tl(SIZE)); } #define TRANS_CRC32C(NAME, SIZE) \ static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32c, tcg_constant_tl(SIZE)); } TRANS_CRC32(b, 1); TRANS_CRC32(h, 2); diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index ba3c7da375a..52bcedc7c6e 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -541,7 +541,7 @@ void helper_ctr_clear(CPURISCVState *env) riscv_ctr_clear(env); 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Wed, 26 Aug 2026 11:44:19 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 11/13] system/vl: add new option -target Date: Thu, 27 Aug 2026 02:42:25 +0800 Message-ID: <20260826184229.1145-12-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=luoyonggang@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - Parse -target with QEMU_OPTION_nouserconfig, right after MODULE_INIT_TARGET_INFO, because later init depends on TargetInfo. - target_info_qom_set_target() takes Error **errp. A name comes from -target or from argv0 (qemu-system-aarch64). qemu-system with no suffix and no -target fails; use -target ? to list names. - Fuzz passes TARGET_NAME instead of relying on a unique TargetInfo. Signed-off-by: Pierrick Bouvier Signed-off-by: Yonggang Luo --- include/qemu/target-info-qom.h | 3 +- qemu-options.hx | 8 ++++ system/vl.c | 36 ++++++++++++---- target-info-qom.c | 77 ++++++++++++++++++++++++++++++---- tests/qtest/fuzz/fuzz.c | 2 +- 5 files changed, 110 insertions(+), 16 deletions(-) diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h index 842cf241e0a..9e56383ea6b 100644 --- a/include/qemu/target-info-qom.h +++ b/include/qemu/target-info-qom.h @@ -10,6 +10,7 @@ #define QEMU_TARGET_INFO_QOM_H #include "qemu/target-info-impl.h" +#include "qapi/error.h" #include "qom/object.h" #define TYPE_TARGET_INFO "target-info" @@ -40,7 +41,7 @@ typedef struct TargetInfoQomClass { OBJECT_DECLARE_TYPE(TargetInfoQom, TargetInfoQomClass, TARGET_INFO) -void target_info_qom_set_target(void); +void target_info_qom_set_target(const char *name, Error **errp); /** * get_machine_types_available: diff --git a/qemu-options.hx b/qemu-options.hx index 34970fffc94..824807be1d8 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -24,6 +24,14 @@ SRST Display version information and exit ERST +DEF("target", HAS_ARG, QEMU_OPTION_target, \ + "-target target selects the target architecture ('-target help' for list)\n", + QEMU_ARCH_ALL) +SRST +``-target target`` + Selects target architecture ('-target help' for list) +ERST + DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ "-machine [type=]name[,prop=value[,...]]\n" " selects emulated machine ('-machine help' for list)\n" diff --git a/system/vl.c b/system/vl.c index 4b1fcd2031f..28c5741c385 100644 --- a/system/vl.c +++ b/system/vl.c @@ -281,6 +281,15 @@ static QemuOptsList qemu_accel_opts = { }, }; +static QemuOptsList qemu_target_opts = { + .name = "target", + .implied_opt_name = "target", + .head = QTAILQ_HEAD_INITIALIZER(qemu_target_opts.head), + .desc = { + { /* end of list */ }, + }, +}; + static QemuOptsList qemu_boot_opts = { .name = "boot-opts", .implied_opt_name = "order", @@ -2856,6 +2865,7 @@ void qemu_init(int argc, char **argv) const char *optarg; MachineClass *machine_class; bool userconfig = true; + const char *target_name_option = NULL; FILE *vmstate_dump_file = NULL; qemu_add_opts(&qemu_drive_opts); @@ -2889,6 +2899,7 @@ void qemu_init(int argc, char **argv) qemu_add_opts(&qemu_semihosting_config_opts); qemu_add_opts(&qemu_fw_cfg_opts); qemu_add_opts(&qemu_action_opts); + qemu_add_opts(&qemu_target_opts); qemu_add_run_with_opts(); module_call_init(MODULE_INIT_OPTS); @@ -2898,13 +2909,6 @@ void qemu_init(int argc, char **argv) os_setup_limits(); module_call_init(MODULE_INIT_TARGET_INFO); - target_info_qom_set_target(); - - module_init_info(qemu_modinfo); - module_allow_arch(target_name()); - - qemu_init_subsystems(); - /* first pass of option parsing */ optind = 1; while (optind < argc) { @@ -2919,10 +2923,25 @@ void qemu_init(int argc, char **argv) case QEMU_OPTION_nouserconfig: userconfig = false; break; + case QEMU_OPTION_target: + target_name_option = optarg; + break; } } } + /* + * Identify target: first from option, then from argv[0]. + * This happens even before handling --help option, because it may contain + * entries that are target specific. + */ + target_info_qom_set_target(target_name_option, &error_fatal); + + module_init_info(qemu_modinfo); + module_allow_arch(target_name()); + + qemu_init_subsystems(); + machine_opts_dict = qdict_new(); if (userconfig) { qemu_read_default_config_file(&error_fatal); @@ -2946,6 +2965,9 @@ void qemu_init(int argc, char **argv) exit(1); } switch(popt->index) { + case QEMU_OPTION_target: + /* handled previously, ignore it here */ + break; case QEMU_OPTION_cpu: /* hw initialization will check this */ cpu_option = optarg; diff --git a/target-info-qom.c b/target-info-qom.c index 68ad734049c..5f7af028749 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -7,6 +7,7 @@ */ #include "qemu/osdep.h" +#include "qemu/help_option.h" #include "qapi/error.h" #include "qom/object.h" #include "qemu/target-info-impl.h" @@ -87,16 +88,78 @@ const TargetInfo *target_info(void) return target_info_ptr; } -void target_info_qom_set_target(void) +static void set_target_info(const TargetInfo *chosen) { - g_autoptr(GSList) targets = object_class_get_list(TYPE_TARGET_INFO, false); + target_info_ptr = chosen; +} + +static void list_targets_available(void) +{ + printf("List of targets available:\n"); + g_autoptr(GSList) targets = object_class_get_list_sorted(TYPE_TARGET_INFO, false); + for (GSList *elem = targets; elem; elem = elem->next) { + const TargetInfo *ti = TARGET_INFO_CLASS(elem->data)->target_info; + + printf("- %s\n", ti->target_name); + } +} + +static bool target_info_matches_name(const TargetInfo *ti, const char *name) +{ + return !strcmp(name, ti->target_name); +} + +/* qemu-system-aarch64[.exe] -> aarch64; qemu-system[.exe] -> NULL. */ +static const char *target_from_argv0(char *base) +{ + if (g_str_has_prefix(base, "qemu-system-")) { + return base + strlen("qemu-system-"); + } + return NULL; +} +void target_info_qom_set_target(const char *name, Error **errp) +{ + g_autoptr(GSList) targets = object_class_get_list(TYPE_TARGET_INFO, false); + g_autofree char *prg_base = NULL; size_t num_found = g_slist_length(targets); - if (num_found != 1) { - error_setg(&error_fatal, num_found == 0 ? - "no target-info is available" : - "more than one target-info is available"); + + if (num_found == 0) { + error_setg(errp, "no target-info is available"); + return; + } + + if (!name) { + const char *prg = g_get_prgname(); + if (prg && prg[0]) { + char *dot; + + prg_base = g_path_get_basename(prg); + dot = strrchr(prg_base, '.'); + if (dot && g_ascii_strcasecmp(dot, ".exe") == 0) { + *dot = '\0'; + } + name = target_from_argv0(prg_base); + } + } + + if (name) { + if (is_help_option(name)) { + list_targets_available(); + exit(0); + } + for (GSList *elem = targets; elem; elem = elem->next) { + const TargetInfo *ti = TARGET_INFO_CLASS(elem->data)->target_info; + if (target_info_matches_name(ti, name)) { + set_target_info(ti); + return; + } + } + error_setg(errp, "target '%s' is not available, " + "use -target ? to list available targets", name); + return; } - target_info_ptr = TARGET_INFO_CLASS(targets->data)->target_info; + error_setg(errp, "no target specified, " + "use -target ? to list available targets"); } diff --git a/tests/qtest/fuzz/fuzz.c b/tests/qtest/fuzz/fuzz.c index a3a131c80f8..c992fab4079 100644 --- a/tests/qtest/fuzz/fuzz.c +++ b/tests/qtest/fuzz/fuzz.c @@ -174,7 +174,7 @@ int LLVMFuzzerInitialize(int *argc, char ***argv, char ***envp) /* Initialize qgraph and modules */ qos_graph_init(); module_call_init(MODULE_INIT_TARGET_INFO); - target_info_qom_set_target(); + target_info_qom_set_target(fuzz_arch, &error_fatal); module_call_init(MODULE_INIT_FUZZ_TARGET); module_call_init(MODULE_INIT_QOM); module_call_init(MODULE_INIT_LIBQOS); From patchwork Wed Aug 26 18:42:26 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yonggang Luo X-Patchwork-Id: 2292946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Wed, 26 Aug 2026 11:44:28 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:44:27 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 12/13] target-info: dispatch CPU QMP, dump, and arm/riscv semihosting Date: Thu, 27 Aug 2026 02:42:26 +0800 Message-ID: <20260826184229.1145-13-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=luoyonggang@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - Combined binaries cannot keep one global C symbol per arch for query-cpu-definitions, dump notes, or Angel semihosting. Put those handlers on a process-wide TargetCpuOps table and fill one member at a time. - TARGET_INFO_CPU_OP is type_init (MODULE_INIT_QOM). That runs after target_info_qom_set_target(), so ELF constructors only queue the callback. target_info_register_cpu_op() stores the impl only when cpu_type matches the selected TargetInfo; a duplicate slot is reported and ignored. A NULL member means this target has no handler, not "too early". - Keep the table in target-info.c (common_ss) and filter with target_info()->cpu_type so user-mode can resolve TARGET_INFO_CPU_OP. Take the address of the impl so the same macro stores both function pointers and ops tables. - QMP query-cpu-definitions and query-cpu-model-expansion dispatch from hw/core/machine-qmp-cmds.c. Dump cpu_get_dump_info and cpu_get_note_size dispatch from hw/core/cpu-system.c. Arch handlers are static with an arch prefix (s390_query_*, arm_get_dump_info, ...). ppc and mips drop expansion stubs; the dispatcher errors instead. - Angel semihosting uses CPUSemihostingOps on TargetCpuOps.semihosting. ARM and RISC-V keep a static ops table in common-semi-target.c and register it with TARGET_INFO_CPU_OP. Wrappers in common-semi.h call target_info_cpu_ops()->semihosting. Always compile those files so both tables exist in a combined link. - Drop stubs/qmp-cpu.c and stubs/dump.c: every system binary has the wrappers, and tools do not implement these commands. Keep stubs/qmp-cpu-s390x.c for comparison/baseline. Signed-off-by: Yonggang Luo --- MAINTAINERS | 1 - hw/core/cpu-system.c | 23 +++++++++++ hw/core/machine-qmp-cmds.c | 26 +++++++++++++ include/qemu/target-info-qom.h | 39 +++++++++++++++++++ include/semihosting/common-semi.h | 56 ++++++++++++++++++++++++--- stubs/dump.c | 27 ------------- stubs/meson.build | 2 - stubs/qmp-cpu.c | 21 ---------- target-info.c | 32 +++++++++++++++ target/arm/arch_dump.c | 8 +++- target/arm/arm-qmp-cmds.c | 15 +++++-- target/arm/common-semi-target.c | 23 ++++++++--- target/arm/meson.build | 7 +--- target/i386/arch_dump.c | 8 +++- target/i386/cpu-system.c | 12 ++++-- target/i386/cpu.c | 6 ++- target/loongarch/arch_dump.c | 8 +++- target/loongarch/loongarch-qmp-cmds.c | 15 +++++-- target/mips/system/mips-qmp-cmds.c | 15 +++---- target/ppc/arch_dump.c | 8 +++- target/ppc/ppc-qmp-cmds.c | 15 +++---- target/riscv/arch_dump.c | 8 +++- target/riscv/common-semi-target.c | 25 ++++++++---- target/riscv/meson.build | 4 +- target/riscv/riscv-qmp-cmds.c | 15 +++++-- target/s390x/arch_dump.c | 8 +++- target/s390x/cpu_models_system.c | 15 +++++-- 27 files changed, 311 insertions(+), 131 deletions(-) delete mode 100644 stubs/dump.c delete mode 100644 stubs/qmp-cpu.c diff --git a/MAINTAINERS b/MAINTAINERS index 902db77218e..08e84e4ac6d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3348,7 +3348,6 @@ F: include/system/dump-arch.h F: include/system/dump.h F: qapi/dump.json F: scripts/dump-guest-memory.py -F: stubs/dump.c F: docs/specs/vmcoreinfo.rst F: tests/qtest/vmcoreinfo-test.c F: tests/qtest/dump-test.c diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 14eb4ed87f8..6dfbbac7f24 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -24,7 +24,9 @@ #include "exec/cputlb.h" #include "exec/target_page.h" #include "system/memory.h" +#include "system/dump-arch.h" #include "qemu/target-info.h" +#include "qemu/target-info-qom.h" #include "hw/core/qdev.h" #include "hw/core/qdev-properties.h" #include "hw/core/sysemu-cpu-ops.h" @@ -127,6 +129,27 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, return (*cpu->cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } +int cpu_get_dump_info(ArchDumpInfo *info, + const struct GuestPhysBlockList *guest_phys_blocks) +{ + const TargetCpuOps *ops = target_info_cpu_ops(); + + if (!ops->get_dump_info) { + return -1; + } + return ops->get_dump_info(info, guest_phys_blocks); +} + +ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +{ + const TargetCpuOps *ops = target_info_cpu_ops(); + + if (!ops->get_note_size) { + return -1; + } + return ops->get_note_size(class, machine, nr_cpus); +} + bool cpu_internal_is_big_endian(CPUState *cpu) { if (cpu->cc->sysemu_ops->internal_is_big_endian) { diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index e6e6ecc31e3..f8297203848 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -449,3 +449,29 @@ void qmp_dump_skeys(const char *filename, Error **errp) } DUMP_SKEYS_INTERFACE_CLASS(oc)->qmp_dump_skeys(filename, errp); } + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + const TargetCpuOps *ops = target_info_cpu_ops(); + + if (!ops->query_cpu_definitions) { + error_setg(errp, + "CPU model definitions are not supported on this target"); + return NULL; + } + return ops->query_cpu_definitions(errp); +} + +CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) +{ + const TargetCpuOps *ops = target_info_cpu_ops(); + + if (!ops->query_cpu_model_expansion) { + error_setg(errp, + "CPU model expansion is not supported on this target"); + return NULL; + } + return ops->query_cpu_model_expansion(type, model, errp); +} diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h index 9e56383ea6b..438663f9e1b 100644 --- a/include/qemu/target-info-qom.h +++ b/include/qemu/target-info-qom.h @@ -13,6 +13,45 @@ #include "qapi/error.h" #include "qom/object.h" +#include + +typedef struct ArchDumpInfo ArchDumpInfo; +struct GuestPhysBlockList; +typedef struct CPUSemihostingOps CPUSemihostingOps; + +typedef struct TargetCpuOps { + CpuDefinitionInfoList *(*query_cpu_definitions)(Error **errp); + CpuModelExpansionInfo *(*query_cpu_model_expansion)( + CpuModelExpansionType type, CpuModelInfo *model, Error **errp); + int (*get_dump_info)(ArchDumpInfo *info, + const struct GuestPhysBlockList *guest_phys_blocks); + ssize_t (*get_note_size)(int class, int machine, int nr_cpus); + const CPUSemihostingOps *semihosting; +} TargetCpuOps; + +/** + * target_info_register_cpu_op: + * @cpu_type: CPU_RESOLVING_TYPE of the registering architecture + * @offset: offsetof(TargetCpuOps, member) for the slot being filled + * @impl: handler or ops table stored at that offset + * + * Combined binaries merge one member at a time so QMP, dump, and + * semihosting (or split QMP files) can register independently. + * MODULE_INIT_QOM runs after target_info_qom_set_target(), so only + * the selected cpu_type is stored. + */ +void target_info_register_cpu_op(const char *cpu_type, size_t offset, + void *impl); +const TargetCpuOps *target_info_cpu_ops(void); + +#define TARGET_INFO_CPU_OP(cpu_type, member, impl) \ +static void glue(target_info_cpu_op_, impl)(void) \ +{ \ + target_info_register_cpu_op((cpu_type), offsetof(TargetCpuOps, member), \ + (void *)&(impl)); \ +} \ +type_init(glue(target_info_cpu_op_, impl)) + #define TYPE_TARGET_INFO "target-info" #define TYPE_TARGET_SPECIFIC "target-specific" diff --git a/include/semihosting/common-semi.h b/include/semihosting/common-semi.h index aa511a46f42..f86a855a3dd 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -34,12 +34,56 @@ #ifndef COMMON_SEMI_H #define COMMON_SEMI_H +#include "exec/cpu-common.h" +#include "qemu/target-info-qom.h" + +typedef struct CPUSemihostingOps { + uint64_t (*arg)(CPUState *cs, int argno); + void (*set_ret)(CPUState *cs, uint64_t ret); + bool (*is_64bit)(CPUArchState *env); + bool (*sys_exit_is_extended)(CPUState *cs); + uint64_t (*stack_bottom)(CPUState *cs); + bool (*has_synccache)(CPUArchState *env); +} CPUSemihostingOps; + void do_common_semihosting(CPUState *cs); -uint64_t common_semi_arg(CPUState *cs, int argno); -void common_semi_set_ret(CPUState *cs, uint64_t ret); -bool is_64bit_semihosting(CPUArchState *env); -bool common_semi_sys_exit_is_extended(CPUState *cs); -uint64_t common_semi_stack_bottom(CPUState *cs); -bool common_semi_has_synccache(CPUArchState *env); + +static inline const CPUSemihostingOps *cpu_semihosting_ops(void) +{ + const CPUSemihostingOps *ops = target_info_cpu_ops()->semihosting; + + g_assert(ops); + return ops; +} + +static inline uint64_t common_semi_arg(CPUState *cs, int argno) +{ + return cpu_semihosting_ops()->arg(cs, argno); +} + +static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +{ + cpu_semihosting_ops()->set_ret(cs, ret); +} + +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return cpu_semihosting_ops()->is_64bit(env); +} + +static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +{ + return cpu_semihosting_ops()->sys_exit_is_extended(cs); +} + +static inline uint64_t common_semi_stack_bottom(CPUState *cs) +{ + return cpu_semihosting_ops()->stack_bottom(cs); +} + +static inline bool common_semi_has_synccache(CPUArchState *env) +{ + return cpu_semihosting_ops()->has_synccache(env); +} #endif /* COMMON_SEMI_H */ diff --git a/stubs/dump.c b/stubs/dump.c deleted file mode 100644 index df7897b72b1..00000000000 --- a/stubs/dump.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * QEMU dump - * - * Copyright Fujitsu, Corp. 2011, 2012 - * - * Authors: - * Wen Congyang - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "system/dump-arch.h" - -int cpu_get_dump_info(ArchDumpInfo *info, - const struct GuestPhysBlockList *guest_phys_blocks) -{ - return -1; -} - -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) -{ - return -1; -} - diff --git a/stubs/meson.build b/stubs/meson.build index 3b2f2680b19..94024aef868 100644 --- a/stubs/meson.build +++ b/stubs/meson.build @@ -68,7 +68,6 @@ if have_system # adding more of these. If the symbol is used in specific_ss, # in particular, consider defining a preprocessor macro via # Kconfig or configs/targets/. - stub_ss.add(files('dump.c')) stub_ss.add(files('cmos.c')) stub_ss.add(files('fw_cfg.c')) if igvm.found() @@ -82,7 +81,6 @@ if have_system stub_ss.add(files('qmp-i386-sev.c')) stub_ss.add(files('qmp-i386-sgx.c')) stub_ss.add(files('qmp-i386-xen.c')) - stub_ss.add(files('qmp-cpu.c')) stub_ss.add(files('qmp-cpu-s390x.c')) stub_ss.add(files('qmp-cpu-s390x-kvm.c')) stub_ss.add(files('hmp-cmd-info_mem.c')) diff --git a/stubs/qmp-cpu.c b/stubs/qmp-cpu.c deleted file mode 100644 index a8c7ee89b9d..00000000000 --- a/stubs/qmp-cpu.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "qapi/qapi-commands-machine.h" - -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) -{ - error_setg(errp, "CPU model expansion is not supported on this target"); - return NULL; -} - -CpuDefinitionInfoList * -qmp_query_cpu_definitions(Error **errp) -{ - error_setg(errp, "CPU model definitions are not supported on this target"); - return NULL; -} diff --git a/target-info.c b/target-info.c index ce7f9797dce..aa4be08bb94 100644 --- a/target-info.c +++ b/target-info.c @@ -7,9 +7,11 @@ */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/target-info.h" #include "qemu/target-info-qapi.h" #include "qemu/target-info-impl.h" +#include "qemu/target-info-qom.h" #include "qapi/error.h" const char *target_name(void) @@ -124,3 +126,33 @@ bool target_config_xen(void) { return target_info()->config_xen; } + +static TargetCpuOps target_cpu_ops; + +void target_info_register_cpu_op(const char *cpu_type, size_t offset, + void *impl) +{ + const TargetInfo *ti = target_info(); + void **slot; + + g_assert(ti); + g_assert(offset + sizeof(void *) <= sizeof(TargetCpuOps)); + g_assert((offset % sizeof(void *)) == 0); + + if (strcmp(cpu_type, ti->cpu_type)) { + return; + } + + slot = (void **)((char *)&target_cpu_ops + offset); + if (*slot) { + error_report("TargetCpuOps already registered for type '%s' (offset %zu)", + cpu_type, offset); + return; + } + *slot = impl; +} + +const TargetCpuOps *target_info_cpu_ops(void) +{ + return &target_cpu_ops; +} diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 1dd79849c13..e072516bdac 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -24,6 +24,7 @@ #include "system/dump.h" #include "cpu-features.h" #include "internals.h" +#include "qemu/target-info-qom.h" /* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */ struct aarch64_user_regs { @@ -385,7 +386,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, return 0; } -int cpu_get_dump_info(ArchDumpInfo *info, +static int arm_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { ARMCPU *cpu; @@ -439,7 +440,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t arm_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu = ARM_CPU(first_cpu); size_t note_size; @@ -459,3 +460,6 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) return note_size * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, arm_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, arm_get_note_size); diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 83ec95c290f..c85bde5d79d 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -32,6 +32,7 @@ #include "qobject/qdict.h" #include "qom/qom-qobject.h" #include "cpu.h" +#include "qemu/target-info-qom.h" static GICCapability *gic_cap_new(int version) { @@ -79,9 +80,10 @@ static const char *cpu_model_advertised_features[] = { NULL }; -CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +arm_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { CpuModelExpansionInfo *expansion_info; const QDict *qdict_in; @@ -216,7 +218,7 @@ static void arm_cpu_add_definition(gpointer data, gpointer user_data) QAPI_LIST_PREPEND(*cpu_list, info); } -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *arm_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list = NULL; GSList *list; @@ -227,3 +229,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) return cpu_list; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + arm_query_cpu_definitions); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + arm_query_cpu_model_expansion); diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-target.c index 2b77ce9c17b..eccd3735df8 100644 --- a/target/arm/common-semi-target.c +++ b/target/arm/common-semi-target.c @@ -12,7 +12,7 @@ #include "semihosting/common-semi.h" #include "target/arm/cpu-qom.h" -uint64_t common_semi_arg(CPUState *cs, int argno) +static uint64_t arm_common_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -23,7 +23,7 @@ uint64_t common_semi_arg(CPUState *cs, int argno) } } -void common_semi_set_ret(CPUState *cs, uint64_t ret) +static void arm_common_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -34,25 +34,36 @@ void common_semi_set_ret(CPUState *cs, uint64_t ret) } } -bool common_semi_sys_exit_is_extended(CPUState *cs) +static bool arm_common_semi_sys_exit_is_extended(CPUState *cs) { return is_a64(cpu_env(cs)); } -bool is_64bit_semihosting(CPUArchState *env) +static bool arm_is_64bit_semihosting(CPUArchState *env) { return is_a64(env); } -uint64_t common_semi_stack_bottom(CPUState *cs) +static uint64_t arm_common_semi_stack_bottom(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; return is_a64(env) ? env->xregs[31] : env->regs[13]; } -bool common_semi_has_synccache(CPUArchState *env) +static bool arm_common_semi_has_synccache(CPUArchState *env) { /* Ok for A64, invalid for A32/T32 */ return is_a64(env); } + +static const CPUSemihostingOps arm_semihosting_ops = { + .arg = arm_common_semi_arg, + .set_ret = arm_common_semi_set_ret, + .is_64bit = arm_is_64bit_semihosting, + .sys_exit_is_extended = arm_common_semi_sys_exit_is_extended, + .stack_bottom = arm_common_semi_stack_bottom, + .has_synccache = arm_common_semi_has_synccache, +}; + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, semihosting, arm_semihosting_ops); diff --git a/target/arm/meson.build b/target/arm/meson.build index 0369f96b4cc..dfcec55bd97 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -44,13 +44,10 @@ arm_stubs_ss.add(files( arm_user_ss.add(files( 'el2-stubs.c', 'cpregs-omap-stub.c', + 'common-semi-target.c', )) -arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', - if_true: files('common-semi-target.c')) -arm_common_system_ss.add(files('cpu.c')) -arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', - if_true: files('common-semi-target.c')) +arm_common_system_ss.add(files('cpu.c', 'common-semi-target.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', diff --git a/target/i386/arch_dump.c b/target/i386/arch_dump.c index 16e47c4747d..c060b2b4ccb 100644 --- a/target/i386/arch_dump.c +++ b/target/i386/arch_dump.c @@ -16,6 +16,7 @@ #include "system/dump.h" #include "elf.h" #include "system/memory_mapping.h" +#include "qemu/target-info-qom.h" #define ELF_NOTE_SIZE(hdr_size, name_size, desc_size) \ ((DIV_ROUND_UP((hdr_size), 4) \ @@ -394,7 +395,7 @@ int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cs, return cpu_write_qemu_note(f, &cpu->env, s, 0); } -int cpu_get_dump_info(ArchDumpInfo *info, +static int x86_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { bool lma = false; @@ -429,7 +430,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t x86_get_note_size(int class, int machine, int nr_cpus) { int name_size = 5; /* "CORE" or "QEMU" */ size_t elf_note_size = 0; @@ -459,3 +460,6 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) return (elf_note_size + qemu_note_size) * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, x86_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, x86_get_note_size); diff --git a/target/i386/cpu-system.c b/target/i386/cpu-system.c index c8bbf0cbafd..d2babd1ba09 100644 --- a/target/i386/cpu-system.c +++ b/target/i386/cpu-system.c @@ -29,6 +29,7 @@ #include "qapi/qapi-commands-machine.h" #include "cpu-internal.h" +#include "qemu/target-info-qom.h" /* Return a QDict containing keys for all properties that can be included * in static expansion of CPU models. All properties set by x86_cpu_load_model() @@ -188,10 +189,10 @@ out: return xc; } -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +x86_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { X86CPU *xc = NULL; Error *err = NULL; @@ -241,6 +242,9 @@ out: return ret; } +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + x86_query_cpu_model_expansion); + void cpu_clear_apic_feature(CPUX86State *env) { env->features[FEAT_1_EDX] &= ~CPUID_APIC; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5805d33ab92..4e31b8a2a60 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -48,6 +48,7 @@ #include "system/address-spaces.h" #include "hw/core/boards.h" #include "hw/i386/sgx-epc.h" +#include "qemu/target-info-qom.h" #endif #include "system/qtest.h" #include "tcg/tcg-cpu.h" @@ -8191,7 +8192,7 @@ static void x86_cpu_definition_entry(gpointer data, gpointer user_data) QAPI_LIST_PREPEND(*cpu_list, info); } -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *x86_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list = NULL; GSList *list = get_sorted_cpu_model_list(); @@ -8200,6 +8201,9 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) return cpu_list; } +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + x86_query_cpu_definitions); + #endif /* !CONFIG_USER_ONLY */ static uint8_t x86_cpu_get_host_avx10_version(void) diff --git a/target/loongarch/arch_dump.c b/target/loongarch/arch_dump.c index 9d84faef969..af4ab5df5b5 100644 --- a/target/loongarch/arch_dump.c +++ b/target/loongarch/arch_dump.c @@ -22,6 +22,7 @@ #include "elf.h" #include "system/dump.h" #include "internals.h" +#include "qemu/target-info-qom.h" /* struct user_pt_regs from arch/loongarch/include/uapi/asm/ptrace.h */ struct loongarch_user_regs { @@ -142,7 +143,7 @@ int loongarch_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, return ret; } -int cpu_get_dump_info(ArchDumpInfo *info, +static int loongarch_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { info->d_machine = EM_LOONGARCH; @@ -152,7 +153,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t loongarch_get_note_size(int class, int machine, int nr_cpus) { size_t note_size = 0; @@ -162,3 +163,6 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) return note_size * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, loongarch_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, loongarch_get_note_size); diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c index f053f22bb8c..848ad640aee 100644 --- a/target/loongarch/loongarch-qmp-cmds.c +++ b/target/loongarch/loongarch-qmp-cmds.c @@ -14,6 +14,7 @@ #include "qobject/qdict.h" #include "qapi/qobject-input-visitor.h" #include "qom/qom-qobject.h" +#include "qemu/target-info-qom.h" static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) { @@ -28,7 +29,7 @@ static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) QAPI_LIST_PREPEND(*cpu_list, info); } -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *loongarch_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list = NULL; GSList *list; @@ -45,9 +46,10 @@ static const char *cpu_model_advertised_features[] = { "ptw", NULL }; -CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +loongarch_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { Visitor *visitor; CpuModelExpansionInfo *expansion_info; @@ -133,3 +135,8 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, return expansion_info; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + loongarch_query_cpu_definitions); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + loongarch_query_cpu_model_expansion); diff --git a/target/mips/system/mips-qmp-cmds.c b/target/mips/system/mips-qmp-cmds.c index b6a2874f2dd..ff78487423b 100644 --- a/target/mips/system/mips-qmp-cmds.c +++ b/target/mips/system/mips-qmp-cmds.c @@ -11,15 +11,7 @@ #include "qapi/error.h" #include "qapi/qapi-commands-machine.h" #include "cpu.h" - -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) -{ - error_setg(errp, "CPU model expansion is not supported on this target"); - return NULL; -} +#include "qemu/target-info-qom.h" static void mips_cpu_add_definition(gpointer data, gpointer user_data) { @@ -36,7 +28,7 @@ static void mips_cpu_add_definition(gpointer data, gpointer user_data) QAPI_LIST_PREPEND(*cpu_list, info); } -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *mips_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list = NULL; GSList *list; @@ -47,3 +39,6 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) return cpu_list; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + mips_query_cpu_definitions); diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index 80ac6c3e320..07f0c75c45e 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -17,6 +17,7 @@ #include "elf.h" #include "system/dump.h" #include "system/kvm.h" +#include "qemu/target-info-qom.h" #ifdef TARGET_PPC64 #define ELFCLASS ELFCLASS64 @@ -229,7 +230,7 @@ static const struct NoteFuncDescStruct { typedef struct NoteFuncDescStruct NoteFuncDesc; -int cpu_get_dump_info(ArchDumpInfo *info, +static int ppc_get_dump_info(ArchDumpInfo *info, const struct GuestPhysBlockList *guest_phys_blocks) { PowerPCCPU *cpu; @@ -257,7 +258,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t ppc_get_note_size(int class, int machine, int nr_cpus) { int name_size = 8; /* "CORE" or "QEMU" rounded */ size_t elf_note_size = 0; @@ -313,3 +314,6 @@ int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, PowerPCCPU *cpu = POWERPC_CPU(cs); return ppc_write_all_elf_notes("CORE", f, cpu, cpuid, s); } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, ppc_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, ppc_get_note_size); diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c index 96228919966..70fca0170b1 100644 --- a/target/ppc/ppc-qmp-cmds.c +++ b/target/ppc/ppc-qmp-cmds.c @@ -29,15 +29,7 @@ #include "qapi/qapi-commands-machine.h" #include "cpu-models.h" #include "cpu-qom.h" - -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) -{ - error_setg(errp, "CPU model expansion is not supported on this target"); - return NULL; -} +#include "qemu/target-info-qom.h" static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) { @@ -53,7 +45,7 @@ static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) QAPI_LIST_PREPEND(*first, info); } -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *ppc_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list = NULL; GSList *list; @@ -82,3 +74,6 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) return cpu_list; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + ppc_query_cpu_definitions); diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 12b68799070..7e4b584faa0 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "elf.h" #include "system/dump.h" +#include "qemu/target-info-qom.h" /* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */ struct riscv64_user_regs { @@ -161,7 +162,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, return ret; } -int cpu_get_dump_info(ArchDumpInfo *info, +static int riscv_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { RISCVCPU *cpu; @@ -187,7 +188,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t riscv_get_note_size(int class, int machine, int nr_cpus) { size_t note_size; @@ -199,3 +200,6 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) return note_size * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, riscv_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, riscv_get_note_size); diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-target.c index aeaeb88d536..aed9dfc5b68 100644 --- a/target/riscv/common-semi-target.c +++ b/target/riscv/common-semi-target.c @@ -12,38 +12,49 @@ #include "cpu.h" #include "semihosting/common-semi.h" -uint64_t common_semi_arg(CPUState *cs, int argno) +static uint64_t riscv_common_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; return env->gpr[xA0 + argno]; } -void common_semi_set_ret(CPUState *cs, uint64_t ret) +static void riscv_common_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; env->gpr[xA0] = ret; } -bool is_64bit_semihosting(CPUArchState *env) +static bool riscv_is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) != MXL_RV32; } -bool common_semi_sys_exit_is_extended(CPUState *cs) +static bool riscv_common_semi_sys_exit_is_extended(CPUState *cs) { - return is_64bit_semihosting(cpu_env(cs)); + return riscv_is_64bit_semihosting(cpu_env(cs)); } -uint64_t common_semi_stack_bottom(CPUState *cs) +static uint64_t riscv_common_semi_stack_bottom(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; return env->gpr[xSP]; } -bool common_semi_has_synccache(CPUArchState *env) +static bool riscv_common_semi_has_synccache(CPUArchState *env) { return true; } + +static const CPUSemihostingOps riscv_semihosting_ops = { + .arg = riscv_common_semi_arg, + .set_ret = riscv_common_semi_set_ret, + .is_64bit = riscv_is_64bit_semihosting, + .sys_exit_is_extended = riscv_common_semi_sys_exit_is_extended, + .stack_bottom = riscv_common_semi_stack_bottom, + .has_synccache = riscv_common_semi_has_synccache, +}; + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, semihosting, riscv_semihosting_ops); diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 42d0f6d538a..5adb6d1c9e7 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -11,12 +11,10 @@ gen = [ riscv_ss = ss.source_set() riscv_ss.add(gen) -riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', - if_true: files('common-semi-target.c')) - riscv_ss.add(files( 'cpu.c', 'gdbstub.c', + 'common-semi-target.c', )) riscv_system_ss = ss.source_set() diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 2647deef916..248e6a0eaf0 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -36,6 +36,7 @@ #include "cpu-qom.h" #include "cpu.h" #include "target/riscv/tcg/csr.h" +#include "qemu/target-info-qom.h" static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { @@ -54,7 +55,7 @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data) QAPI_LIST_PREPEND(*cpu_list, info); } -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *riscv_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list = NULL; GSList *list = object_class_get_list(TYPE_RISCV_CPU, false); @@ -154,9 +155,10 @@ err: visit_free(visitor); } -CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +riscv_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { CpuModelExpansionInfo *expansion_info; QDict *qdict_out; @@ -225,3 +227,8 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, return expansion_info; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + riscv_query_cpu_definitions); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + riscv_query_cpu_model_expansion); diff --git a/target/s390x/arch_dump.c b/target/s390x/arch_dump.c index 2c26e992959..c0334baa72f 100644 --- a/target/s390x/arch_dump.c +++ b/target/s390x/arch_dump.c @@ -18,6 +18,7 @@ #include "elf.h" #include "system/dump.h" #include "kvm/kvm_s390x.h" +#include "qemu/target-info-qom.h" #include "target/s390x/kvm/pv.h" struct S390xUserRegsStruct { @@ -449,7 +450,7 @@ static void arch_cleanup(DumpState *s) } } -int cpu_get_dump_info(ArchDumpInfo *info, +static int s390_get_dump_info(ArchDumpInfo *info, const struct GuestPhysBlockList *guest_phys_blocks) { info->d_machine = EM_S390; @@ -469,7 +470,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t s390_get_note_size(int class, int machine, int nr_cpus) { int name_size = 8; /* "LINUX" or "CORE" + pad */ size_t elf_note_size = 0; @@ -495,3 +496,6 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) return (elf_note_size) * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, s390_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, s390_get_note_size); diff --git a/target/s390x/cpu_models_system.c b/target/s390x/cpu_models_system.c index 5b846048675..5470bf55e20 100644 --- a/target/s390x/cpu_models_system.c +++ b/target/s390x/cpu_models_system.c @@ -20,6 +20,7 @@ #include "qapi/qobject-input-visitor.h" #include "qobject/qdict.h" #include "qapi/qapi-commands-machine.h" +#include "qemu/target-info-qom.h" static void list_add_feat(const char *name, void *opaque); @@ -82,7 +83,7 @@ static void create_cpu_model_list(ObjectClass *klass, void *opaque) QAPI_LIST_PREPEND(*cpu_list, info); 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Wed, 26 Aug 2026 11:44:37 -0700 (PDT) Received: from WIN-BH9M8FJACR9 ([103.94.185.75]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-3283d60c291sm17681846eec.6.2026.08.26.11.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:44:36 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Peter Maydell , Fabiano Rosas , Aurelien Jarno , qemu-riscv@nongnu.org, Song Gao <17746591750@163.com>, "Michael S. Tsirkin" , Jiaxun Yang , qemu-ppc@nongnu.org, Xianglai Li , David Hildenbrand , Richard Henderson , Palmer Dabbelt , Aleksandar Rikalo , Harsh Prateek Bora , Bibo Mao , Weiwei Li , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Matthew Rosato , Chinmay Rath , Alistair Francis , Alexander Bulekov , Chao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Laurent Vivier , Cornelia Huck , Zhao Liu , Eric Farman , qemu-s390x@nongnu.org, Paolo Bonzini , Stefan Hajnoczi , qemu-arm@nongnu.org, Ilya Leoshkevich , Darren Kenny , Sunil V L , Daniel Henrique Barboza , Ani Sinha , Nicholas Piggin , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Liu Zhiwei , Igor Mammedov Subject: [PATCH v2 13/13] meson: build single binary Date: Thu, 27 Aug 2026 02:42:27 +0800 Message-ID: <20260826184229.1145-14-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260826184229.1145-1-luoyonggang@gmail.com> References: <20260826184229.1145-1-luoyonggang@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=luoyonggang@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org - Add -Dsingle_binary / --enable-single-binary (default true) and --disable-single-binary to gate the combined qemu-system binary. - Map each base arch to a primary softmmu target (arm -> aarch64-softmmu, riscv -> riscv64-softmmu) that supplies arch_srcs. Sibling targets contribute target-info-def.c only. - Apply common_ss and system_ss once against the union of those base-arch configs so constructors and Kconfig stubs are not duplicated. - Build qemu-system only, including on Windows. Do not add qemu-systemw: a GUI twin would keep QEMU exporting data from the .exe into DLLs, and those data exports cannot be delay-loaded (qdev_prop_array and other qdev_prop_*). That would block enabling modules globally on Windows. Signed-off-by: Pierrick Bouvier Signed-off-by: Yonggang Luo --- meson.build | 69 +++++++++++++++++++++++++++++++++-- meson_options.txt | 2 + scripts/meson-buildoptions.sh | 3 ++ 3 files changed, 71 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 449d50f2983..eea54fd0ba3 100644 --- a/meson.build +++ b/meson.build @@ -4249,6 +4249,18 @@ if host_os == 'darwin' endif traceable = [] +single_binary_arch_objects = [] +single_binary_bases_config = {} +single_binary_deps = [] +single_binary_crates = [] +# base arch -> softmmu target that supplies arch_srcs +single_binary_primary = { + 'arm': 'aarch64-softmmu', + 'riscv': 'riscv64-softmmu', +} +if not get_option('single_binary') + single_binary_primary = {} +endif emulators = {} foreach target : target_dirs config_target = config_target_mak[target] @@ -4321,8 +4333,6 @@ foreach target : target_dirs endif endif - arch_srcs += files('target-info-def.c') - if target_base_arch in target_arch t = target_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() @@ -4391,8 +4401,9 @@ foreach target : target_dirs lib_deps += dep.partial_dependency(compile_args: true, includes: true) endforeach + target_info_src = files('target-info-def.c') lib = static_library('qemu-' + target, - sources: arch_srcs + genh, + sources: target_info_src + arch_srcs + genh, dependencies: lib_deps, objects: objects, include_directories: target_inc, @@ -4400,6 +4411,16 @@ foreach target : target_dirs build_by_default: false) if target.endswith('-softmmu') + if target_base_arch in single_binary_primary + single_binary_bases_config += config_target + single_binary_arch_objects += lib.extract_objects(target_info_src) + if target == single_binary_primary[target_base_arch] + single_binary_arch_objects += lib.extract_objects(arch_srcs) + single_binary_deps += arch_deps + single_binary_deps += target_stubs + single_binary_crates += main_rs + endif + endif execs = [{ 'name': 'qemu-system-' + target_name, 'win_subsystem': 'console', @@ -4481,6 +4502,47 @@ foreach target : target_dirs endforeach endforeach +if single_binary_arch_objects.length() != 0 + single_binary_objects = [] + foreach spec: [[common_ss, common_all], [system_ss, libsystem]] + src = spec[0].apply(single_binary_bases_config, strict: false) + single_binary_objects += spec[1].extract_objects(src.sources()) + single_binary_deps += src.dependencies() + endforeach + foreach base, tgt: single_binary_primary + if base in target_common_arch_libs + src = target_common_arch[base].apply(single_binary_bases_config, + strict: false) + single_binary_objects += target_common_arch_libs[base].extract_objects( + src.sources()) + single_binary_deps += src.dependencies() + endif + if base in target_common_system_arch_libs + src = target_common_system_arch[base].apply(single_binary_bases_config, + strict: false) + single_binary_objects += target_common_system_arch_libs[base].extract_objects( + src.sources()) + single_binary_deps += src.dependencies() + endif + endforeach + single_binary_objects += single_binary_arch_objects + + single_binary_link_args = emulator_link_args + single_binary_link_args += enable_modules ? ['@block.syms', '@qemu.syms'] : [] + emulator = executable('qemu-system', + sources: [single_binary_crates, files('system/main.c')], + dependencies: single_binary_deps + [sdl], + objects: single_binary_objects, + link_depends: [block_syms, qemu_syms], + link_args: single_binary_link_args, + install: true) + emulators += {'qemu-system': emulator} + traceable += [{ + 'exe': 'qemu-system', + 'probe-prefix': 'qemu.system.multi', + }] +endif + # Other build targets if get_option('plugins') @@ -4833,6 +4895,7 @@ if config_all_accel.has_key('CONFIG_TCG') endif endif summary_info += {'target list': ' '.join(target_dirs)} +summary_info += {'single binary': get_option('single_binary')} if have_system summary_info += {'default devices': get_option('default_devices')} summary_info += {'out of process emulation': multiprocess_allowed} diff --git a/meson_options.txt b/meson_options.txt index a07cb47d35e..9d86a46fba7 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -91,6 +91,8 @@ option('tcg', type: 'feature', value: 'enabled', description: 'TCG support') option('plugins', type: 'boolean', value: false, description: 'TCG plugins via shared library loading') +option('single_binary', type: 'boolean', value: true, + description: 'combined qemu-system binary') option('debug_tcg', type: 'boolean', value: false, description: 'TCG debugging') option('debug_remap', type: 'boolean', value: false, diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index c003985047c..d8e49111ac7 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -19,6 +19,7 @@ meson_options_help() { printf "%s\n" ' --disable-install-blobs install provided firmware blobs' printf "%s\n" ' --disable-qom-cast-debug cast debugging support' printf "%s\n" ' --disable-relocatable toggle relocatable install' + printf "%s\n" ' --disable-single-binary combined qemu-system binary' printf "%s\n" ' --docdir=VALUE Base directory for documentation installation' printf "%s\n" ' (can be empty) [share/doc]' printf "%s\n" ' --enable-asan enable address sanitizer' @@ -486,6 +487,8 @@ _meson_option_parse() { --disable-seccomp) printf "%s" -Dseccomp=disabled ;; --enable-selinux) printf "%s" -Dselinux=enabled ;; --disable-selinux) printf "%s" -Dselinux=disabled ;; + --enable-single-binary) printf "%s" -Dsingle_binary=true ;; + --disable-single-binary) printf "%s" -Dsingle_binary=false ;; --enable-slirp) printf "%s" -Dslirp=enabled ;; --disable-slirp) printf "%s" -Dslirp=disabled ;; --enable-slirp-smbd) printf "%s" -Dslirp_smbd=enabled ;;