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Mon, 18 May 2026 15:27:55 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:27:55 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:19 -0400 Subject: [PATCH v4 01/14] spacemit: k1: support multi-board infrastructure MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-1-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Restructure K1 SoC support to handle multiple boards through a single configuration: 1. Rename bananapi-f3_defconfig to spacemit_k1_defconfig. 2. Move all K1 board files to board/spacemit/k1/. 3. Replace TARGET_BANANAPI_F3 with TARGET_SPACEMIT_K1 and rename the board's .h header to k1.h. Eliminates the need for board-specific defconfigs while maintaining hardware compatibility. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - No change. --- arch/riscv/Kconfig | 8 ++++---- arch/riscv/cpu/k1/Kconfig | 4 ++++ board/spacemit/{bananapi-f3 => k1}/Kconfig | 6 +++--- board/spacemit/{bananapi-f3 => k1}/MAINTAINERS | 4 ++-- board/spacemit/{bananapi-f3 => k1}/Makefile | 0 board/spacemit/{bananapi-f3 => k1}/board.c | 0 configs/{bananapi-f3_defconfig => spacemit_k1_defconfig} | 2 +- doc/board/spacemit/bananapi-f3.rst | 2 +- include/configs/{bananapi-f3.h => k1.h} | 0 9 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ad7589123c6..485067ed266 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,9 +14,6 @@ config TARGET_ANDES_AE350 config TARGET_ANDES_VOYAGER bool "Support Andes Voyager Board" -config TARGET_BANANAPI_F3 - bool "Support BananaPi F3 Board" - config TARGET_BEAGLEBOARD_BEAGLEVFIRE bool "Support BeagleBoard BeagleV-Fire Board (based on Microchip MPFS)" @@ -50,6 +47,9 @@ config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 +config TARGET_SPACEMIT_K1 + bool "Support Spacemit K1 SoC" + config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board" select BOARD_LATE_INIT @@ -119,7 +119,7 @@ source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" source "board/sophgo/licheerv_nano/Kconfig" -source "board/spacemit/bananapi-f3/Kconfig" +source "board/spacemit/k1/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig index 14201df80f2..3701bf2b5da 100644 --- a/arch/riscv/cpu/k1/Kconfig +++ b/arch/riscv/cpu/k1/Kconfig @@ -2,6 +2,8 @@ # # Copyright (C) 2024, Kongyang Liu +if TARGET_SPACEMIT_K1 + config SPACEMIT_K1 bool select BINMAN @@ -17,3 +19,5 @@ config SPACEMIT_K1 imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT + +endif diff --git a/board/spacemit/bananapi-f3/Kconfig b/board/spacemit/k1/Kconfig similarity index 79% rename from board/spacemit/bananapi-f3/Kconfig rename to board/spacemit/k1/Kconfig index f89fa9af2c7..1c615f89b64 100644 --- a/board/spacemit/bananapi-f3/Kconfig +++ b/board/spacemit/k1/Kconfig @@ -1,7 +1,7 @@ -if TARGET_BANANAPI_F3 +if TARGET_SPACEMIT_K1 config SYS_BOARD - default "bananapi-f3" + default "k1" config SYS_VENDOR default "spacemit" @@ -10,7 +10,7 @@ config SYS_CPU default "k1" config SYS_CONFIG_NAME - default "bananapi-f3" + default "k1" config TEXT_BASE default 0x00200000 diff --git a/board/spacemit/bananapi-f3/MAINTAINERS b/board/spacemit/k1/MAINTAINERS similarity index 61% rename from board/spacemit/bananapi-f3/MAINTAINERS rename to board/spacemit/k1/MAINTAINERS index 131bad03181..b256cbe7978 100644 --- a/board/spacemit/bananapi-f3/MAINTAINERS +++ b/board/spacemit/k1/MAINTAINERS @@ -1,6 +1,6 @@ BananaPi F3 M: Huan Zhou S: Maintained -F: board/spacemit/bananapi-f3/ -F: configs/bananapi-f3_defconfig +F: board/spacemit/k1/ +F: configs/spacemit_k1_defconfig F: doc/board/spacemit/bananapi-f3.rst diff --git a/board/spacemit/bananapi-f3/Makefile b/board/spacemit/k1/Makefile similarity index 100% rename from board/spacemit/bananapi-f3/Makefile rename to board/spacemit/k1/Makefile diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/k1/board.c similarity index 100% rename from board/spacemit/bananapi-f3/board.c rename to board/spacemit/k1/board.c diff --git a/configs/bananapi-f3_defconfig b/configs/spacemit_k1_defconfig similarity index 95% rename from configs/bananapi-f3_defconfig rename to configs/spacemit_k1_defconfig index adecbee10f2..fae561bbf8a 100644 --- a/configs/bananapi-f3_defconfig +++ b/configs/spacemit_k1_defconfig @@ -6,7 +6,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-bananapi-f3" CONFIG_SYS_BOOTM_LEN=0xa000000 CONFIG_SYS_LOAD_ADDR=0x200000 -CONFIG_TARGET_BANANAPI_F3=y +CONFIG_TARGET_SPACEMIT_K1=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst index f2220950a3a..1ece2ce9d02 100644 --- a/doc/board/spacemit/bananapi-f3.rst +++ b/doc/board/spacemit/bananapi-f3.rst @@ -29,7 +29,7 @@ built for SpacemiT K1 SoC as below: .. code-block:: console cd - make bananapi-f3_defconfig + make spacemit_k1_defconfig make OPENSBI=/build/platform/generic/firmware/fw_dynamic.bin This will generate u-boot.itb diff --git a/include/configs/bananapi-f3.h b/include/configs/k1.h similarity index 100% rename from include/configs/bananapi-f3.h rename to include/configs/k1.h From patchwork Tue May 19 10:26:20 2026 Content-Type: text/plain; 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Mon, 18 May 2026 15:28:17 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.27.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:28:17 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:20 -0400 Subject: [PATCH v4 02/14] spacemit: k1: enable SPL with debug UART MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-2-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Add SPL support featuring debug UART output for early boot diagnostics on K1 SoC. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - Reuse upstream BPI-F3 DT in both SPL and U-Boot proper phases via OF_UPSTREAM; - Add SPL bootph-* markers in k1-bananapi-f3-u-boot.dtsi. --- arch/riscv/cpu/k1/Kconfig | 2 ++ arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 4 ++++ board/spacemit/k1/Makefile | 2 ++ board/spacemit/k1/spl.c | 24 ++++++++++++++++++++++++ configs/spacemit_k1_defconfig | 16 ++++++++++++++++ include/configs/k1.h | 6 ++++-- 6 files changed, 52 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig index 3701bf2b5da..b155535658d 100644 --- a/arch/riscv/cpu/k1/Kconfig +++ b/arch/riscv/cpu/k1/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # # Copyright (C) 2024, Kongyang Liu +# Copyright (C) 2025-2026, RISCstar Ltd. if TARGET_SPACEMIT_K1 @@ -9,6 +10,7 @@ config SPACEMIT_K1 select BINMAN select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 + select SUPPORT_SPL imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index 9e1925eb68e..4e4d0e0c49e 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -28,3 +28,7 @@ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", "pll1_d4", "pll1_d78_31p5", "pmua_aclk"; }; + +&uart0 { + bootph-pre-ram; +}; diff --git a/board/spacemit/k1/Makefile b/board/spacemit/k1/Makefile index 2168698402b..f9cbf4b0e06 100644 --- a/board/spacemit/k1/Makefile +++ b/board/spacemit/k1/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # # Copyright (c) 2024, Kongyang Liu +# Copyright (c) 2025-2026, RISCstar Ltd. obj-y := board.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c new file mode 100644 index 00000000000..e15cf5f1abf --- /dev/null +++ b/board/spacemit/k1/spl.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026, RISCstar Ltd. + */ + +#include + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed:%d\n", ret); + + riscv_cpu_setup(); + + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NONE; +} diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index fae561bbf8a..29050ece278 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -4,17 +4,30 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-bananapi-f3" +CONFIG_SPL_STACK=0xc083fb00 +CONFIG_SPL_TEXT_BASE=0xc0801000 +CONFIG_SPL_BSS_START_ADDR=0xc083fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SYS_BOOTM_LEN=0xa000000 CONFIG_SYS_LOAD_ADDR=0x200000 +CONFIG_SPL_SIZE_LIMIT=0x31000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xd4017000 +CONFIG_DEBUG_UART_CLOCK=14700000 CONFIG_TARGET_SPACEMIT_K1=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y +CONFIG_STACK_SIZE=0x100000 CONFIG_FIT=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_BOARD_INIT is not set +CONFIG_SPL_MAX_SIZE=0x33000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_HUSH_PARSER=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y @@ -22,5 +35,8 @@ CONFIG_CLK_SPACEMIT=y CONFIG_CLK_SPACEMIT_K1=y CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y +CONFIG_DEBUG_UART_NS16550=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y diff --git a/include/configs/k1.h b/include/configs/k1.h index 97cf4d72df0..15a40f2128f 100644 --- a/include/configs/k1.h +++ b/include/configs/k1.h @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2024, Kongyang Liu + * Copyright (C) 2025-2026, RISCstar Ltd. * */ #ifndef __CONFIG_H #define __CONFIG_H -#define CFG_SYS_SDRAM_BASE 0x0 -#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ +#define CFG_SYS_NS16550_CLK 14700000 +#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ +#define CFG_SYS_SDRAM_BASE 0x0 #endif /* __CONFIG_H */ From patchwork Tue May 19 10:26:21 2026 Content-Type: text/plain; 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Mon, 18 May 2026 15:28:41 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:28:41 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:21 -0400 Subject: [PATCH v4 03/14] configs: k1: enable early timer support MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-3-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Enable CONFIG_TIMER_EARLY to allow udelay() calls during early initialization phases. This is required for proper timing operations before the full timer driver is available. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - SPL_RISCV_MMODE (not SMODE); disable SPL SMP. - Add RISCV_MMODE_TIMERBASE/_TIMEROFF. - Enable SPL_REGMAP/SPL_SYSCON. --- configs/spacemit_k1_defconfig | 6 +++++- include/configs/k1.h | 5 +++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index 29050ece278..fd0d228992a 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -17,9 +17,10 @@ CONFIG_DEBUG_UART_CLOCK=14700000 CONFIG_TARGET_SPACEMIT_K1=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y +CONFIG_SPL_RISCV_MMODE=y +# CONFIG_SPL_SMP is not set CONFIG_STACK_SIZE=0x100000 CONFIG_FIT=y -CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CBSIZE=256 @@ -31,6 +32,8 @@ CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_HUSH_PARSER=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y CONFIG_CLK_SPACEMIT=y CONFIG_CLK_SPACEMIT_K1=y CONFIG_PINCTRL=y @@ -40,3 +43,4 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y +CONFIG_TIMER_EARLY=y diff --git a/include/configs/k1.h b/include/configs/k1.h index 15a40f2128f..e09c3594905 100644 --- a/include/configs/k1.h +++ b/include/configs/k1.h @@ -12,4 +12,9 @@ #define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ #define CFG_SYS_SDRAM_BASE 0x0 +#define RISCV_MMODE_TIMERBASE 0xe4000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 +#define RISCV_MMODE_TIMER_FREQ 24000000 +#define RISCV_SMODE_TIMER_FREQ 24000000 + #endif /* __CONFIG_H */ From patchwork Tue May 19 10:26:22 2026 Content-Type: text/plain; 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Mon, 18 May 2026 15:29:01 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:29:01 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:22 -0400 Subject: [PATCH v4 04/14] clk: spacemit: k1: prune SPL clock tree MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-4-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean K1 SPL runs from on-chip SRAM with a small pre-relocation malloc heap. Registering the full K1 clock tree would not fit, so split the tree on CONFIG_SPL_BUILD: the SPL build registers only the subset SPL needs (currently UART, SDHCI, I2C (TWSI), and their PLL/MPMU/APMU/APBC ancestors); the non-SPL build keeps the full tree. Where surviving SPL CCU definitions reference parent clocks outside that subset, use "clock-dummy", so framework parent lookups still resolve. Signed-off-by: Guodong Xu --- v4: - New patch. Prune SPL clock tree to the UART/SDHCI/I2C subset. --- drivers/clk/spacemit/clk-k1.c | 128 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/drivers/clk/spacemit/clk-k1.c b/drivers/clk/spacemit/clk-k1.c index 80eede251b8..6695c4379e1 100644 --- a/drivers/clk/spacemit/clk-k1.c +++ b/drivers/clk/spacemit/clk-k1.c @@ -44,6 +44,18 @@ static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +CCU_PLL_DEFINE(CLK_PLL1, pll1, pll1, "clock-24m", pll1_rate_tbl, + APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK, + CLK_SET_RATE_GATE); + +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D4, pll1_d4, pll1_d4, "pll1", APBS_PLL1_SWCR2, + BIT(3), 4, 1); +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D6, pll1_d6, pll1_d6, "pll1", APBS_PLL1_SWCR2, + BIT(5), 6, 1); +CCU_FACTOR_GATE_FLAGS_DEFINE(CLK_PLL1_D8, pll1_d8, pll1_d8, "pll1", + APBS_PLL1_SWCR2, BIT(7), 8, 1, CLK_IS_CRITICAL); +#else static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), }; @@ -131,9 +143,23 @@ CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D8, pll3_d8, pll3_d8, "pll3", APBS_PLL3_SWCR2, CCU_FACTOR_DEFINE(CLK_PLL3_20, pll3_20, pll3_20, "pll3_d8", 20, 1); CCU_FACTOR_DEFINE(CLK_PLL3_40, pll3_40, pll3_40, "pll3_d8", 10, 1); CCU_FACTOR_DEFINE(CLK_PLL3_80, pll3_80, pll3_80, "pll3_d8", 5, 1); +#endif /* APBS clocks end */ /* MPMU clocks start */ +#if IS_ENABLED(CONFIG_SPL_BUILD) +CCU_GATE_DEFINE(CLK_PLL1_614, pll1_d4_614p4, pll1_d4_614p4, "pll1_d4", + MPMU_ACGR, BIT(15), 0); +CCU_GATE_DEFINE(CLK_PLL1_409P6, pll1_d6_409p6, pll1_d6_409p6, "pll1_d6", + MPMU_ACGR, BIT(0), 0); +CCU_GATE_DEFINE(CLK_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8", + MPMU_ACGR, BIT(13), 0); +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_31P5, pll1_d78_31p5, pll1_d78_31p5, + "pll1_d4", MPMU_ACGR, BIT(6), 39, 2); +CCU_DDN_DEFINE(CLK_SLOW_UART2, slow_uart2_48, slow_uart2_48, + "pll1_d4_614p4", MPMU_SUCCR_1, + CCU_DDN_MASK(16, 13), 16, CCU_DDN_MASK(0, 13), 0, 2, 0); +#else CCU_GATE_DEFINE(CLK_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8", MPMU_ACGR, BIT(13), 0); @@ -251,9 +277,37 @@ CCU_GATE_DEFINE(CLK_WDT_BUS, wdt_bus_clk, wdt_bus_clk, "apb_clk", MPMU_WDTPCR, BIT(0), 0); CCU_GATE_DEFINE(CLK_RIPC, ripc_clk, ripc_clk, "apb_clk", MPMU_RIPCCR, 0x1, 0); +#endif /* MPMU clocks end */ /* APBC clocks start */ +#if IS_ENABLED(CONFIG_SPL_BUILD) +static const char * const uart_clk_parents[] = { + "clock-dummy", + "clock-dummy", + "slow_uart2_48", +}; + +CCU_MUX_GATE_DEFINE(CLK_UART0, uart0_clk, uart0_clk, uart_clk_parents, + ARRAY_SIZE(uart_clk_parents), APBC_UART1_CLK_RST, + 4, 3, BIT(1) | BIT(0), 0); + +static const char * const twsi_parents[] = { + "pll1_d78_31p5", +}; + +CCU_MUX_GATE_DEFINE(CLK_TWSI2, twsi2_clk, twsi2_clk, twsi_parents, + ARRAY_SIZE(twsi_parents), APBC_TWSI2_CLK_RST, + 4, 3, BIT(1) | BIT(0), 0); +/* + * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. + * Combine functional and bus bits together as a gate to avoid sharing the + * write-only register between different clock hardwares. + */ +CCU_GATE_DEFINE(CLK_TWSI8, twsi8_clk, twsi8_clk, "pll1_d78_31p5", + APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); + +#else static const char * const uart_clk_parents[] = { "pll1_m3d128_57p6", "slow_uart1_14p74", @@ -598,9 +652,44 @@ CCU_GATE_DEFINE(CLK_TSEN_BUS, tsen_bus_clk, tsen_bus_clk, "apb_clk", CCU_GATE_DEFINE(CLK_IPC_AP2AUD_BUS, ipc_ap2aud_bus_clk, ipc_ap2aud_bus_clk, "apb_clk", APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); +#endif /* APBC clocks end */ /* APMU clocks start */ +#if IS_ENABLED(CONFIG_SPL_BUILD) +static const char * const pmua_aclk_parents[] = { + "clock-dummy", + "pll1_d8_307p2", +}; + +CCU_MUX_DIV_FC_DEFINE(CLK_PMUA_ACLK, pmua_aclk, pmua_aclk, pmua_aclk_parents, + ARRAY_SIZE(pmua_aclk_parents), + APMU_ACLK_CLK_CTRL, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), + 0, 1, 0); + +CCU_GATE_DEFINE(CLK_SDH_AXI, sdh_axi_aclk, sdh_axi_aclk, "pmua_aclk", + APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); + +static const char * const sdh01_parents[] = { + "pll1_d6_409p6", +}; + +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_SDH0, sdh0_clk, sdh0_clk, sdh01_parents, + ARRAY_SIZE(sdh01_parents), + APMU_SDH0_CLK_RES_CTRL, + APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, + BIT(4), 0); + +static const char * const sdh2_parents[] = { + "pll1_d6_409p6", +}; + +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_SDH2, sdh2_clk, sdh2_clk, sdh2_parents, + ARRAY_SIZE(sdh2_parents), + APMU_SDH2_CLK_RES_CTRL, + APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, + BIT(4), 0); +#else static const char * const pmua_aclk_parents[] = { "pll1_d10_245p76", "pll1_d8_307p2", @@ -1082,8 +1171,17 @@ CCU_GATE_DEFINE(CLK_EMAC1_BUS, emac1_bus_clk, emac1_bus_clk, "pmua_aclk", CCU_GATE_DEFINE(CLK_EMAC1_PTP, emac1_ptp_clk, emac1_ptp_clk, "pll2_d6", APMU_EMAC1_CLK_RES_CTRL, BIT(15), 0); +#endif /* APMU clocks end */ +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k1_ccu_pll_clks[] = { + &pll1.common.clk, + &pll1_d4.common.clk, + &pll1_d6.common.clk, + &pll1_d8.common.clk, +}; +#else static struct clk *k1_ccu_pll_clks[] = { &pll1.common.clk, &pll2.common.clk, @@ -1121,6 +1219,7 @@ static struct clk *k1_ccu_pll_clks[] = { &pll3_40.common.clk, &pll3_20.common.clk, }; +#endif static const struct spacemit_ccu_data k1_ccu_pll_data = { .clks = k1_ccu_pll_clks, @@ -1128,6 +1227,15 @@ static const struct spacemit_ccu_data k1_ccu_pll_data = { .offset = K1_PLL_ID, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k1_ccu_mpmu_clks[] = { + &pll1_d4_614p4.common.clk, + &pll1_d6_409p6.common.clk, + &pll1_d8_307p2.common.clk, + &pll1_d78_31p5.common.clk, + &slow_uart2_48.common.clk, +}; +#else static struct clk *k1_ccu_mpmu_clks[] = { &pll1_d8_307p2.common.clk, &pll1_d32_76p8.common.clk, @@ -1167,6 +1275,7 @@ static struct clk *k1_ccu_mpmu_clks[] = { &i2s_bclk.common.clk, &wdt_bus_clk.common.clk, }; +#endif static const struct spacemit_ccu_data k1_ccu_mpmu_data = { .clks = k1_ccu_mpmu_clks, @@ -1174,6 +1283,13 @@ static const struct spacemit_ccu_data k1_ccu_mpmu_data = { .offset = K1_MPMU_ID, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k1_ccu_apbc_clks[] = { + &uart0_clk.common.clk, + &twsi2_clk.common.clk, + &twsi8_clk.common.clk, +}; +#else static struct clk *k1_ccu_apbc_clks[] = { &uart0_clk.common.clk, &uart2_clk.common.clk, @@ -1278,6 +1394,7 @@ static struct clk *k1_ccu_apbc_clks[] = { &sspa0_i2s_bclk.common.clk, &sspa1_i2s_bclk.common.clk, }; +#endif static const struct spacemit_ccu_data k1_ccu_apbc_data = { .clks = k1_ccu_apbc_clks, @@ -1285,6 +1402,14 @@ static const struct spacemit_ccu_data k1_ccu_apbc_data = { .offset = K1_APBC_ID, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k1_ccu_apmu_clks[] = { + &pmua_aclk.common.clk, + &sdh_axi_aclk.common.clk, + &sdh0_clk.common.clk, + &sdh2_clk.common.clk, +}; +#else static struct clk *k1_ccu_apmu_clks[] = { &cci550_clk.common.clk, &cpu_c0_hi_clk.common.clk, @@ -1349,6 +1474,7 @@ static struct clk *k1_ccu_apmu_clks[] = { &v2d_clk.common.clk, &emmc_bus_clk.common.clk, }; +#endif static int clk_k1_enable(struct clk *clk) { @@ -1486,6 +1612,8 @@ static int k1_pll_clk_probe(struct udevice *dev) const struct spacemit_ccu_data *data; int ret; + clk_register_fixed_rate(NULL, "clock-dummy", 0); + ret = regmap_init_mem(dev_ofnode(dev), &base_regmap); if (ret) return ret; From patchwork Tue May 19 10:26:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 2240082 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - SPL_SYS_MALLOC_F_LEN=0x4000. --- configs/spacemit_k1_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index fd0d228992a..23019266103 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -1,9 +1,11 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x5000 CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-bananapi-f3" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL_STACK=0xc083fb00 CONFIG_SPL_TEXT_BASE=0xc0801000 CONFIG_SPL_BSS_START_ADDR=0xc083fc00 @@ -29,11 +31,14 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SPL_MAX_SIZE=0x33000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_DM_RESET=y CONFIG_HUSH_PARSER=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y CONFIG_CLK_SPACEMIT=y CONFIG_CLK_SPACEMIT_K1=y CONFIG_PINCTRL=y @@ -44,3 +49,4 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER_EARLY=y +CONFIG_SPL_LIB_RATIONAL=y From patchwork Tue May 19 10:26:24 2026 Content-Type: text/plain; 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Mon, 18 May 2026 15:29:55 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.29.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:29:55 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:24 -0400 Subject: [PATCH v4 06/14] dts: k1: enable clocks in SPL MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-6-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Make the K1 clock controllers visible to SPL by tagging the four root fixed clocks (osc_32k, vctcxo_{1,3,24}m) and the four syscon nodes (mpmu, pll, apmu, apbc) with bootph-pre-ram in the BPI-F3 U-Boot overlay. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - Drop v3's separate k1-spl.dts (which #included k1.dtsi from the local fork); place SPL bootph-pre-ram markers in k1-bananapi-f3-u-boot.dtsi against the upstream-mirrored BPI-F3 DT. - Extend APBC clocks/clock-names with pll1_d78_31p5 (MPMU) and pll1_d4 (PLL controller). The kernel registers these via clk_register_fixed_factor at runtime; U-Boot's CCF resolves them through DT, so they must be listed for probe ordering. --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index 4e4d0e0c49e..fbee8763a21 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -32,3 +32,35 @@ &uart0 { bootph-pre-ram; }; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; From patchwork Tue May 19 10:26:25 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 2240084 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 18 May 2026 15:30:31 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:30:30 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:25 -0400 Subject: [PATCH v4 07/14] board: k1: initialize clock and serial devices in SPL MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-7-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Initialize clock and serial devices in SPL. Otherwise, the device driver won't be loaded in SPL. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - No change. --- board/spacemit/k1/spl.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c index e15cf5f1abf..78f26616347 100644 --- a/board/spacemit/k1/spl.c +++ b/board/spacemit/k1/spl.c @@ -3,8 +3,45 @@ * Copyright (c) 2025-2026, RISCstar Ltd. */ +#include +#include +#include #include +static void clk_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@d4090000", &dev); + if (ret) + panic("Fail to detect clock-controller@d4090000\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4050000", &dev); + if (ret) + panic("Fail to detect system-controller@d4050000\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4282800", &dev); + if (ret) + panic("Fail to detect system-controller@d4282800\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4015000", &dev); + if (ret) + panic("Fail to detect system-controller@d4015000\n"); + + if (device_active(dev)) + log_debug("clk: device is active\n"); + else + log_debug("clk: device not active, probing...\n"); +} + +void serial_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_SERIAL, 0, &dev); + if (ret) + panic("Serial uclass init failed: %d\n", ret); +} + void board_init_f(ulong dummy) { int ret; @@ -15,6 +52,8 @@ void board_init_f(ulong dummy) riscv_cpu_setup(); + clk_early_init(); + serial_early_init(); preloader_console_init(); } From patchwork Tue May 19 10:26:26 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 2240085 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=riscstar-com.20251104.gappssmtp.com header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256 header.s=20251104 header.b=dCiwUWZ8; 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Mon, 18 May 2026 15:30:52 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:30:51 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:26 -0400 Subject: [PATCH v4 08/14] i2c: k1: add I2C driver support MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-8-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Add I2C driver support on Spacemit K1 SoC using driver model. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu Reviewed-by: Heiko Schocher --- v4: - i2c reset lookup made optional (upstream DT omits 'resets'). - Drop unused 'resets' field from priv. --- drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/k1_i2c.c | 523 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/k1_i2c.h | 69 +++++++ 4 files changed, 600 insertions(+) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 37288a47eb7..814a20d629e 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -797,6 +797,13 @@ config SYS_I2C_IHS help Support for gdsys IHS I2C driver on FPGA bus. +config SYS_I2C_SPACEMIT_K1 + bool "Spacemit K1 I2C driver" + depends on DM_I2C + help + Support for Spacemit I2C controller. It's based on + Driver Model. + source "drivers/i2c/muxes/Kconfig" endif diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 2da649e97d3..0e3a0f9fb5f 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o +obj-$(CONFIG_SYS_I2C_SPACEMIT_K1) += k1_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o obj-$(CONFIG_SYS_I2C_SUN8I_RSB) += sun8i_rsb.o diff --git a/drivers/i2c/k1_i2c.c b/drivers/i2c/k1_i2c.c new file mode 100644 index 00000000000..a08ff15803d --- /dev/null +++ b/drivers/i2c/k1_i2c.c @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023-2026 Spacemit, Inc + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "k1_i2c.h" + +#define ICR_OFFSET 0x00 +#define ISR_OFFSET 0x04 +#define ISAR_OFFSET 0x08 +#define IDBR_OFFSET 0x0c +#define ILCR_OFFSET 0x10 +#define IWCR_OFFSET 0x14 +#define IRCR_OFFSET 0x18 +#define IBMR_OFFSET 0x1c +#define WFIFO_OFFSET 0x20 +#define WFIFO_WPTR_OFFSET 0x24 +#define WFIFO_RPTR_OFFSET 0x28 +#define RFIFO_OFFSET 0x2c +#define RFIFO_WPTR_OFFSET 0x30 +#define RFIFO_RPTR_OFFSET 0x34 + +/* All transfers are described by this data structure */ +struct k1_i2c_msg { + u8 condition; + u8 acknack; + u8 direction; + u8 data; +}; + +struct k1_i2c { + u32 icr; + u32 isr; + u32 isar; + u32 idbr; + u32 ilcr; + u32 iwcr; + u32 irst_cyc; + u32 ibmr; +}; + +struct k1_i2c_priv { + int id; + void __iomem *base; + struct clk clk; + u32 clk_rate; +}; + +/* + * i2c_reset: - reset the host controller + * + */ +static void i2c_reset(void __iomem *base) +{ + u32 icr_mode; + u32 val; + + /* Save bus mode (standard or fast speed) for later use */ + icr_mode = readl(base + ICR_OFFSET) & ICR_MODE_MASK; + /* disable unit */ + val = readl(base + ICR_OFFSET); + writel(val & ~ICR_IUE, base + ICR_OFFSET); + udelay(10); + /* reset the unit */ + val = readl(base + ICR_OFFSET); + val |= ICR_UR; + writel(val, base + ICR_OFFSET); + udelay(100); + /* disable unit */ + val = readl(base + ICR_OFFSET); + writel(val & ~ICR_IUE, base + ICR_OFFSET); + + /* set slave address */ + writel(0x00, base + ISR_OFFSET); + /* set control reg values */ + writel(I2C_ICR_INIT | icr_mode, base + ICR_OFFSET); + writel(I2C_ISR_INIT, base + ISR_OFFSET); /* set clear interrupt bits */ + val = readl(base + ICR_OFFSET); + val |= ICR_IUE; + writel(val, base + ICR_OFFSET); /* enable unit */ + udelay(100); +} + +static inline bool is_isr_set_or_clr(unsigned long isr, unsigned long set_mask, + unsigned long clr_mask) +{ + return ((isr & set_mask) == set_mask) && ((isr & clr_mask) == 0); +} + +/* + * i2c_isr_set_cleared: - wait until certain bits of the I2C status register + * are set and cleared + * + * @return: 0 on success or -ETIMEDOUT. + */ +static int i2c_isr_set_cleared(void __iomem *base, unsigned long set_mask, + unsigned long clr_mask) +{ + int cnt = 1000, delay = 10, isr, ret; + + ret = read_poll_timeout(readl, isr, + is_isr_set_or_clr(isr, set_mask, clr_mask), + delay, delay * cnt, base + ISR_OFFSET); + return ret; +} + +/* + * i2c_transfer: - Transfer one byte over the i2c bus + * + * This function can transfer a byte over the i2c bus in both directions. + * It is used by the public API functions. + * + * @return: 0: transfer successful or error code + */ +static int i2c_transfer(void __iomem *base, struct k1_i2c_msg *msg) +{ + int ret; + u32 val; + + if (!msg) + goto transfer_error_msg_empty; + + switch (msg->direction) { + case I2C_WRITE: + /* check if bus is not busy */ + if (i2c_isr_set_cleared(base, 0, ISR_IBB)) + goto transfer_error_bus_busy; + + /* start transmission */ + val = readl(base + ICR_OFFSET); + val &= ~ICR_START; + writel(val, base + ICR_OFFSET); + val = readl(base + ICR_OFFSET); + val &= ~ICR_STOP; + writel(val, base + ICR_OFFSET); + writel(msg->data, base + IDBR_OFFSET); + if (msg->condition == I2C_COND_START) { + val = readl(base + ICR_OFFSET); + val |= ICR_START; + writel(val, base + ICR_OFFSET); + } + if (msg->condition == I2C_COND_STOP) { + val = readl(base + ICR_OFFSET); + val |= ICR_STOP; + writel(val, base + ICR_OFFSET); + } + if (msg->acknack == I2C_ACKNAK_SENDNAK) { + val = readl(base + ICR_OFFSET); + val |= ICR_ACKNAK; + writel(val, base + ICR_OFFSET); + } + if (msg->acknack == I2C_ACKNAK_SENDACK) { + val = readl(base + ICR_OFFSET); + val &= ~ICR_ACKNAK; + writel(val, base + ICR_OFFSET); + } + val = readl(base + ICR_OFFSET); + val &= ~ICR_ALDIE; + writel(val, base + ICR_OFFSET); + val = readl(base + ICR_OFFSET); + val |= ICR_TB; + writel(val, base + ICR_OFFSET); + + /* transmit register empty? */ + if (i2c_isr_set_cleared(base, ISR_ITE, 0)) + goto transfer_error_transmit_timeout; + + /* clear 'transmit empty' state */ + val = readl(base + ISR_OFFSET); + val |= ISR_ITE; + writel(val, base + ISR_OFFSET); + + /* wait for ACK from slave */ + if (msg->acknack == I2C_ACKNAK_WAITACK) + if (i2c_isr_set_cleared(base, 0, ISR_ACKNAK)) + goto transfer_error_ack_missing; + break; + + case I2C_READ: + /* check if bus is not busy */ + if (i2c_isr_set_cleared(base, 0, ISR_IBB)) + goto transfer_error_bus_busy; + + /* start receive */ + val = readl(base + ICR_OFFSET); + val &= ~ICR_START; + writel(val, base + ICR_OFFSET); + val = readl(base + ICR_OFFSET); + val &= ~ICR_STOP; + writel(val, base + ICR_OFFSET); + if (msg->condition == I2C_COND_START) { + val = readl(base + ICR_OFFSET); + val |= ICR_START; + writel(val, base + ICR_OFFSET); + } + if (msg->condition == I2C_COND_STOP) { + val = readl(base + ICR_OFFSET); + val |= ICR_STOP; + writel(val, base + ICR_OFFSET); + } + if (msg->acknack == I2C_ACKNAK_SENDNAK) { + val = readl(base + ICR_OFFSET); + val |= ICR_ACKNAK; + writel(val, base + ICR_OFFSET); + } + if (msg->acknack == I2C_ACKNAK_SENDACK) { + val = readl(base + ICR_OFFSET); + val &= ~ICR_ACKNAK; + writel(val, base + ICR_OFFSET); + } + val = readl(base + ICR_OFFSET); + val &= ~ICR_ALDIE; + writel(val, base + ICR_OFFSET); + val = readl(base + ICR_OFFSET); + val |= ICR_TB; + writel(val, base + ICR_OFFSET); + + /* receive register full? */ + if (i2c_isr_set_cleared(base, ISR_IRF, 0)) + goto transfer_error_receive_timeout; + + msg->data = readl(base + IDBR_OFFSET); + + /* clear 'receive empty' state */ + val = readl(base + ISR_OFFSET); + val |= ISR_IRF; + writel(val, base + ISR_OFFSET); + break; + default: + goto transfer_error_illegal_param; + } + + return 0; + +transfer_error_msg_empty: + debug("%s: error: 'msg' is empty\n", __func__); + ret = -EINVAL; + goto i2c_transfer_finish; + +transfer_error_transmit_timeout: + debug("%s: error: transmit timeout\n", __func__); + ret = -ETIMEDOUT; + goto i2c_transfer_finish; + +transfer_error_ack_missing: + debug("%s: error: ACK missing\n", __func__); + ret = -EREMOTEIO; + goto i2c_transfer_finish; + +transfer_error_receive_timeout: + debug("%s: error: receive timeout\n", __func__); + ret = -ETIMEDOUT; + goto i2c_transfer_finish; + +transfer_error_illegal_param: + debug("%s: error: illegal parameters\n", __func__); + ret = -EINVAL; + goto i2c_transfer_finish; + +transfer_error_bus_busy: + debug("%s: error: bus is busy\n", __func__); + ret = -EIO; + goto i2c_transfer_finish; + +i2c_transfer_finish: + debug("%s: ISR: 0x%04x\n", __func__, readl(base + ISR_OFFSET)); + i2c_reset(base); + return ret; +} + +static int __i2c_read(void __iomem *base, uchar chip, u8 *addr, int alen, + uchar *buffer, int len) +{ + struct k1_i2c_msg msg; + int ret; + + debug("%s(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n", + __func__, chip, *addr, alen, len); + + if (len == 0) { + pr_err("reading zero byte is invalid\n"); + return -EINVAL; + } + + i2c_reset(base); + + /* dummy chip address write */ + debug("%s: dummy chip address write\n", __func__); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data &= 0xFE; + ret = i2c_transfer(base, &msg); + if (ret) + return ret; + + /* + * send memory address bytes; + * alen defines how much bytes we have to send. + */ + while (--alen >= 0) { + debug("%s: send address byte %02x (alen=%d)\n", + __func__, *addr, alen); + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = addr[alen]; + ret = i2c_transfer(base, &msg); + if (ret) + return ret; + } + + /* start read sequence */ + debug("%s: start read sequence\n", __func__); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data |= 0x01; + ret = i2c_transfer(base, &msg); + if (ret) + return ret; + + /* read bytes; send NACK at last byte */ + while (len--) { + if (len == 0) { + msg.condition = I2C_COND_STOP; + msg.acknack = I2C_ACKNAK_SENDNAK; + } else { + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_SENDACK; + } + + msg.direction = I2C_READ; + msg.data = 0x00; + ret = i2c_transfer(base, &msg); + if (ret) + return ret; + + *buffer = msg.data; + debug("%s: reading byte (%p)=0x%02x\n", + __func__, buffer, *buffer); + buffer++; + } + + i2c_reset(base); + + return 0; +} + +static int __i2c_write(struct k1_i2c *base, uchar chip, u8 *addr, int alen, + uchar *buffer, int len) +{ + struct k1_i2c_msg msg; + int ret; + + debug("%s(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n", + __func__, chip, *addr, alen, len); + + i2c_reset(base); + + /* chip address write */ + debug("%s: chip address write\n", __func__); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data &= 0xFE; + ret = i2c_transfer(base, &msg); + if (ret) + return ret; + + /* + * send memory address bytes; + * alen defines how much bytes we have to send. + */ + while (--alen >= 0) { + debug("%s: send address byte %02x (alen=%d)\n", + __func__, *addr, alen); + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = addr[alen]; + ret = i2c_transfer(base, &msg); + if (ret) + return ret; + } + + /* write bytes; send NACK at last byte */ + while (len--) { + debug("%s: writing byte (%p)=0x%02x\n", + __func__, buffer, *buffer); + + if (len == 0) + msg.condition = I2C_COND_STOP; + else + msg.condition = I2C_COND_NORMAL; + + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = *(buffer++); + + ret = i2c_transfer(base, &msg); + if (ret) + return ret; + } + + i2c_reset(base); + + return 0; +} + +static int k1_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct k1_i2c_priv *i2c = dev_get_priv(bus); + struct i2c_msg *dmsg, *omsg, dummy; + + memset(&dummy, 0, sizeof(struct i2c_msg)); + + /* + * We expect either two messages (one with an offset and one with the + * actual data) or one message (just data or offset/data combined) + */ + if (nmsgs > 2 || nmsgs == 0) { + debug("%s: Only one or two messages are supported.", __func__); + return -EINVAL; + } + + omsg = nmsgs == 1 ? &dummy : msg; + dmsg = nmsgs == 1 ? msg : msg + 1; + + if (dmsg->flags & I2C_M_RD) + return __i2c_read(i2c->base, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len); + else + return __i2c_write(i2c->base, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len); +} + +static int k1_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct k1_i2c_priv *priv = dev_get_priv(bus); + void __iomem *base = priv->base; + u32 val; + + if (speed > I2C_SPEED_STANDARD_RATE) + val = ICR_FM; + else + val = ICR_SM; + clrsetbits_le32(base + ICR_OFFSET, ICR_MODE_MASK, val); + + return 0; +} + +static int k1_i2c_probe(struct udevice *bus) +{ + struct k1_i2c_priv *priv = dev_get_priv(bus); + struct reset_ctl reset; + int ret; + + priv->id = dev_seq(bus); + + /* + * The upstream K1 dts intentionally omits the 'resets' property + * on i2c nodes — the apbc clock-enable path performs the + * controller reset internally as part of clock gating. Treat the + * reset lookup as optional so we work on the kernel-mainline DT. + */ + ret = reset_get_by_index(bus, 0, &reset); + if (!ret) { + reset_assert(&reset); + udelay(10); + reset_deassert(&reset); + udelay(10); + } else if (ret != -ENOENT && ret != -ENODATA) { + dev_err(bus, "%s: reset lookup failed (%d)\n", __func__, ret); + return ret; + } + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS && ret != -EOPNOTSUPP) { + debug("%s: failed to enable clock\n", __func__); + return ret; + } + priv->clk_rate = clk_get_rate(&priv->clk); + + priv->base = (void *)devfdt_get_addr_ptr(bus); + k1_i2c_set_bus_speed(bus, priv->clk_rate); + return 0; +} + +static const struct dm_i2c_ops k1_i2c_ops = { + .xfer = k1_i2c_xfer, + .set_bus_speed = k1_i2c_set_bus_speed, +}; + +static const struct udevice_id k1_i2c_ids[] = { + { .compatible = "spacemit,k1-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_spacemit) = { + .name = "i2c_spacemit", + .id = UCLASS_I2C, + .of_match = k1_i2c_ids, + .probe = k1_i2c_probe, + .priv_auto = sizeof(struct k1_i2c_priv), + .ops = &k1_i2c_ops, +}; diff --git a/drivers/i2c/k1_i2c.h b/drivers/i2c/k1_i2c.h new file mode 100644 index 00000000000..856947aa43b --- /dev/null +++ b/drivers/i2c/k1_i2c.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023-2026 Spacemit Ltd. + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#ifndef __SPACEMIT_I2C_H +#define __SPACEMIT_I2C_H + +/* Shall the current transfer have a start/stop condition? */ +#define I2C_COND_NORMAL 0 +#define I2C_COND_START 1 +#define I2C_COND_STOP 2 + +/* Shall the current transfer be ack/nacked or being waited for it? */ +#define I2C_ACKNAK_WAITACK 1 +#define I2C_ACKNAK_SENDACK 2 +#define I2C_ACKNAK_SENDNAK 4 + +/* Specify who shall transfer the data (master or slave) */ +#define I2C_READ 0 +#define I2C_WRITE 1 + +#if (CONFIG_SYS_I2C_SPEED == 400000) +#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | \ + ICR_GCD | ICR_SCLE) +#else +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | \ + ICR_SCLE) +#endif + +/* ----- Control register bits ---------------------------------------- */ + +#define ICR_START 0x1 /* start bit */ +#define ICR_STOP 0x2 /* stop bit */ +#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ +#define ICR_TB 0x8 /* transfer byte bit */ +#define ICR_MA BIT(12) /* master abort */ +#define ICR_SCLE BIT(13) /* master clock enable, mona SCLEA */ +#define ICR_IUE BIT(14) /* unit enable */ +#define ICR_GCD BIT(21) /* general call disable */ +#define ICR_ITEIE BIT(19) /* enable tx interrupts */ +#define ICR_IRFIE BIT(20) /* enable rx interrupts, mona: DRFIE */ +#define ICR_BEIE BIT(22) /* enable bus error ints */ +#define ICR_SSDIE BIT(24) /* slave STOP detected int enable */ +#define ICR_ALDIE BIT(18) /* enable arbitration interrupt */ +#define ICR_SADIE BIT(23) /* slave address detected int enable */ +#define ICR_UR BIT(10) /* unit reset */ +#define ICR_SM (0x0) /* Standard Mode */ +#define ICR_FM BIT(8) /* Fast Mode */ +#define ICR_MODE_MASK (0x300) /* Mode mask */ + +/* ----- Status register bits ----------------------------------------- */ + +#define ISR_RWM BIT(13) /* read/write mode */ +#define ISR_ACKNAK BIT(14) /* ack/nak status */ +#define ISR_UB BIT(15) /* unit busy */ +#define ISR_IBB BIT(16) /* bus busy */ +#define ISR_SSD BIT(24) /* slave stop detected */ +#define ISR_ALD BIT(18) /* arbitration loss detected */ +#define ISR_ITE BIT(19) /* tx buffer empty */ +#define ISR_IRF BIT(20) /* rx buffer full */ +#define ISR_GCAD BIT(21) /* general call address detected */ +#define ISR_SAD BIT(23) /* slave address detected */ +#define ISR_BED BIT(22) /* bus error no ACK/NAK */ + +#define I2C_ISR_INIT 0x1FDE000 + +#endif From patchwork Tue May 19 10:26:27 2026 Content-Type: text/plain; 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Mon, 18 May 2026 15:31:27 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:31:27 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:27 -0400 Subject: [PATCH v4 09/14] spacemit: k1: add TLV EEPROM support in SPL MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-9-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao And support for required components including clock, I2C controller, and I2C EEPROM. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - DT: drop forked i2c/eeprom nodes; only bootph markers in overlay. - Drop reset_early_init(). - spl_boot_device() -> BOOT_DEVICE_NOR; stub pmic_init/spl_board_init. - Enable SPL_I2C/SPL_I2C_EEPROM/SPL_CMD_TLV_EEPROM. --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 9 +++ board/spacemit/k1/spl.c | 93 ++++++++++++++++++++++++++++++- board/spacemit/k1/tlv_codes.h | 22 ++++++++ configs/spacemit_k1_defconfig | 8 +++ 4 files changed, 131 insertions(+), 1 deletion(-) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index fbee8763a21..ac56bf512ad 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -64,3 +64,12 @@ &syscon_apbc { bootph-pre-ram; }; + +&i2c2 { + bootph-pre-ram; + resets = <&syscon_apbc RESET_TWSI2>; + + eeprom@50 { + bootph-pre-ram; + }; +}; diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c index 78f26616347..e862548f980 100644 --- a/board/spacemit/k1/spl.c +++ b/board/spacemit/k1/spl.c @@ -3,10 +3,77 @@ * Copyright (c) 2025-2026, RISCstar Ltd. */ +#include +#include +#include +#include #include #include +#include +#include #include #include +#include + +#define MUX_MODE4 4 +#define EDGE_NONE BIT(6) +#define PULL_UP (6 << 13) /* bit[15:13] 110 */ +#define PAD_DS_MEDIUM BIT(12) +#define PAD_1V8_DS2 PAD_DS_MEDIUM +#define I2C_PIN_CONFIG(x) ((x) | EDGE_NONE | PULL_UP | PAD_1V8_DS2) +#define I2C_BUF_SIZE 64 + +#define MFP_GPIO_84 0xd401e154 +#define MFP_GPIO_85 0xd401e158 + +static void i2c_early_init(void) +{ + struct udevice *bus; + + // eeprom: I2C2, pin group(GPIO_84, GPIO_85) + writel(I2C_PIN_CONFIG(MUX_MODE4), (void __iomem *)MFP_GPIO_84); + writel(I2C_PIN_CONFIG(MUX_MODE4), (void __iomem *)MFP_GPIO_85); + udelay(100); + uclass_first_device(UCLASS_I2C, &bus); + while (bus) { + uclass_next_device(&bus); + if (!bus) + break; + } +} + +int read_product_name(char *name, int size) +{ + u8 eeprom_data[TLV_TOTAL_LEN_MAX], *p; + struct tlvinfo_header *tlv_hdr; + struct tlvinfo_tlv *tlv_entry; + int ret, i = 0; + u32 entry_size; + + if (!name || size <= 0) + return -EINVAL; + ret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr, + &tlv_entry, i); + if (ret) + return ret; + p = (u8 *)tlv_entry; + for (i = 0; i < tlv_hdr->totallen; ) { + if (tlv_entry->type == TLV_CODE_PRODUCT_NAME) { + if (tlv_entry->length < size) + size = tlv_entry->length; + memset(name, 0, size); + memcpy(name, &tlv_entry->value[0], size); + return 0; + } + if (tlv_entry->type == TLV_CODE_CRC_32) + return -ENOENT; + entry_size = tlv_entry->length + sizeof(struct tlvinfo_tlv); + i += entry_size; + p += entry_size; + tlv_entry = (struct tlvinfo_tlv *)p; + } + return -ENOENT; +} static void clk_early_init(void) { @@ -44,6 +111,7 @@ void serial_early_init(void) void board_init_f(ulong dummy) { + u8 i2c_buf[I2C_BUF_SIZE] = { 0 }; int ret; ret = spl_early_init(); @@ -54,10 +122,33 @@ void board_init_f(ulong dummy) clk_early_init(); serial_early_init(); + preloader_console_init(); + + i2c_early_init(); + ret = read_product_name(i2c_buf, I2C_BUF_SIZE); + if (ret) + log_info("Fail to detect board:%d\n", ret); + else + log_info("Get board name:%s\n", (char *)i2c_buf); } u32 spl_boot_device(void) { - return BOOT_DEVICE_NONE; + return BOOT_DEVICE_NOR; +} + +void pmic_init(void) +{ + struct udevice *pmic_dev = NULL; + int ret; + + ret = uclass_get_device(UCLASS_PMIC, 0, &pmic_dev); + if (ret) + panic("Fail to detect PMIC:%d\n", ret); +} + +void spl_board_init(void) +{ + pmic_init(); } diff --git a/board/spacemit/k1/tlv_codes.h b/board/spacemit/k1/tlv_codes.h new file mode 100644 index 00000000000..e40fbdcee6d --- /dev/null +++ b/board/spacemit/k1/tlv_codes.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#ifndef __TLV_CODES_H +#define __TLV_CODES_H + +#define TLV_CODE_SDK_VERSION 0x40 +#define TLV_CODE_DDR_CSNUM 0x41 +#define TLV_CODE_DDR_TYPE 0x42 +#define TLV_CODE_DDR_DATARATE 0x43 +#define TLV_CODE_DDR_TX_ODT 0x44 + +#define TLV_CODE_WIFI_MAC_ADDR 0x60 +#define TLV_CODE_BLUETOOTH_ADDR 0x61 + +#define TLV_CODE_PMIC_TYPE 0x80 +#define TLV_CODE_EEPROM_I2C_INDEX 0x81 +#define TLV_CODE_EEPROM_PIN_GROUP 0x82 + +#endif /* __TLV_CODES_H */ diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index 23019266103..ce0314686ab 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -31,8 +31,11 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SPL_MAX_SIZE=0x33000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_I2C=y CONFIG_SPL_DM_RESET=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_TLV_EEPROM=y +CONFIG_SPL_CMD_TLV_EEPROM=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_SPL_REGMAP=y @@ -41,6 +44,11 @@ CONFIG_SPL_CLK=y CONFIG_SPL_CLK_CCF=y CONFIG_CLK_SPACEMIT=y CONFIG_CLK_SPACEMIT_K1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_SPACEMIT_K1=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SPL_I2C_EEPROM=y CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_UART_NS16550=y From patchwork Tue May 19 10:26:28 2026 Content-Type: text/plain; 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Mon, 18 May 2026 15:31:48 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:31:47 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:28 -0400 Subject: [PATCH v4 10/14] spacemit: k1: Add DDR firmware support to SPL MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-10-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Include DDR initialization firmware in the SPL image. The firmware path can be specified via the DDR_FW_FILE environment variable. If the firmware is not found, an empty placeholder file is created to allow the build to proceed without DDR initialization support. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - DT: binman u-boot-spl-ddr moves into k1-bananapi-f3-u-boot.dtsi. - fence.i instead of flush_dcache_range() after firmware copy. - Log fix: "DDR isn't invalid" -> "DDR is not ready". - Makefile: FORCE, cmp -s, clean-files. --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 23 ++++++ board/spacemit/k1/Makefile | 21 +++++ board/spacemit/k1/spl.c | 127 ++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index ac56bf512ad..1a6240a9725 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -73,3 +73,26 @@ bootph-pre-ram; }; }; + +&binman { + u-boot-spl-ddr { + type = "section"; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + ddr-fw { + type = "blob"; + filename = "ddr_fw.bin"; + align = <64>; + }; + + u-boot-any { + type = "section"; + size = <0>; + offset = <0>; + }; + }; +}; diff --git a/board/spacemit/k1/Makefile b/board/spacemit/k1/Makefile index f9cbf4b0e06..a57af2e1f08 100644 --- a/board/spacemit/k1/Makefile +++ b/board/spacemit/k1/Makefile @@ -5,3 +5,24 @@ obj-y := board.o obj-$(CONFIG_SPL_BUILD) += spl.o + +DDR_FW_SRC ?= $(DDR_FW_FILE) +FW_TARGET = $(objtree)/ddr_fw.bin + +$(obj)/spl.o: $(FW_TARGET) + +$(FW_TARGET): FORCE + @if [ -n "$(DDR_FW_SRC)" ] && [ -f "$(DDR_FW_SRC)" ]; then \ + if ! cmp -s "$(DDR_FW_SRC)" $@ 2>/dev/null; then \ + echo " Copying DDR firmware from: $(DDR_FW_SRC)"; \ + cp "$(DDR_FW_SRC)" $@; \ + fi; \ + elif [ -s $@ ]; then \ + : ; \ + else \ + echo " Note: No DDR firmware found, creating empty placeholder"; \ + echo " (Set DDR_FW_FILE to specify firmware location)"; \ + touch $@; \ + fi + +clean-files += $(FW_TARGET) diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c index e862548f980..bab4fac3a13 100644 --- a/board/spacemit/k1/spl.c +++ b/board/spacemit/k1/spl.c @@ -4,8 +4,11 @@ */ #include +#include +#include #include #include +#include #include #include #include @@ -14,6 +17,7 @@ #include #include #include +#include "tlv_codes.h" #define MUX_MODE4 4 #define EDGE_NONE BIT(6) @@ -26,6 +30,29 @@ #define MFP_GPIO_84 0xd401e154 #define MFP_GPIO_85 0xd401e158 +#define DDR_FIRMWARE_BASE 0xc082d000 + +#define DDR_DEFAULT_CS_NUM 2 +#define DDR_DEFAULT_TYPE "LPDDR4X" +#define DDR_DEFAULT_TX_ODT 80 +#define DDR_DEFAULT_DATA_RATE 2400 + +#define MAGIC_NUM 0xaa55aa55 + +typedef void (*puts_func_t)(const char *s); +typedef int (*ddr_init_func_t)(u64 ddr_base, u32 cs_num, u32 data_rate, + puts_func_t puts); + +struct ddr_cfg { + u32 data_rate; + u32 cs_num; + u32 tx_odt; + u8 type[I2C_BUF_SIZE]; +}; + +binman_sym_declare(ulong, ddr_fw, image_pos); +binman_sym_declare(ulong, ddr_fw, size); + static void i2c_early_init(void) { struct udevice *bus; @@ -109,6 +136,105 @@ void serial_early_init(void) panic("Serial uclass init failed: %d\n", ret); } +/* Set default value for DDR chips */ +static void ddr_cfg_init(struct ddr_cfg *cfg) +{ + memset(cfg, 0, sizeof(struct ddr_cfg)); + cfg->data_rate = DDR_DEFAULT_DATA_RATE; + cfg->cs_num = DDR_DEFAULT_CS_NUM; + cfg->tx_odt = DDR_DEFAULT_TX_ODT; + strcpy(cfg->type, DDR_DEFAULT_TYPE); +} + +int read_ddr_info(struct ddr_cfg *cfg) +{ + u8 eeprom_data[TLV_TOTAL_LEN_MAX], *p; + struct tlvinfo_header *tlv_hdr; + struct tlvinfo_tlv *tlv_entry; + u32 size, entry_size; + int ret, i; + bool found = false; + + if (!cfg) + return -EINVAL; + ddr_cfg_init(cfg); + ret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr, + &tlv_entry, i); + if (ret) + return ret; + p = (u8 *)tlv_entry; + for (i = 0; i < tlv_hdr->totallen; ) { + switch (tlv_entry->type) { + case TLV_CODE_DDR_CSNUM: + memcpy(&cfg->cs_num, &tlv_entry->value[0], 1); + found = true; + break; + case TLV_CODE_DDR_TYPE: + size = min((u32)tlv_entry->length, (u32)I2C_BUF_SIZE); + memcpy(&cfg->type[0], &tlv_entry->value[0], size); + found = true; + break; + case TLV_CODE_DDR_DATARATE: + memcpy(&cfg->data_rate, &tlv_entry->value[0], 2); + found = true; + break; + case TLV_CODE_DDR_TX_ODT: + memcpy(&cfg->tx_odt, &tlv_entry->value[0], 1); + found = true; + break; + case TLV_CODE_CRC_32: + if (!found) + return -ENOENT; + return 0; + } + entry_size = tlv_entry->length + sizeof(struct tlvinfo_tlv); + i += entry_size; + p += entry_size; + tlv_entry = (struct tlvinfo_tlv *)p; + } + if (!found) + return -ENOENT; + return 0; +} + +void ddr_early_init(void) +{ + void __iomem *src, *dst; + ulong pos, size; + struct ddr_cfg cfg; + ddr_init_func_t ddr_init; + + pos = binman_sym(ulong, ddr_fw, image_pos); + size = binman_sym(ulong, ddr_fw, size); + src = (void __iomem *)pos; + dst = (void __iomem *)(DDR_FIRMWARE_BASE); + log_info("DDR firmware: [0x%lx]:0x%x, size:0x%lx\n", pos, readl(src), size); + memcpy((u8 *)dst, (u8 *)src, size); + size = round_up(size, 64); + /* + * Ensure the just-written DDR firmware bytes are observable in the + * instruction stream. RISC-V's fence.i alone is sufficient for the + * single-hart SPL case; skip flush_dcache_range as cbo.flush may + * trap on our current privilege state. + */ + asm volatile ("fence.i" ::: "memory"); + + read_ddr_info(&cfg); + ddr_init = (ddr_init_func_t)DDR_FIRMWARE_BASE; +#ifdef DEBUG + ddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, puts); +#else + ddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, NULL); +#endif + writel(MAGIC_NUM, (void __iomem *)0x00000000); + flush_dcache_range(0, 64); + invalidate_dcache_range(0, 64); + if (readl((void __iomem *)0x00000000) == MAGIC_NUM) + log_info("DDR is ready\n"); + else + log_info("DDR is not ready\n"); +} + void board_init_f(ulong dummy) { u8 i2c_buf[I2C_BUF_SIZE] = { 0 }; @@ -131,6 +257,7 @@ void board_init_f(ulong dummy) log_info("Fail to detect board:%d\n", ret); else log_info("Get board name:%s\n", (char *)i2c_buf); + ddr_early_init(); } u32 spl_boot_device(void) From patchwork Tue May 19 10:26:29 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 2240089 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 18 May 2026 15:32:11 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:32:10 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:29 -0400 Subject: [PATCH v4 11/14] power: pmic: add support for Spacemit P1 PMIC MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-11-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Spacemit's PMIC is used by Spacemit K1 SoC. It contains voltage regulators, GPIOs and Watchdog. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu Acked-by: Peng Fan --- v4: - No change. --- drivers/power/pmic/Kconfig | 8 ++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_spacemit_p1.c | 94 ++++++++++++++++++++ include/power/spacemit_p1.h | 163 ++++++++++++++++++++++++++++++++++ 4 files changed, 266 insertions(+) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 5bc14842e66..aaae3eacc14 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -434,6 +434,14 @@ config PMIC_RAA215300 allows register access and will bind the sysreset driver (CONFIG_SYSRESET_RAA215300) if it is enabled. +config PMIC_SPACEMIT_P1 + bool "Enable driver for Spacemit P1 power management chip" + depends on DM_PMIC + help + The P1 PMIC integrates multiple functions including + voltage regulators, a watchdog timer, GPIO interfaces, and a + real-time clock. + config DM_PMIC_MTK_PWRAP bool "Enable driver for MediaTek PMIC Wrapper Support" help diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 2cda5a892fd..0ac92084221 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_$(PHASE_)DM_PMIC_TPS80031) += tps80031.o obj-$(CONFIG_$(PHASE_)PMIC_PALMAS) += palmas.o obj-$(CONFIG_$(PHASE_)PMIC_LP873X) += lp873x.o obj-$(CONFIG_$(PHASE_)PMIC_LP87565) += lp87565.o +obj-$(CONFIG_PMIC_SPACEMIT_P1) += pmic_spacemit_p1.o obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o obj-$(CONFIG_PMIC_TPS65219) += tps65219.o diff --git a/drivers/power/pmic/pmic_spacemit_p1.c b/drivers/power/pmic/pmic_spacemit_p1.c new file mode 100644 index 00000000000..46c5926874c --- /dev/null +++ b/drivers/power/pmic/pmic_spacemit_p1.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#include +#include +#include + +static int pmic_p1_reg_count(struct udevice *dev) +{ + return P1_MAX_REGS; +} + +static int pmic_p1_write(struct udevice *dev, uint reg, const u8 *buffer, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buffer, len); + if (ret) + pr_err("%s write error on register %02x\n", dev->name, reg); + + return ret; +} + +static int pmic_p1_read(struct udevice *dev, uint reg, u8 *buffer, + int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buffer, len); + if (ret) + pr_err("%s read error on register %02x\n", dev->name, reg); + + return ret; +} + +static const struct pmic_child_info p1_children_info[] = { + { .prefix = "buck", .driver = P1_BUCK_DRIVER }, + { .prefix = "aldo", .driver = P1_ALDO_DRIVER }, + { .prefix = "dldo", .driver = P1_DLDO_DRIVER }, + { }, +}; + +static int pmic_p1_bind(struct udevice *dev) +{ + const struct pmic_child_info *p1_children_info = + (struct pmic_child_info *)dev_get_driver_data(dev); + ofnode regulators_node; + int children; + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s regulators subnode not found\n", dev->name); + return -EINVAL; + } + + children = pmic_bind_children(dev, regulators_node, + p1_children_info); + if (!children) + debug("%s has no children (regulators)\n", dev->name); + + return 0; +} + +static int pmic_p1_probe(struct udevice *dev) +{ + return 0; +} + +static struct dm_pmic_ops pmic_p1_ops = { + .reg_count = pmic_p1_reg_count, + .read = pmic_p1_read, + .write = pmic_p1_write, +}; + +static const struct udevice_id pmic_p1_match[] = { + { + .compatible = "spacemit,p1", + .data = (ulong)&p1_children_info, + }, { + /* sentinel */ + } +}; + +U_BOOT_DRIVER(pmic_p1) = { + .name = "pmic_p1", + .id = UCLASS_PMIC, + .of_match = pmic_p1_match, + .bind = pmic_p1_bind, + .probe = pmic_p1_probe, + .ops = &pmic_p1_ops, +}; diff --git a/include/power/spacemit_p1.h b/include/power/spacemit_p1.h new file mode 100644 index 00000000000..ef5a45e8cec --- /dev/null +++ b/include/power/spacemit_p1.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#ifndef __SPACEMIT_P1_H_ +#define __SPACEMIT_P1_H_ + +#define P1_MAX_REGS 0xA8 + +#define P1_REG_ID 0x0 + +#define P1_ID 0x2 + +#define P1_REG_BUCK1_CTRL 0x47 +#define P1_REG_BUCK2_CTRL 0x4a +#define P1_REG_BUCK3_CTRL 0x4d +#define P1_REG_BUCK4_CTRL 0x50 +#define P1_REG_BUCK5_CTRL 0x53 +#define P1_REG_BUCK6_CTRL 0x56 + +#define P1_REG_BUCK1_VSEL 0x48 +#define P1_REG_BUCK2_VSEL 0x4b +#define P1_REG_BUCK3_VSEL 0x4e +#define P1_REG_BUCK4_VSEL 0x51 +#define P1_REG_BUCK5_VSEL 0x54 +#define P1_REG_BUCK6_VSEL 0x57 + +#define P1_REG_BUCK1_SVSEL 0x49 +#define P1_REG_BUCK2_SVSEL 0x4c +#define P1_REG_BUCK3_SVSEL 0x4f +#define P1_REG_BUCK4_SVSEL 0x52 +#define P1_REG_BUCK5_SVSEL 0x55 +#define P1_REG_BUCK6_SVSEL 0x58 + +#define P1_BUCK_CTRL(x) (0x47 + ((x) - 1) * 3) +#define P1_BUCK_VSEL(x) (0x48 + ((x) - 1) * 3) +#define P1_BUCK_SVSEL(x) (0x49 + ((x) - 1) * 3) + +#define BUCK_VSEL_MASK 0xff +#define BUCK_EN_MASK 0x1 +#define BUCK_SVSEL_MASK 0xff + +#define P1_REG_ALDO1_CTRL 0x5b +#define P1_REG_ALDO2_CTRL 0x5e +#define P1_REG_ALDO3_CTRL 0x61 +#define P1_REG_ALDO4_CTRL 0x64 + +#define P1_REG_ALDO1_VOLT 0x5c +#define P1_REG_ALDO2_VOLT 0x5f +#define P1_REG_ALDO3_VOLT 0x62 +#define P1_REG_ALDO4_VOLT 0x65 + +#define P1_REG_ALDO1_SVOLT 0x5d +#define P1_REG_ALDO2_SVOLT 0x60 +#define P1_REG_ALDO3_SVOLT 0x63 +#define P1_REG_ALDO4_SVOLT 0x66 + +#define P1_ALDO_CTRL(x) (0x5b + ((x) - 1) * 3) +#define P1_ALDO_VOLT(x) (0x5c + ((x) - 1) * 3) +#define P1_ALDO_SVOLT(x) (0x5d + ((x) - 1) * 3) + +#define ALDO_SVSEL_MASK 0x7f +#define ALDO_EN_MASK 0x1 +#define ALDO_VSEL_MASK 0x7f + +#define P1_REG_DLDO1_CTRL 0x67 +#define P1_REG_DLDO2_CTRL 0x6a +#define P1_REG_DLDO3_CTRL 0x6d +#define P1_REG_DLDO4_CTRL 0x70 +#define P1_REG_DLDO5_CTRL 0x73 +#define P1_REG_DLDO6_CTRL 0x76 +#define P1_REG_DLDO7_CTRL 0x79 + +#define P1_REG_DLDO1_VOLT 0x68 +#define P1_REG_DLDO2_VOLT 0x6b +#define P1_REG_DLDO3_VOLT 0x6e +#define P1_REG_DLDO4_VOLT 0x71 +#define P1_REG_DLDO5_VOLT 0x74 +#define P1_REG_DLDO6_VOLT 0x77 +#define P1_REG_DLDO7_VOLT 0x7a + +#define P1_REG_DLDO1_SVOLT 0x69 +#define P1_REG_DLDO2_SVOLT 0x6c +#define P1_REG_DLDO3_SVOLT 0x6f +#define P1_REG_DLDO4_SVOLT 0x72 +#define P1_REG_DLDO5_SVOLT 0x75 +#define P1_REG_DLDO6_SVOLT 0x78 +#define P1_REG_DLDO7_SVOLT 0x7b + +#define P1_DLDO_CTRL(x) (0x67 + ((x) - 1) * 3) +#define P1_DLDO_VOLT(x) (0x68 + ((x) - 1) * 3) +#define P1_DLDO_SVOLT(x) (0x69 + ((x) - 1) * 3) + +#define DLDO_SVSEL_MASK 0x7f +#define DLDO_EN_MASK 0x1 +#define DLDO_VSEL_MASK 0x7f + +#define P1_REG_SWITCH_CTRL 0x59 +#define P1_SWTICH_EN_MASK 0x1 + +#define P1_REG_SWITCH_PWRKEY_EVENT_CTRL 0x97 +#define P1_SWITCH_PWRKEY_EVENT_EN_MSK 0xf + +#define P1_REG_SWITCH_PWRKEY_INIT_CTRL 0x9e +#define P1_SWITCH_PWRKEY_INT_EN_MSK 0xf + +/* Watchdog Timer Registers */ +#define P1_WDT_CTRL 0x44 +#define P1_PWR_CTRL0 0x7C +#define P1_PWR_CTRL2 0x7E +#define P1_PWR_CTRL2_MSK 0xff + +/* Watchdog Timer Control Bits */ +#define P1_WDT_CLEAR_STATUS 0x1 +#define P1_SW_RST 0x2 +#define P1_WDT_RESET_ENABLE 0x80 +#define P1_WDT_ENABLE 0x8 +#define P1_WDT_TIMEOUT_1S 0x0 +#define P1_WDT_TIMEOUT_4S 0x1 +#define P1_WDT_TIMEOUT_8S 0x2 +#define P1_WDT_TIMEOUT_16S 0x3 + +#define P1_RTC_TICK_CTRL 0x1d +#define P1_RTC_TICK_CTRL_MSK 0x7f + +#define P1_RTC_TICK_EVENT 0x92 +#define P1_RTC_TICK_EVENT_MSK 0x3f + +#define P1_RTC_TICK_IRQ 0x99 +#define P1_RTC_TICK_IRQ_MSK 0x3f + +#define P1_REG_ALIVE 0xab +#define P1_ALIVE_MSK 0x7 +#define SYS_REBOOT_FLAG_BIT 0x2 + +/* SWITCH ID */ +enum { + P1_ID_SWITCH1, + P1_ID_SWITCH1_PWRKEY_EVENT, + P1_ID_SWITCH1_PWRKEY_INT, + P1_ID_SWITCH_RTC_TICK_CTRL, + P1_ID_SWITCH_RTC_TICK_EVENT, + P1_ID_SWITCH_RTC_TCK_IRQ, + P1_ID_SWITCH_POWER_DOWN, + P1_ID_SWITCH_CHARGING_FLAG, +}; + +/* POWERKEY events */ +enum { + PWRKEY_RISING_EVENT = 1, + PWRKEY_FAILING_EVENT = 2, + PWRKEY_SHORT_PRESS_EVENT = 4, + PWRKEY_LONG_PRESS_EVENT = 8, +}; + +#define P1_BUCK_DRIVER "p1_buck" +#define P1_ALDO_DRIVER "p1_aldo" +#define P1_DLDO_DRIVER "p1_dldo" +#define P1_SWITCH_DRIVER "p1_switch" +#define P1_WDT_DRIVER "p1_wdt" + +#endif /* __SPACEMIT_P1_H_ */ From patchwork Tue May 19 10:26:30 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 2240090 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=riscstar-com.20251104.gappssmtp.com header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256 header.s=20251104 header.b=xpKoBv7u; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Mon, 18 May 2026 15:32:31 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.32.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:32:31 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:30 -0400 Subject: [PATCH v4 12/14] power: regulator: add support for Spacemit P1 SoC MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-12-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Support voltage regulator for Spacemit P1 SoC. It contains 6 BUCKs and 11 LDOs. Signed-off-by: Raymond Mao Acked-by: Peng Fan Signed-off-by: Guodong Xu --- v4: - Bounds-check + 1-based indexing in p1_aldo()/p1_dldo(). --- drivers/power/regulator/Kconfig | 7 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/spacemit_p1_regulator.c | 464 ++++++++++++++++++++++++ 3 files changed, 472 insertions(+) diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index ca5de5b8726..e6083b5d161 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -557,3 +557,10 @@ config DM_REGULATOR_MT6359 MediaTek MT6359 PMIC. This driver supports the control of different power rails of device through regulator interface. + +config DM_REGULATOR_SPACEMIT_P1 + bool "Enable driver for Spacemit P1 PMIC regulators" + depends on DM_REGULATOR && PMIC_SPACEMIT_P1 + help + Enable implementation of driver-model regulator uclass features + for regulator P1. The driver supports BUCKs, LDOs and SWITCHes. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 36a84e7cd71..308a79f6816 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_$(PHASE_)REGULATOR_RK8XX) += rk8xx.o obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o +obj-$(CONFIG_DM_REGULATOR_SPACEMIT_P1) += spacemit_p1_regulator.o obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_PALMAS) += palmas_regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_PBIAS) += pbias_regulator.o diff --git a/drivers/power/regulator/spacemit_p1_regulator.c b/drivers/power/regulator/spacemit_p1_regulator.c new file mode 100644 index 00000000000..7b5eb710edf --- /dev/null +++ b/drivers/power/regulator/spacemit_p1_regulator.c @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct p1_reg_info { + uint min_uv; + uint step_uv; + u8 vsel_reg; + u8 vsel_sleep_reg; + u8 config_reg; + u8 vsel_mask; + u8 min_sel; + u8 max_sel; +}; + +static const struct p1_reg_info p1_bucks[] = { + /* BUCK 1 */ + { 500000, 5000, P1_BUCK_VSEL(1), P1_BUCK_SVSEL(1), P1_BUCK_CTRL(1), + BUCK_VSEL_MASK, 0x00, 0xaa }, + { 1375000, 25000, P1_BUCK_VSEL(1), P1_BUCK_SVSEL(1), P1_BUCK_CTRL(1), + BUCK_VSEL_MASK, 0xab, 0xfe }, + /* BUCK 2 */ + { 500000, 5000, P1_BUCK_VSEL(2), P1_BUCK_SVSEL(2), P1_BUCK_CTRL(2), + BUCK_VSEL_MASK, 0x00, 0xaa }, + { 1375000, 25000, P1_BUCK_VSEL(2), P1_BUCK_SVSEL(2), P1_BUCK_CTRL(2), + BUCK_VSEL_MASK, 0xab, 0xfe }, + /* BUCK 3 */ + { 500000, 5000, P1_BUCK_VSEL(3), P1_BUCK_SVSEL(3), P1_BUCK_CTRL(3), + BUCK_VSEL_MASK, 0x00, 0xaa }, + { 1375000, 25000, P1_BUCK_VSEL(3), P1_BUCK_SVSEL(3), P1_BUCK_CTRL(3), + BUCK_VSEL_MASK, 0xab, 0xfe }, + /* BUCK 4 */ + { 500000, 5000, P1_BUCK_VSEL(4), P1_BUCK_SVSEL(4), P1_BUCK_CTRL(4), + BUCK_VSEL_MASK, 0x00, 0xaa }, + { 1375000, 25000, P1_BUCK_VSEL(4), P1_BUCK_SVSEL(4), P1_BUCK_CTRL(4), + BUCK_VSEL_MASK, 0xab, 0xfe }, + /* BUCK 5 */ + { 500000, 5000, P1_BUCK_VSEL(5), P1_BUCK_SVSEL(5), P1_BUCK_CTRL(5), + BUCK_VSEL_MASK, 0x00, 0xaa }, + { 1375000, 25000, P1_BUCK_VSEL(5), P1_BUCK_SVSEL(5), P1_BUCK_CTRL(5), + BUCK_VSEL_MASK, 0xab, 0xfe }, + /* BUCK 6 */ + { 500000, 5000, P1_BUCK_VSEL(6), P1_BUCK_SVSEL(6), P1_BUCK_CTRL(6), + BUCK_VSEL_MASK, 0x00, 0xaa }, + { 1375000, 25000, P1_BUCK_VSEL(6), P1_BUCK_SVSEL(6), P1_BUCK_CTRL(6), + BUCK_VSEL_MASK, 0xab, 0xfe }, +}; + +static const struct p1_reg_info p1_aldos[] = { + /* ALDO 1 */ + { 500000, 25000, P1_ALDO_VOLT(1), P1_ALDO_SVOLT(1), P1_ALDO_CTRL(1), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* ALDO 2 */ + { 500000, 25000, P1_ALDO_VOLT(2), P1_ALDO_SVOLT(2), P1_ALDO_CTRL(2), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* ALDO 3 */ + { 500000, 25000, P1_ALDO_VOLT(3), P1_ALDO_SVOLT(3), P1_ALDO_CTRL(3), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* ALDO 4 */ + { 500000, 25000, P1_ALDO_VOLT(4), P1_ALDO_SVOLT(4), P1_ALDO_CTRL(4), + ALDO_VSEL_MASK, 0x0b, 0x7f }, +}; + +static const struct p1_reg_info p1_dldos[] = { + /* DLDO 1 */ + { 500000, 25000, P1_DLDO_VOLT(1), P1_DLDO_SVOLT(1), P1_DLDO_CTRL(1), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* DLDO 2 */ + { 500000, 25000, P1_DLDO_VOLT(2), P1_DLDO_SVOLT(2), P1_DLDO_CTRL(2), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* DLDO 3 */ + { 500000, 25000, P1_DLDO_VOLT(3), P1_DLDO_SVOLT(3), P1_DLDO_CTRL(3), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* DLDO 4 */ + { 500000, 25000, P1_DLDO_VOLT(4), P1_DLDO_SVOLT(4), P1_DLDO_CTRL(4), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* DLDO 5 */ + { 500000, 25000, P1_DLDO_VOLT(5), P1_DLDO_SVOLT(5), P1_DLDO_CTRL(5), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* DLDO 6 */ + { 500000, 25000, P1_DLDO_VOLT(6), P1_DLDO_SVOLT(6), P1_DLDO_CTRL(6), + ALDO_VSEL_MASK, 0x0b, 0x7f }, + /* DLDO 7 */ + { 500000, 25000, P1_DLDO_VOLT(7), P1_DLDO_SVOLT(7), P1_DLDO_CTRL(7), + ALDO_VSEL_MASK, 0x0b, 0x7f }, +}; + +static const struct p1_reg_info *get_buck_reg(struct udevice *pmic, + int idx, int uvolt) +{ + if (idx < 0) + return NULL; + if (uvolt < 1375000) + return &p1_bucks[(idx - 1) * 2 + 0]; + return &p1_bucks[(idx - 1) * 2 + 1]; +} + +static const struct p1_reg_info *get_aldo_reg(struct udevice *pmic, + int idx, int uvolt) +{ + if (idx < 1 || idx > ARRAY_SIZE(p1_aldos)) + return NULL; + return &p1_aldos[idx - 1]; +} + +static const struct p1_reg_info *get_dldo_reg(struct udevice *pmic, + int idx, int uvolt) +{ + if (idx < 1 || idx > ARRAY_SIZE(p1_dldos)) + return NULL; + return &p1_dldos[idx - 1]; +} + +static int buck_get_value(struct udevice *dev) +{ + const struct dm_pmic_ops *ops = device_get_ops(dev->parent); + const struct p1_reg_info *info; + uint val; + int ret; + + if (!ops || !ops->read) + return -ENOSYS; + + info = get_buck_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + ret = pmic_reg_read(dev->parent, info->vsel_reg); + if (ret < 0) + return ret; + val = ret & info->vsel_mask; + while (val > info->max_sel) + info++; + + return info->min_uv + (val - info->min_sel) * info->step_uv; +} + +static int buck_set_value(struct udevice *dev, int uvolt) +{ + const struct dm_pmic_ops *ops = device_get_ops(dev->parent); + const struct p1_reg_info *info; + uint val; + int ret; + + if (!ops || !ops->write) + return -ENOSYS; + + info = get_buck_reg(dev->parent, dev->driver_data, uvolt); + if (!info) + return -ENOENT; + val = (uvolt - info->min_uv); + val = val / info->step_uv; + val += info->min_sel; + ret = pmic_reg_write(dev->parent, info->vsel_reg, val); + if (ret < 0) + return ret; + return 0; +} + +static int buck_get_enable(struct udevice *dev) +{ + const struct p1_reg_info *info; + int ret; + + info = get_buck_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->config_reg); + if (ret < 0) + return ret; + return ret & BUCK_EN_MASK; +} + +static int buck_set_enable(struct udevice *dev, bool enable) +{ + const struct p1_reg_info *info; + uint val; + int ret; + + info = get_buck_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->config_reg); + if (ret < 0) + return ret; + val = (unsigned int)ret; + val &= BUCK_EN_MASK; + + if (enable == val) + return 0; + + val = enable; + ret = pmic_clrsetbits(dev->parent, info->config_reg, BUCK_EN_MASK, val); + if (ret < 0) + return ret; + + return 0; +} + +static const struct dm_regulator_ops p1_buck_ops = { + .get_value = buck_get_value, + .set_value = buck_set_value, + .get_enable = buck_get_enable, + .set_enable = buck_set_enable, +}; + +static int p1_buck_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + + uc_pdata->type = REGULATOR_TYPE_BUCK; + uc_pdata->mode_count = 0; + + return 0; +} + +U_BOOT_DRIVER(p1_buck) = { + .name = P1_BUCK_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &p1_buck_ops, + .probe = p1_buck_probe, +}; + +static int aldo_get_value(struct udevice *dev) +{ + const struct dm_pmic_ops *ops = device_get_ops(dev->parent); + const struct p1_reg_info *info; + uint val; + int ret; + + if (!ops || !ops->read) + return -ENOSYS; + + info = get_aldo_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->vsel_reg); + if (ret < 0) + return ret; + + val = ret & info->vsel_mask; + while (val > info->max_sel) + info++; + + return info->min_uv + (val - info->min_sel) * info->step_uv; +} + +static int aldo_set_value(struct udevice *dev, int uvolt) +{ + const struct dm_pmic_ops *ops = device_get_ops(dev->parent); + const struct p1_reg_info *info; + uint val; + int ret; + + if (!ops || !ops->write) + return -ENOSYS; + + info = get_aldo_reg(dev->parent, dev->driver_data, uvolt); + if (!info) + return -ENOENT; + val = (uvolt - info->min_uv); + val = val / info->step_uv; + val += info->min_sel; + ret = pmic_reg_write(dev->parent, info->vsel_reg, val); + if (ret < 0) + return ret; + return 0; +} + +static int aldo_get_enable(struct udevice *dev) +{ + const struct p1_reg_info *info; + int ret; + + info = get_aldo_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->config_reg); + if (ret < 0) + return ret; + return ret & ALDO_EN_MASK; +} + +static int aldo_set_enable(struct udevice *dev, bool enable) +{ + const struct p1_reg_info *info; + uint val; + int ret; + + info = get_aldo_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->config_reg); + if (ret < 0) + return ret; + val = (unsigned int)ret; + val &= ALDO_EN_MASK; + + if (enable == val) + return 0; + + val = enable; + ret = pmic_clrsetbits(dev->parent, info->config_reg, ALDO_EN_MASK, val); + if (ret < 0) + return ret; + + return 0; +} + +static const struct dm_regulator_ops p1_aldo_ops = { + .get_value = aldo_get_value, + .set_value = aldo_set_value, + .get_enable = aldo_get_enable, + .set_enable = aldo_set_enable, +}; + +static int p1_aldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->mode_count = 0; + + return 0; +} + +U_BOOT_DRIVER(p1_aldo) = { + .name = P1_ALDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &p1_aldo_ops, + .probe = p1_aldo_probe, +}; + +static int dldo_get_value(struct udevice *dev) +{ + const struct dm_pmic_ops *ops = device_get_ops(dev->parent); + const struct p1_reg_info *info; + uint val; + int ret; + + if (!ops || !ops->read) + return -ENOSYS; + + info = get_dldo_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->vsel_reg); + if (ret < 0) + return ret; + + val = ret & info->vsel_mask; + while (val > info->max_sel) + info++; + + return info->min_uv + (val - info->min_sel) * info->step_uv; +} + +static int dldo_set_value(struct udevice *dev, int uvolt) +{ + const struct dm_pmic_ops *ops = device_get_ops(dev->parent); + const struct p1_reg_info *info; + uint val; + int ret; + + if (!ops || !ops->write) + return -ENOSYS; + + info = get_dldo_reg(dev->parent, dev->driver_data, uvolt); + if (!info) + return -ENOENT; + val = (uvolt - info->min_uv); + val = val / info->step_uv; + val += info->min_sel; + ret = pmic_reg_write(dev->parent, info->vsel_reg, val); + if (ret < 0) + return ret; + return 0; +} + +static int dldo_get_enable(struct udevice *dev) +{ + const struct p1_reg_info *info; + int ret; + + info = get_dldo_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->config_reg); + if (ret < 0) + return ret; + return ret & DLDO_EN_MASK; +} + +static int dldo_set_enable(struct udevice *dev, bool enable) +{ + const struct p1_reg_info *info; + uint val; + int ret; + + info = get_dldo_reg(dev->parent, dev->driver_data, 0); + if (!info) + return -ENOENT; + + ret = pmic_reg_read(dev->parent, info->config_reg); + if (ret < 0) + return ret; + val = (unsigned int)ret; + val &= DLDO_EN_MASK; + + if (enable == val) + return 0; + + val = enable; + ret = pmic_clrsetbits(dev->parent, info->config_reg, DLDO_EN_MASK, val); + if (ret < 0) + return ret; + + return 0; +} + +static const struct dm_regulator_ops p1_dldo_ops = { + .get_value = dldo_get_value, + .set_value = dldo_set_value, + .get_enable = dldo_get_enable, + .set_enable = dldo_set_enable, +}; + +static int p1_dldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->mode_count = 0; + + return 0; +} + +U_BOOT_DRIVER(p1_dldo) = { + .name = P1_DLDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &p1_dldo_ops, + .probe = p1_dldo_probe, +}; From patchwork Tue May 19 10:26:31 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 2240091 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Mon, 18 May 2026 15:32:57 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.32.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:32:57 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:31 -0400 Subject: [PATCH v4 13/14] board: k1: enable pmic in spl MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-13-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Raymond Mao Add Spacemit P1 SoC support in SPL. And set the default voltage for BUCKs and LDOs. Also update MAINTAINERS: add Guodong Xu as co-maintainer, list the u-boot-spacemit mailing list, register the new K1 driver files (i2c, PMIC, regulator), and fix a pre-existing '@@' typo in Huan Zhou's email. Fixes: 1cd239f44438 ("riscv: spacemit: bananapi_f3: initial support added") Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu --- v4: - DT: drop forked pmic@41; overlay keeps bootph + regulator-name overrides for regulator_get_by_platname(). - Overlay: explicit `resets = <&syscon_apbc RESET_TWSI8>` on &i2c8. - set_vdd_mmc(): program 1.8 V before enable. - defconfig: SPL_DM_REGULATOR (not SPL_DM_PMIC). - Drop duplicate . - MAINTAINERS: fix Huan Zhou email typo (@@ -> @, Fixes: tag included). --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 32 ++++++++++++ board/spacemit/k1/MAINTAINERS | 7 ++- board/spacemit/k1/spl.c | 84 +++++++++++++++++++++++++++---- configs/spacemit_k1_defconfig | 6 +++ 4 files changed, 117 insertions(+), 12 deletions(-) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index 1a6240a9725..b0224dc7827 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -74,6 +74,38 @@ }; }; +/* + * The kernel pmic@41 nodes use the standard regulator-* properties only; + * U-Boot's regulator framework looks up suppliers by `regulator-name`. + * Carry the U-Boot-specific names (vdd_core / vdd_1v8 / vdd_1v8_mmc) here + * so SPL can program the bucks that DDR training depends on. + */ +&i2c8 { + bootph-pre-ram; + resets = <&syscon_apbc RESET_TWSI8>; + + pmic@41 { + bootph-pre-ram; + + regulators { + buck1 { + regulator-name = "vdd_core"; + bootph-pre-ram; + }; + + buck3 { + regulator-name = "vdd_1v8"; + bootph-pre-ram; + }; + + aldo1 { + regulator-name = "vdd_1v8_mmc"; + bootph-pre-ram; + }; + }; + }; +}; + &binman { u-boot-spl-ddr { type = "section"; diff --git a/board/spacemit/k1/MAINTAINERS b/board/spacemit/k1/MAINTAINERS index b256cbe7978..8976c575dff 100644 --- a/board/spacemit/k1/MAINTAINERS +++ b/board/spacemit/k1/MAINTAINERS @@ -1,6 +1,11 @@ BananaPi F3 -M: Huan Zhou +M: Huan Zhou +M: Guodong Xu +L: u-boot-spacemit@groups.io S: Maintained F: board/spacemit/k1/ F: configs/spacemit_k1_defconfig F: doc/board/spacemit/bananapi-f3.rst +F: drivers/i2c/k1_i2c.c +F: drivers/power/pmic/pmic_spacemit_p1.c +F: drivers/power/regulator/spacemit_p1_regulator.c diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c index bab4fac3a13..2afabc72a3f 100644 --- a/board/spacemit/k1/spl.c +++ b/board/spacemit/k1/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include "tlv_codes.h" @@ -136,6 +137,76 @@ void serial_early_init(void) panic("Serial uclass init failed: %d\n", ret); } +static void set_vdd_core(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_core", &dev); + if (ret) + panic("Fail to detect vdd_core (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_core (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_core (%d)\n", ret); + log_info("vdd_core, value:%d\n", ret); +} + +static void set_vdd_1v8(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_1v8", &dev); + if (ret) + panic("Fail to detect vdd_1v8 (%d)\n", ret); + ret = regulator_set_value(dev, 1800000); + if (ret) + log_warning("Fail to set vdd_1v8 as 1800000 (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_1v8 (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_1v8 (%d)\n", ret); + log_info("vdd_1v8, value:%d\n", ret); +} + +static void set_vdd_mmc(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_1v8_mmc", &dev); + if (ret) + panic("Fail to detect vdd_1v8_mmc (%d)\n", ret); + ret = regulator_set_value(dev, 1800000); + if (ret) + log_warning("Fail to set vdd_1v8_mmc as 1800000 (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_1v8_mmc (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_1v8_mmc (%d)\n", ret); + log_info("vdd_1v8_mmc, value:%d\n", ret); +} + +void pmic_init(void) +{ + struct udevice *pmic_dev; + int ret; + + ret = uclass_get_device(UCLASS_PMIC, 0, &pmic_dev); + if (ret) + panic("Fail to detect PMIC (%d)\n", ret); + set_vdd_core(); + set_vdd_1v8(); + set_vdd_mmc(); +} + /* Set default value for DDR chips */ static void ddr_cfg_init(struct ddr_cfg *cfg) { @@ -257,6 +328,8 @@ void board_init_f(ulong dummy) log_info("Fail to detect board:%d\n", ret); else log_info("Get board name:%s\n", (char *)i2c_buf); + pmic_init(); + ddr_early_init(); } @@ -265,17 +338,6 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NOR; } -void pmic_init(void) -{ - struct udevice *pmic_dev = NULL; - int ret; - - ret = uclass_get_device(UCLASS_PMIC, 0, &pmic_dev); - if (ret) - panic("Fail to detect PMIC:%d\n", ret); -} - void spl_board_init(void) { - pmic_init(); } diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index ce0314686ab..e71c079bef2 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_MAX_SIZE=0x33000 CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_TLV_EEPROM=y CONFIG_SPL_CMD_TLV_EEPROM=y @@ -51,6 +52,11 @@ CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPACEMIT_P1=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_SPACEMIT_P1=y CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y From patchwork Tue May 19 10:26:32 2026 Content-Type: text/plain; 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Mon, 18 May 2026 15:33:32 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::4072]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5ef27sm206379265ad.8.2026.05.18.15.32.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 15:33:32 -0700 (PDT) From: Guodong Xu Date: Tue, 19 May 2026 06:26:32 -0400 Subject: [PATCH v4 14/14] doc: spacemit: add K1 SPL build and test guide MIME-Version: 1.0 Message-Id: <20260519-b4-k1-spl-bring-up-v4-14-3915a2a904c1@riscstar.com> References: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> In-Reply-To: <20260519-b4-k1-spl-bring-up-v4-0-3915a2a904c1@riscstar.com> To: u-boot@lists.denx.de, Kongyang Liu , Yixun Lan Cc: Tom Rini , Lukasz Majewski , Patrice Chotard , Patrick Delaunay , Michal Simek , Quentin Schulz , Yao Zi , Junhui Liu , Peter Korsgaard , Leo Yu-Chi Liang , Raymond Mao , Gabriel Fernandez , Kever Yang , Finley Xiao , Rick Chen , Conor Dooley , u-boot-spacemit@groups.io, Vincent Legoll , Huan Zhou , Jamie Gibbons , Randolph Sheng-Kai Lin , Sam Protsenko , Peng Fan , Heiko Schocher , Casey Connolly , Justin Swartz , Jaehoon Chung , David Lechner , Julien Masson , Macpaul Lin , Henrik Grimler , Kory Maincent , Anshul Dalal , Bo-Chen Chen , Justin Klaassen , Guodong Xu , Heinrich Schuchardt , Guodong Xu , Heinrich Schuchardt X-Mailer: b4 0.15.1 X-Mailman-Approved-At: Tue, 19 May 2026 00:38:07 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The K1 SPL patchset requires DDR firmware integration and FSBL signing steps that are not covered by existing documentation. Add a SoC-level guide so reviewers and developers can build and test on hardware. Signed-off-by: Guodong Xu --- v4: - New in series. Folded from standalone v2 doc thread. --- doc/board/spacemit/index.rst | 1 + doc/board/spacemit/k1-spl.rst | 243 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 244 insertions(+) diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst index e7d3d94e459..a5e35ee12ab 100644 --- a/doc/board/spacemit/index.rst +++ b/doc/board/spacemit/index.rst @@ -6,4 +6,5 @@ SpacemiT :maxdepth: 1 bananapi-f3 + k1-spl diff --git a/doc/board/spacemit/k1-spl.rst b/doc/board/spacemit/k1-spl.rst new file mode 100644 index 00000000000..187eed56e8e --- /dev/null +++ b/doc/board/spacemit/k1-spl.rst @@ -0,0 +1,243 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +SpacemiT K1 SPL Build and Test Guide +===================================== + +This guide explains how to build and test U-Boot SPL on SpacemiT K1 based +boards. It covers building SPL with DDR initialization, generating the signed +FSBL image, and deploying via USB fastboot. + +Tested boards: Banana Pi BPI-F3, MusePi Pro. + +.. note:: + + The procedure described here loads SPL into SRAM via USB fastboot and + does not modify the on-board flash, so a power cycle restores the + board's normal boot path. + + At this stage of the patchset, SPL initializes DDR and then halts with + "SPL: Unsupported Boot Device!" because SPI NOR storage support is not + yet available in U-Boot proper. This document will be updated when + U-Boot stage support is ready. + +Prerequisites +~~~~~~~~~~~~~ + +- A SpacemiT K1 board with USB Type-C and UART access +- USB-to-UART adapter (3.3V TTL) +- ``minicom`` or equivalent serial terminal, configured at 115200 8N1 +- ``fastboot`` tool on the host + +Hardware Setup +~~~~~~~~~~~~~~ + +**1. UART Connection** + +Remove all other cables first, then attach UART. Connect a 3.3V +USB-to-UART cable to the board's UART header (J25 on the BPI-F3):: + + BPI-F3 top view + +--------------------------------------------------+ + | | + | J15: USB-C [====] [FDL] [PWR] [RST] | + | | + | | + | J25 (UART header) | + | [TXD] [RXD] [GND] | + +--------------------------------------------------+ + +After UART is connected, attach the USB Type-C cable to the OTG port +(J15 on BPI-F3) to power on. + +**2. Serial Console** + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Default baudrate: 115200. + +Building U-Boot SPL +~~~~~~~~~~~~~~~~~~~~ + +**1. Obtain the DDR training firmware** + +The DDR training firmware is a proprietary binary provided by SpacemiT. It is +not included in U-Boot and must be downloaded separately from: + +https://github.com/spacemit-com/spacemit-firmware/tree/master/k1/v0.2 + +Download ``ddr_fw.bin`` from that directory. + +This binary is integrated into the SPL image at build time via the binman +framework. When the SPL image is loaded to SRAM (e.g., via USB fastboot), +the SPL executes the DDR firmware from SRAM to perform DDR initialization. + +**2. Obtain OpenSBI fw_dynamic.bin** + +Any pre-built ``fw_dynamic.bin`` is sufficient. Upstream OpenSBI +sources are at https://github.com/riscv-software-src/opensbi if you +need to build one. + +At this stage of the patchset, SPL halts before invoking OpenSBI, +but U-Boot's binman still packages ``fw_dynamic.bin`` into +``u-boot.itb`` and the build fails if it is missing. + +**3. Build SPL** + +.. code-block:: console + + $ export CROSS_COMPILE=riscv64-linux-gnu- + $ export ARCH=riscv + $ export DDR_FW_FILE=$(pwd)/ddr_fw.bin + $ export OPENSBI=/path/to/fw_dynamic.bin + $ make spacemit_k1_defconfig + $ make + +Output: ``u-boot-spl-ddr.bin`` in the build directory. This image contains the +SPL code and the DDR firmware blob packaged together via binman. + +.. note:: + + If ``DDR_FW_FILE`` is not set, the build completes with an empty + placeholder. The resulting SPL will boot but cannot initialize DDR. + +**4. Generate signed FSBL image** + +The K1 BootROM requires a signed first-stage bootloader (FSBL). The signing +tool (``tools/build_binary_file.py``) is in SpacemiT's vendor U-Boot repository: + +.. code-block:: console + + $ git clone -b k1-bl-v2.2.y https://gitee.com/spacemit-buildroot/uboot-2022.10 + +The script uses ``fsbl_ddr.json`` which may not exist by default. If +``fsbl_ddr.json`` does not exist in +``uboot-2022.10/board/spacemit/k1-x/configs/``, +create it by copying ``fsbl.json`` and replacing the reference to +``u-boot-spl.bin`` with ``u-boot-spl-ddr.bin``: + +.. code-block:: console + + $ cd uboot-2022.10/board/spacemit/k1-x/configs + $ cp fsbl.json fsbl_ddr.json + $ sed -i 's/u-boot-spl\.bin/u-boot-spl-ddr.bin/g' fsbl_ddr.json + +Create the ``fsbl.sh`` script below in the ``uboot-2022.10`` directory. +Update the path variables to match your local setup: + +.. code-block:: bash + + #!/bin/sh + MAINLINE_UBOOT_IMG_PATH="{your path}/u-boot" + MAINLINE_SPL_IMG_PATH="{your path}/u-boot/spl" + FSBL_PATH="{your path}/uboot-2022.10/spl_bin" + KEY_TOOL_PATH="{your path}/uboot-2022.10/tools" + CONFIG_PATH="{your path}/uboot-2022.10/board/spacemit/k1-x/configs" + + mkdir -p ${FSBL_PATH} + echo "Clean binaries in ${FSBL_PATH}" + rm -f ${FSBL_PATH}/u-boot-spl-ddr.bin + rm -f ${FSBL_PATH}/u-boot-spl.bin + + if [ ! -d ${MAINLINE_SPL_IMG_PATH} ]; then + MAINLINE_UBOOT_IMG_PATH="{your path}/build" + MAINLINE_SPL_IMG_PATH="{your path}/build/spl" + fi + + # The signing tool reads u-boot-spl-ddr.bin from the path declared in + # fsbl_ddr.json's "source" field, which is resolved relative to the + # JSON file's directory -- i.e. one level up from CONFIG_PATH, not + # FSBL_PATH. Stage the unsigned binary there before signing. + cp ${MAINLINE_UBOOT_IMG_PATH}/u-boot-spl-ddr.bin ${CONFIG_PATH}/../ + python3 ${KEY_TOOL_PATH}/build_binary_file.py \ + -c ${CONFIG_PATH}/fsbl_ddr.json \ + -o ${FSBL_PATH}/FSBL.bin + +Then run: + +.. code-block:: console + + $ chmod +x fsbl.sh + $ ./fsbl.sh + +Output: ``FSBL.bin`` in the ``spl_bin`` directory, ready for deployment. + +Deploying via USB Fastboot +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To enter BootROM fastboot mode: + +1. Power off the board by unplugging its power supply. +2. **Press and hold** the FDL button (called "Boot Key" on some boards; + see the board layout above for the BPI-F3). +3. While holding the button, use a USB cable to connect the OTG port to + your host. This cable is also used by fastboot to upload the firmware. +4. Release the button. + +On the host, ``fastboot devices`` should list the board:: + + dfu-device DFU download + +The serial console shows the BootROM's USB download handler trace, +including a line like:: + + usb2d_initialize : enter + +This indicates the board is ready to accept an image via USB. + +.. tip:: + + If you are worried about insufficient USB power, you can first plug + in the power, then release the button, and then plug in the USB + cable. + +On the host: + +.. code-block:: console + + $ sudo fastboot stage FSBL.bin + $ sudo fastboot continue + +Expected Output +~~~~~~~~~~~~~~~~ + +During successful SPL boot with DDR initialization, the serial console +shows output like:: + + + + U-Boot SPL 2026.04-rc4-00430-g8b84b1ed8ea9 (May 08 2026 - 09:08:27 -0400) + Fail to detect board:-19 + vdd_core, value:900000 + vdd_1v8, value:1800000 + vdd_1v8_mmc, value:1800000 + DDR firmware: [0xc0815840]:0xf0227179, size:0x8d98 + DDR is ready + SPL: Unsupported Boot Device! + SPL: failed to boot from all boot devices + ### ERROR ### Please RESET the board ### + +To walk through the key lines: + +- ``DDR firmware: [...], size:0x8d98`` - DDR firmware loaded successfully +- ``DDR is ready`` - DDR initialization completed +- ``SPL: failed to boot from all boot devices`` - expected at this stage, + confirms that SPL with DDR init is working correctly + +If SPL hangs before printing DDR messages, verify that ``DDR_FW_FILE`` was set +during build and that ``ddr_fw.bin`` is not empty. + +.. tip:: + + To see verbose DDR training output from the DDR firmware (per-phase + training pass/fail logs), add ``#define DEBUG`` at the top of + ``board/spacemit/k1/spl.c`` and rebuild. SPL then passes ``puts`` as + the firmware's log callback; otherwise the callback is ``NULL`` and + the firmware runs silently. + +References +~~~~~~~~~~~ + +- `DDR firmware repository `_ +- `SpacemiT vendor U-Boot (signing tool) `_