From patchwork Fri Apr 17 12:24:07 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Stajic X-Patchwork-Id: 2224452 X-Patchwork-Delegate: leo.liang@sifive.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=In5htYtB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fxvnR58Tzz1yCv for ; Fri, 17 Apr 2026 22:48:27 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5F7CD843E0; Fri, 17 Apr 2026 14:44:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.b="In5htYtB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 92CC2841C2; Fri, 17 Apr 2026 14:24:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from MRWPR03CU001.outbound.protection.outlook.com (mail-francesouthazlp170110003.outbound.protection.outlook.com [IPv6:2a01:111:f403:c207::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 49DAB83EEF for ; Fri, 17 Apr 2026 14:24:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uros.stajic@htecgroup.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dYq+3QkLTPmYZK+LOMrdQpuksz9AIYVG5pG7BUfZXCFg4MkccVyAzcE+Aq07NDmFXLEnGBNn2MNIajVZYvV6JTgxeKsr3T18rGfB7W28yxVEUvAlVOevE94CMIjKWZs0wuHW5SQ2cN00SQZz3eyPwX32fbVLYvnk0dSs0xfb/a80aNPEfEiRZcfntMCHni4djoovteeO8pwQTIQm78jYdz4iykCMu+cZgZ4WRmgM9sINNsDpdYfkuijinlyJL8+4nmVIh1xQX/xrNEyo5pX0iOrmw099rsBlKBAfDf4F0pZ9SFC8EU+XEQPp42ih7eGPve4YB0r5SeIyVqT4OWQqfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Thf2V7dS2/6qcSiBQMkn6sYvlgSQ4D2uspF2fnoWlOI=; b=W3ymoVb6F+7nvDylJ3cul31EUfcMO+/RFSNECvKWStISnY0xrV7pip2UR/usv7nCF48oS5wGc3prc/5LP69t4BM5ATXijK1kLNMaaaJ/vPoF2WnzVThcE9eh2zFUSD5+s8fSY3NhyBVRmIrrkE6O3e4Nq4Axo0dLAeNnxKMqfdBvUwYT57SvksqTBmsA3Ge/iLfDnr4xfZfQRdp5rUvHDbr0jBP23mk2bCR9eYm57ft7NnS1eM6NpmWHkEvMgiM+7+6kFuhivF5eD0SiwIVPOzLDgmdZa+lynjIB31CYjPS9UJ26jLCPwL2Auib2Mngr9gEfrVtcIYQXrRuK93NBYA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=htecgroup.com; dmarc=pass action=none header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Thf2V7dS2/6qcSiBQMkn6sYvlgSQ4D2uspF2fnoWlOI=; b=In5htYtBbvYYZzo7vEUPqh6a8AXkbCq7ulX0ETaXM/wWOGSNwugfSwoH+6kEB8vuiSHaC9wi8qwhsJFO+88MCNmqt3x77JYXoBDf5XPwSZ7ZT5K6bZAzQzCSqMxOYSOdvsJjHP75TDS7AlTHXEnTSK/TlnN5Gcbc36MjBT2wQHPypTYuFmZIPnuDBGPXlMfCdVHuBF1EI9SrLVn44EcTh6AP74V4WB4sCw9vW7T/bL23fVxHXE+PCS115+llefpXCMIZIbOUIy/9hF8l2EUbur64TJ8HimlrsdAVT5O2sKLgyJ6fhCIdYeFXdZO2lTj65qT2kKRVaWt5h4271Ojt1Q== Received: from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20) by AS5PR09MB8577.eurprd09.prod.outlook.com (2603:10a6:20b:753::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr 2026 12:24:07 +0000 Received: from PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81%2]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026 12:24:07 +0000 From: Uros Stajic To: "u-boot@lists.denx.de" CC: Djordje Todorovic , Leo Yu-Chi Liang , Rick Chen , Chao-ying Fu , Uros Stajic Subject: [PATCH v7 1/7] riscv: Add initial support for P8700 SoC Thread-Topic: [PATCH v7 1/7] riscv: Add initial support for P8700 SoC Thread-Index: AQHczmUWo/c40iu3BkuV7ipGrew0GA== Date: Fri, 17 Apr 2026 12:24:07 +0000 Message-ID: <20260417122213.147529-2-uros.stajic@htecgroup.com> References: <20260417122213.147529-1-uros.stajic@htecgroup.com> In-Reply-To: <20260417122213.147529-1-uros.stajic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA3PR09MB8140:EE_|AS5PR09MB8577:EE_ x-ms-office365-filtering-correlation-id: c9413936-abb3-47d1-8511-08de9c7c38f8 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|1800799024|376014|366016|38070700021|18002099003|22082099003|56012099003; x-microsoft-antispam-message-info: 47koFf4klh3w4BF9CGEfqQ3dhTz9E29TE3QUuk/IN5we4KPFrnbrUw9/NU0URyjOsvsfJgn7gPsapwRDePzcmZ7D9d0A1ou2F/z9Ll8XbvUiVgjig8T/c3uUkJ3o2noUboqU+NYzM2fq8YupO33pd6HTvTWHY/ubdSwhsM8JvJWTrF5M4k/Y6ndBWx+lKaB0okPZzxRlY1+VAAyv/JXydRebhNEBzZiDJR/CZxtlORqe4URrHJB7GAJRgXRNtyja0d1f8wru0tDOs69zJNtUgw3aRorPMh+5rj60wEmP/6hE87loTp6zByzjyaVEPBTuugjbxyus/LZ2IsW9o5hkVz5T3Z2nViu3W4nIKUG3zjB8NvHzrF93JfR06tMLN9gFMI49ONEsLYYcrLgC2cp/8XH/tawn+Iz+HD8WwlvSy0CNDYrwvADr2vHzZIbH2RpHIz8khYQcrV7DALOmW9PQQI8NcAmNrMO1GcH2P6uGVIEclA65wku0gpdJHYc+5PR2O0pMiFHPOA2nen3J6Wa3StGgbfVje2+1LYk6gQemBnBonDfoxud9bqOWY9hOt5gQb8WP2o4+qv+qDWbKsVFAHHIcuImlywWAIr2lTUVg/SfQuVV4jByopyl0Gh4F6HU9rncl483q6kMBxHKeW3vCi1C9le0lZFxLL1dmucgZm9dRSRXGNYUvNAADvE7CJYKuFxONNQC4EYRbcuXa9XYpRJ1Gpwv4WQJ2Jt/ZKby3wSrTVvUwpnL4Iks/UWCJNazQZ1SpUZF/65fvPAuTh5lMnhJ6Cm54U8/vdrkaNBJiUy4= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(376014)(366016)(38070700021)(18002099003)(22082099003)(56012099003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?q?as1E/OWcAlTSBPrU4ssvjfb+TKu/?= =?utf-8?q?KQTQwD7vfWfh8ZxykL/7MX12gDgXHoISBS+M9Fmr7Zs9j5p121yExIC3fKqgoejC4?= =?utf-8?q?/mEdsAro6Va4Z9042DsqwHCiAJ1P+gMOwdX2T21vXXr37nx7sfF824NVAMGOcypxQ?= =?utf-8?q?tthkVaY//k3XrOOwV0ipTAm5WECAv1y/yZfSINQsbBeTOodmR7insdM8M7Vv5uS43?= =?utf-8?q?Pg9V5aZzzW+/RL+6QvSh1YUOZCLZ6pGzPW4YT/1hFOc7yU0ILT9XBuclnt0/zrjBF?= =?utf-8?q?+B2aw4gBNKooKLlnpIpRwudKoRC7ITKXD1FqBiO2e35KoNCDNZp6UYThHdauO2HKu?= =?utf-8?q?2OBxdcNJ/L1zL626JwZ4v6/LOqqtRRpy7H9itW5RPq0CXYHVsxLdQLnHzk7D9VoxG?= =?utf-8?q?Q3b/oc8D69P4E3dD1bwX9ISKdP/wVQi3U7CCE8NggkuwlCRk9SIT0YBRM7o8c/H6c?= =?utf-8?q?3jih2NgDjS3OPUmsqX53DA9ssbV9MBnXRzHQ1RzzkLuQpI5Ec6AhJkHSYjrbcRr33?= =?utf-8?q?0VffyOtv/7EdXV0i+vtbuzdtn+L6fWARKEf7c83egNbZfM0bnZv+CVSk501NZ0RaV?= =?utf-8?q?Ka7u8xwtEz0tLv/RF3Lx56uf0ELZRiosVPIkUQqRTL/iAmFBs2bCgyFDAe12ueeby?= =?utf-8?q?lS/qdwaYJXh3U1+zbHUlUtsHXy0qlPMy/L2p5qx3qco7+goxLriGcjmlrWWBLxf7D?= =?utf-8?q?NDWCjVz3VxCygYfUc8W1P/vpvKaPC1AJq9nqW0lfCRprTjJtTZA9+WngNmx7Vrdzg?= =?utf-8?q?rZqhVeSVbjk5ZCBBNXvKfhezRC4hQVIkKLZBiJ4QDuiCfpae9Y2MT2t4B2fOqNTHx?= =?utf-8?q?LsB42C6+Dkiz4qsnOJt5+JG5Yg7Fz6dO7E6aOfiBZQ7SZLkT6cZDqyr/T6+BRdvum?= =?utf-8?q?mGFOiGX0EkIbjsL6MUm+BEIH+PV2/9ohluPEQkYHDp66EiSVHVblnrrNQ5xfNeD2c?= =?utf-8?q?qYelbsNBoBkkfsZV/RoDzVxOeQPLa6jUcYlNEtywSE+Xxydr42h7EX+1KKQR04Iy3?= =?utf-8?q?kg9O6u8egmdY5xFOz7UN9IUK/qCekoJ6vNv2AB+aemE2kYIXBU0yglUjr3Xn4NiMM?= =?utf-8?q?shUkkPSFbTwiJzgIlmGAKwvxuOJ02dS0QFcjLrMx5aNf0atcRJ1y+YeElCUOq68je?= =?utf-8?q?9/g+4xzzn8EZiEdbb1KL2Vd7guslbmwHso5Tc9iysLBoR8sDmG78E1Pfcizk4pex7?= =?utf-8?q?n60NhD6ssJdyhotbSrFO6vIk49o0p+839Ner3RnOtyvg1nACBMx8ucFpvx6geZHep?= =?utf-8?q?Fgy5cVhXoI0AasIf2HQdviXZzuQkltcBffAB31zHBIyYyGNWRTdZd9xIFatvHLys4?= =?utf-8?q?2YY2SPZPFMyyo0WYwPK3rKQ7/PfO0+TPfdFhdq1HjnGNSCdYZ2njJcmQw1Qxk77s8?= =?utf-8?q?1jfohAZgAz5y3beuW4J6Aah0ysXCWdFBnait5WfgD/NxcJTKjwGCqh+7jifJir7++?= =?utf-8?q?zJPnV8z+qkgk3bWDsppUwoYcPIiCItaB1jSJ6Bg/4b2NNi36sPhlLxWOL7xsYB0/y?= =?utf-8?q?ckLw8Ml3HjygJ5cpRySfFFzFwN3aW3Gt3B6drs45DWjukM+T805aymGkw9UQOApca?= =?utf-8?q?MVL9Qs7AHe7W/fon5CWSO4G6u0PKVX1zHJhDX99H3KxPjl4j/LvJmLjNIRdLEHiK3?= =?utf-8?q?sJA93fHvG31DBYJSpCNjymprfStUDEHK9d3zzY7b+F/N6Z7bvhwW0=3D?= Content-ID: <2FD6A6C4433CFA4DA1B1D8318FBD6CBD@eurprd09.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA3PR09MB8140.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c9413936-abb3-47d1-8511-08de9c7c38f8 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2026 12:24:07.8300 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rAuPZdtLNk+OOu8T6mN4WFF7gOFh6Jt/vlmMuuLBJkLDxAgloG/TF4G1QILnYJ4LpTRQYWkAWnEHjg/T3Egh7cXEzZXJsn1yWhKy1zjF05s= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR09MB8577 X-Mailman-Approved-At: Fri, 17 Apr 2026 14:43:59 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Chao-ying Fu Add initial platform support for the P8700-F, a high-performance multi-core RV64GC SoC with optional multi-cluster configuration and hardware multithreading. This patch introduces the initial platform code necessary to support the P8700 CPU in U-Boot. Reviewed-by: Leo Yu-Chi Liang Signed-off-by: Chao-ying Fu Signed-off-by: Uros Stajic --- arch/riscv/Kconfig | 1 + arch/riscv/cpu/p8700/Kconfig | 21 +++++ arch/riscv/cpu/p8700/Makefile | 8 ++ arch/riscv/cpu/p8700/cache.c | 93 +++++++++++++++++++ arch/riscv/cpu/p8700/cpu.c | 105 ++++++++++++++++++++++ arch/riscv/cpu/p8700/dram.c | 37 ++++++++ arch/riscv/cpu/p8700/p8700.c | 12 +++ arch/riscv/include/asm/arch-p8700/p8700.h | 101 +++++++++++++++++++++ 8 files changed, 378 insertions(+) create mode 100644 arch/riscv/cpu/p8700/Kconfig create mode 100644 arch/riscv/cpu/p8700/Makefile create mode 100644 arch/riscv/cpu/p8700/cache.c create mode 100644 arch/riscv/cpu/p8700/cpu.c create mode 100644 arch/riscv/cpu/p8700/dram.c create mode 100644 arch/riscv/cpu/p8700/p8700.c create mode 100644 arch/riscv/include/asm/arch-p8700/p8700.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ad7589123c6..d3380c3ac3f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -136,6 +136,7 @@ source "arch/riscv/cpu/jh7110/Kconfig" source "arch/riscv/cpu/k1/Kconfig" source "arch/riscv/cpu/k230/Kconfig" source "arch/riscv/cpu/th1520/Kconfig" +source "arch/riscv/cpu/p8700/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/p8700/Kconfig b/arch/riscv/cpu/p8700/Kconfig new file mode 100644 index 00000000000..bcd4c63fec7 --- /dev/null +++ b/arch/riscv/cpu/p8700/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021, Chao-ying Fu + +config P8700_RISCV + bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_ACLINT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT + +config RISCV_CM_BASE + hex "RISCV CM Base Address" + default 0x16100000 + help + The physical base address at which to map the Coherence Manager + Global Configuration Registers (GCRs). diff --git a/arch/riscv/cpu/p8700/Makefile b/arch/riscv/cpu/p8700/Makefile new file mode 100644 index 00000000000..04291375a29 --- /dev/null +++ b/arch/riscv/cpu/p8700/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021, Chao-ying Fu + +obj-y += cache.o +obj-y += cpu.o +obj-y += dram.o +obj-y += p8700.o diff --git a/arch/riscv/cpu/p8700/cache.c b/arch/riscv/cpu/p8700/cache.c new file mode 100644 index 00000000000..06e60156394 --- /dev/null +++ b/arch/riscv/cpu/p8700/cache.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Chao-ying Fu + */ + +#include +#include +#include +#include + +#define MCACHE_BASE_INST 0xec0500f3 + +/* NOTE: We force to use a0 in mcache to encode via .word. + * 0xec0500f3 is a manually encoded custom RISC-V MCACHE instruction. + * The bits [19:15] are set to 01010, selecting register x10 (a0) + * as the source operand. + * The bits [24:20] represent the 'op' field, which is currently set to 0. + * Different cache operations are applied by OR-ing (op << 20) dynamically + * to this base value. + * Because of this encoding, the variable 'addr' is forced into register a0, + * so that the MCACHE instruction uses the address in a0 as its operand. + */ +#define cache_loop(start, end, lsize, op) do { \ + const __typeof__(lsize) __lsize = (lsize); \ + const register void *addr asm("a0") = (const void *)((start) & ~(__lsize - 1)); \ + const void *aend = (const void *)(((end) - 1) & ~(__lsize - 1)); \ + for (; addr <= aend; addr += __lsize) \ + asm volatile (".word %0 | %1 # force to use %2" \ + ::"i"(MCACHE_BASE_INST), "i"((op) << 20), "r"(addr)); \ +} while (0) + +static unsigned long lsize; +static unsigned long l1d_total_size; +static unsigned long slsize; + +static void probe_cache_config(void) +{ + lsize = 64; + l1d_total_size = 64 * 1024; + + int l2_config = 0; + + l2_config = readl((void __iomem *)(CM_BASE + GCR_L2_CONFIG_OFFSET)); + int l2_line_size_info = (l2_config >> L2_LINE_SIZE_SHIFT) + & L2_LINE_SIZE_MASK; + slsize = (l2_line_size_info == 0) ? 0 : 1 << (l2_line_size_info + 1); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + if (lsize == 0) + probe_cache_config(); + + /* aend will be miscalculated when size is zero, so we return here */ + if (start >= end) + return; + + cache_loop(start, end, lsize, HIT_WRITEBACK_INV_D); + + /* flush L2 cache */ + if (slsize) + cache_loop(start, end, slsize, HIT_WRITEBACK_INV_SD); + + /* Instruction Hazard Barrier (IHB) — a hint-encoded SLLI (rd=0, rs1=0, imm=1). + * Ensures that all subsequent instruction fetches, including speculative ones, + * observe state changes from prior instructions. + * Required after MCACHE instructions when instruction fetch depends on cache ops. + */ + asm volatile ("slli x0,x0,1 # ihb"); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + if (lsize == 0) + probe_cache_config(); + + /* aend will be miscalculated when size is zero, so we return here */ + if (start >= end) + return; + + /* invalidate L2 cache */ + if (slsize) + cache_loop(start, end, slsize, HIT_INVALIDATE_SD); + + cache_loop(start, end, lsize, HIT_INVALIDATE_D); + + /* Instruction Hazard Barrier (IHB) — a hint-encoded SLLI (rd=0, rs1=0, imm=1). + * Ensures that all subsequent instruction fetches, including speculative ones, + * observe state changes from prior instructions. + * Required after MCACHE instructions when instruction fetch depends on cache ops. + */ + asm volatile ("slli x0,x0,1 # ihb"); +} diff --git a/arch/riscv/cpu/p8700/cpu.c b/arch/riscv/cpu/p8700/cpu.c new file mode 100644 index 00000000000..55b9f939f8e --- /dev/null +++ b/arch/riscv/cpu/p8700/cpu.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Chao-ying Fu + */ + +#include +#include +#include +#include + +static __noreturn void jump_to_addr(ulong addr) +{ + asm volatile ("jr %0" :: "r"(addr) : "memory"); + __builtin_unreachable(); +} + +void harts_early_init(void) +{ + if (!IS_ENABLED(CONFIG_RISCV_MMODE)) + return; + + ulong hartid = csr_read(CSR_MHARTID); + + /* Wait for DDR3 calibration */ + wait_ddr_calib(); + + /* + * Only mhartid[3:0] == 0 performs CM/GCR programming. + * Other harts skip CM/GCR setup and go straight to PMP/PMA setup. + */ + if ((hartid & 0xFULL) == 0) { + ulong cm_base = CM_BASE; + void __iomem *gcr_win = (void __iomem *)0x1fb80000; + ulong cluster = (hartid >> MHARTID_CLUSTER_SHIFT) & + MHARTID_CLUSTER_MASK; + + cm_base += cluster << CM_BASE_CLUSTER_SHIFT; + + if ((hartid & 0xFFFFUL) == 0) + writeq(cm_base, gcr_win + GCR_BASE_OFFSET); + + ulong core = (hartid >> MHARTID_CORE_SHIFT) & MHARTID_CORE_MASK; + + /* Enable coherency for the current core */ + cm_base += core << CM_BASE_CORE_SHIFT; + writeq((u64)GCR_CL_COH_EN_EN, + (void __iomem *)(cm_base + P8700_GCR_C0_COH_EN)); + + /* + * On hart 0, default PCIe DMA mapping should be the non-IOCU + * target. + */ + if (hartid == 0) + setup_pcie_dma_map(); + } + + /* PMP setup */ + csr_write(pmpaddr1, 0x2fffffffUL); + csr_write(pmpaddr2, 0x07ff7fffUL); + csr_write(pmpaddr3, 0x07f3ffffUL); + csr_write(pmpaddr4, 0x1fffffffffffffffUL); + + unsigned long pmpcfg = ((unsigned long)(PMP_NAPOT | PMP_R | PMP_W | + PMP_X) << 32) | + ((unsigned long)(PMP_NAPOT | PMP_R | + PMP_X) << 24) | + ((unsigned long)(PMP_NAPOT | PMP_R | PMP_W | + PMP_X) << 16) | + ((unsigned long)(PMP_NAPOT | PMP_R | PMP_W | + PMP_X) << 8); + + csr_write(pmpcfg0, pmpcfg); + + /* PMA/cache attributes */ + ulong pmacfg0; + + if (hartid == 0) { + /* + * Hart 0: cacheable for pma0, pma1, pma3; uncacheable for + * pma2, pma4. + */ + pmacfg0 = ((unsigned long)CCA_CACHE_DISABLE << 32) | + ((unsigned long)CCA_CACHE_ENABLE << 24) | + ((unsigned long)CCA_CACHE_DISABLE << 16) | + ((unsigned long)CCA_CACHE_ENABLE << 8) | + ((unsigned long)CCA_CACHE_ENABLE); + } else { + /* + * Hart 1 or above: cacheable for pma0, pma1; uncacheable for + * pma2, pma3, pma4. + */ + pmacfg0 = ((unsigned long)CCA_CACHE_DISABLE << 32) | + ((unsigned long)CCA_CACHE_DISABLE << 24) | + ((unsigned long)CCA_CACHE_DISABLE << 16) | + ((unsigned long)CCA_CACHE_ENABLE << 8) | + ((unsigned long)CCA_CACHE_ENABLE); + } + + asm volatile ("csrw %0, %1" :: "i"(CSR_PMACFG0), "r"(pmacfg0)); + asm volatile ("fence" ::: "memory"); + + /* Secondary harts: after early setup, jump to the common entry point */ + if (hartid != 0) + jump_to_addr(CONFIG_SYS_LOAD_ADDR); +} diff --git a/arch/riscv/cpu/p8700/dram.c b/arch/riscv/cpu/p8700/dram.c new file mode 100644 index 00000000000..2b54326be39 --- /dev/null +++ b/arch/riscv/cpu/p8700/dram.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ + if (IS_ENABLED(CONFIG_64BIT)) { + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (gd->ram_top > SZ_4G) + return SZ_4G; + } + return gd->ram_top; +} diff --git a/arch/riscv/cpu/p8700/p8700.c b/arch/riscv/cpu/p8700/p8700.c new file mode 100644 index 00000000000..41d5547c511 --- /dev/null +++ b/arch/riscv/cpu/p8700/p8700.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Chao-ying Fu + */ + +#include +#include +#include + +__weak void wait_ddr_calib(void) { } + +__weak void setup_pcie_dma_map(void) { } diff --git a/arch/riscv/include/asm/arch-p8700/p8700.h b/arch/riscv/include/asm/arch-p8700/p8700.h new file mode 100644 index 00000000000..d6cc125d76a --- /dev/null +++ b/arch/riscv/include/asm/arch-p8700/p8700.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021, Chao-ying Fu + */ + +#ifndef __P8700_H__ +#define __P8700_H__ + +#define CSR_MIPSCONFIG7 0x7d7 +#define CSR_PMACFG0 0x7e0 + +#define MHARTID_HART_SHIFT 0 +#define MHARTID_HART_MASK 0xf +#define MHARTID_CORE_SHIFT 4 +#define MHARTID_CORE_MASK 0xff +#define MHARTID_CLUSTER_SHIFT 16 +#define MHARTID_CLUSTER_MASK 0xf + +#define MARCHID_UARCH_SHIFT 0 +#define MARCHID_UARCH_MASK 0xff +#define MARCHID_CLASS_SHIFT 8 +#define MARCHID_CLASS_MASK 0xff +#define MARCHID_CLASS_M 0 +#define MARCHID_CLASS_I 1 +#define MARCHID_CLASS_P 2 + +#define CM_BASE_CORE_SHIFT 8 +#define CM_BASE_CLUSTER_SHIFT 19 + +#define P8700_TIMER_ADDR 0x16108050 + +#define CCA_CACHE_ENABLE 0 +#define CCA_BUFFER_CACHE 1 +#define CCA_CACHE_DISABLE 2 +#define CCA_UNCACHE_ACC 3 +#define PMA_SPECULATION (0x1 << 3) + +#define L1_I_CACHE 0 +#define L1_D_CACHE 1 +#define L3_CACHE 2 +#define L2_CACHE 3 + +#define HIT_INVALIDATE 4 +#define HIT_WRITEBACK_INV 5 + +#define HIT_INVALIDATE_D ((HIT_INVALIDATE << 2) | L1_D_CACHE) +#define HIT_INVALIDATE_SD ((HIT_INVALIDATE << 2) | L2_CACHE) +#define HIT_WRITEBACK_INV_D ((HIT_WRITEBACK_INV << 2) | L1_D_CACHE) +#define HIT_WRITEBACK_INV_SD ((HIT_WRITEBACK_INV << 2) | L2_CACHE) + +#define L1D_LINE_SIZE_SHIFT 10 +#define L1D_LINE_SIZE_MASK 0x7 + +#define GCR_L2_CONFIG_OFFSET 0x0130 +#define L2_LINE_SIZE_SHIFT 8 +#define L2_LINE_SIZE_MASK 0xf + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_TOR 0x8 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define CM_BASE CONFIG_RISCV_CM_BASE +#define CPC_BASE (CM_BASE + 0x8000) + +/* CPC Block offsets */ +#define CPC_OFF_LOCAL 0x2000 + +#define CPC_PWRUP_CTL 0x0030 + +#define CPC_SYS_CONFIG 0x0140 + +#define CPC_Cx_CMD 0x0000 +#define CPC_Cx_CMD_RESET 0x4 + +#define P8700_GCR_C0_COH_EN 0x20f8 +#define P8700_GCR_C1_COH_EN 0x21f8 +#define P8700_GCR_C2_COH_EN 0x22f8 +#define P8700_GCR_C3_COH_EN 0x23f8 +#define P8700_GCR_C4_COH_EN 0x24f8 +#define P8700_GCR_C5_COH_EN 0x25f8 + +#define GCR_CL_COH_EN 0x2008 +#define GCR_CL_COH_EN_EN (0x1 << 0) +#define GCR_BASE_OFFSET 0x0008 +#define GIC_BASE_OFFSET 0x0080 +#define CPC_BASE_OFFSET 0x0088 +#define ENABLE 0x1 +#define COUNT_STOP (0x1 << 28) +#define GIC_LOCAL_SECTION_OFS 0x8000 +#define GIC_VL_MASK 0x08 +#define GIC_VL_RMASK 0x0c +#define GIC_VL_SMASK 0x10 +#define GIC_VL_COMPARE_MAP 0x44 + +void wait_ddr_calib(void); +void setup_pcie_dma_map(void); + +#endif /* __P8700_H__ */ From patchwork Fri Apr 17 12:24:43 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Stajic X-Patchwork-Id: 2224453 X-Patchwork-Delegate: leo.liang@sifive.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=he8ORSig; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fxvnd6qQmz1yCv for ; Fri, 17 Apr 2026 22:48:37 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9B87B843E8; Fri, 17 Apr 2026 14:44:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.b="he8ORSig"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 815A8841C2; Fri, 17 Apr 2026 14:24:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from MRWPR03CU001.outbound.protection.outlook.com (mail-francesouthazlp170110003.outbound.protection.outlook.com [IPv6:2a01:111:f403:c207::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0F4BE83EEF for ; Fri, 17 Apr 2026 14:24:46 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uros.stajic@htecgroup.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=goa5iYDcMP8lbPVsVyFvV6rwVRsieS4ovJSM61KoaEq0RUYtyrwdSDm73BeohEl2mCDcJbQqCJDokaJK5XiaVMXH56xd02APEiB4OGhd3w4szMdCo3f1WsokAdVFWz8S2YEn2pDxwNAqZc3+RUsM3S4tfj2587B684R3hwSvljrgQ0Mt1lzviUCLzWcLtl8hS9x17Oalsq9AcWyVm318fQjkJQ/KBgU1ZEK6kegO4z9at3SVKzMu2KOUdiDbxSGO9/koasTVvlSIc8vFguKaMuex6jvZ39Jt1ih0hdhFUhDFOBBMk+QeY3QIU0eHZzMoJljwMIGkz10v02JHSIXf6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rS62jmPpz4EvZU+yyXL28zidCmbVLcgpI7lG0IhmWK8=; b=clrfAhAmFcthv8gVxebgnz0T/M7ltZLx3nV5riLubioHqYw3UwMUYliD1ALD52kysxBeQTEoV2gafN5VkNHGcI9oUzt5EdHEfCfMJPVnVsYTnpgVpa+lhedc2hwLnb1G3tdA20jXe74R71JXYJfkb3ix8RQ7vEqNskXfp2yE1gRChXp6+o9T3WPLkJ7M1ZWJJBp6SQ49HGEfpmVIaH8YeqMPH9HO5UOQqsUdJLDRlZPE4ZDK+Q66rpu71lESQnu3iaSh9fO/KE+E0BpruIUkcbyzTSh3O0ciqkjcEPPT3dIOYMnMUt4d4E2NLWPN11mwUrMPh6Ll9jGM8yalzY0W7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=htecgroup.com; dmarc=pass action=none header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rS62jmPpz4EvZU+yyXL28zidCmbVLcgpI7lG0IhmWK8=; b=he8ORSiglSKf3x8Q4teinFZ+r46cXqe2L+wrGhH5wd9UDOmyPAiTwR9ELWFzdQn333K1UMNgDM2YgA1CXNr8k3Iex20ZwUf1muhAfIXS2z2LPx5q4BTeXtDskg1mvx2RfjX9ZN8J/iqEW4vMfHQqmXtbKuvl2F1ZwwCtMjDgJo7yXjKHvKduVFa6QLrTDlfiq6mguuOjMTFNAIAX5+9IEva0cKgMKri1nZKV3KaOuUBvMO8jtwjtCI+N/XcEIAF1evsqS4DH9t7+99BJGq54Y2hXbkl1iNFe6xLGHJ4B/yXGTYMcC5x8Fz8B1uI8xmuPWAJW0GW+HWIixcsDwILdmQ== Received: from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20) by AS5PR09MB8577.eurprd09.prod.outlook.com (2603:10a6:20b:753::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr 2026 12:24:44 +0000 Received: from PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81%2]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026 12:24:44 +0000 From: Uros Stajic To: "u-boot@lists.denx.de" CC: Djordje Todorovic , Leo Yu-Chi Liang , Rick Chen , Chao-ying Fu , Uros Stajic Subject: [PATCH v7 2/7] board: boston-riscv: Add initial support for P8700 Boston board Thread-Topic: [PATCH v7 2/7] board: boston-riscv: Add initial support for P8700 Boston board Thread-Index: AQHczmUr+q3l+GyXmECbO0GpqEJK8Q== Date: Fri, 17 Apr 2026 12:24:43 +0000 Message-ID: <20260417122213.147529-3-uros.stajic@htecgroup.com> References: <20260417122213.147529-1-uros.stajic@htecgroup.com> In-Reply-To: <20260417122213.147529-1-uros.stajic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA3PR09MB8140:EE_|AS5PR09MB8577:EE_ x-ms-office365-filtering-correlation-id: 8af9b3e6-984f-4ac4-ae3d-08de9c7c4e4c x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|1800799024|376014|366016|38070700021|18002099003|22082099003|56012099003; x-microsoft-antispam-message-info: p20gIYjUrRqAJYY1uGUNgJ/CcdAxlMpCs1QmTCtB2jNebqcBHCuowYYV/hE64w/zdoauowGn9LlOLfQVgtlIoTrOsHWCiyJlWlUNapC4navqN9WDG5J9TOohjYnXWL4tkeJyL6MEHQ4Tw8IZuHaAZIyLX69ye1b0W+SMiCe+QeUixqRQ44RolDPpK6Lu0uJMNrFTDZHySniIG1JGNGgNad1DJFLmfgUjy3QizYrkcaxokwsATqqcfjslscgW512rwBf0Ci5y8hqEqXZt3t2V4OWdWcIUz9G3yL7AzJ7jbO7dE9imE/Qko/XqnXUwwFV+Zx+04948B/BW3ISWX3X1S9PdNpZQk1AOoLjrn2yzIcL85T+u7dtCpNoE1K5D2V2vQ3gDKLdv+hSB0p91YY5kZzJviZ+ZM7StrYUzWmngmymED+5wYH3RKCbTbDyQFqzdQv/WxQuIGQinuKCXM2TxB+91lSwcNrhBzp+fEx7GOrNtLg+mhrC5iaRggsySatyKUBd3z1YcOk8XBhRp5HBanwWGraIJGpzaajeQ7k/hPm30xEdoJ+uV1ILApYAZbyl4eE2hEqdrT1aEJ6jLxWUW4BIqd8h+MXYUnYUFwBHmQdnUuca7cOKBNQovPjAnJB2l6ur8vH3FQoZpY894oiolQW72Lu0TrcjDY10R5JHULs2psuUmfE9En1CkS1ObVhjvgsLGFnJDQYQt1vgY8ddBYhwpZsZrx7nAoLs6ZOLjFo79OgE8kX32104hb1TL3cUm6lWY3m8lrhZUsnig/FKrHasYYky3eY101yeNZ9kSOSk= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(376014)(366016)(38070700021)(18002099003)(22082099003)(56012099003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?q?tFjpjmz/7dZyYa39zbP2WQC?= =?iso-8859-1?q?z//bY7LVshDHtLzrHC9PlFjnXegUFBV/3IjuPSqc29zPDVGL1N34JAkwz8IJ?= =?iso-8859-1?q?8tpFOfNxLji1PTjVkENurMbIxlj6LYGdIUMOanfSHloxaHCUtYw5hEORx5LT?= =?iso-8859-1?q?mmCuPHol0XEWzdz0OYHSVxr6LJn4F+BplaBnt/o89i0W/hrAvem7gvojC0jr?= =?iso-8859-1?q?NagqcCygskHuyUYqPN/BYazrFDX+lZJowdnYM9gy7pFRHM2BwkzQsYZWok1r?= =?iso-8859-1?q?NnvE3MLB+A3Z21yWnAYQ1v7IMltvStEuxKjz27pgQqFKWUxZH+e7i2vnCLwL?= =?iso-8859-1?q?mu4+RoxN6w00bEjUnCGo+4xMgD8tWzQUHw1fKwl8ICTNABWFDCQQBsGs90RZ?= =?iso-8859-1?q?lrqb6PiXMxcL7HVJhlvSxImwP1A6trLo5f1BXfMF+LWFefyCFA6qIwzdPWiL?= =?iso-8859-1?q?vGsCVnhgpP0aXhoy9G5MaRv1xdwNksAbT0tOYn8B4M8VJLcHX/99P+ZC067l?= =?iso-8859-1?q?u+tiogrdO1ez80EbqRs6z/UnGQj9e58bV3j7dzYOMx6lz9t1YBNJkMMHwvlS?= =?iso-8859-1?q?p0mvlK9d66nei+AfpZzO6ayGmJTpQP4KNtHlvxtxj2bEdq7lXixbHOiZx5uQ?= =?iso-8859-1?q?CpSS7we+mIjkhFhuTrFHuicbxnPjIMYM+SyPZYNBmJ2KvRSqGCTWpzdCWoIZ?= =?iso-8859-1?q?jkjGCKfTwiOmzWyFlFXZJl6nVmBr4xOeo+jhG8/NpKwxs3+iYFE1T4E7kJJ5?= =?iso-8859-1?q?h5qUqoWeVNUQChGd3QfeM1Uikpt/B8wJUBXv4AVlkvMwdLc+kNTEpYvR4j6x?= =?iso-8859-1?q?W8wX8tU//GX74Izetlsj+fpakESNNMJdhlXIjdovEevOERZClT17PSuVMJPc?= =?iso-8859-1?q?r/6JV8y3+H18ON1b233skHRaXaQgK+vivIc87A2s8hu8UCsFAhmFBbMrL482?= =?iso-8859-1?q?AnFW2fkM3ghnnKzEnyz+Zl+kDoeMV9qo5tNRAXLkESb8PUrNpA8RkVAqrPK3?= =?iso-8859-1?q?eunmOxkzr0Ev/2u7H2k5QcVjm4S4ileoXjP//44oBHTOO5PEyhVicCERO21J?= =?iso-8859-1?q?PSyRKWJrSfhMRxRbm7ITQMvUyAmxMquhIy12ps9pj9QcK3bwK9eifkkOo8/r?= =?iso-8859-1?q?Iecc7SrFZlq5pwk5SFCpvuZL7Zp/pbwznojtLmTkhiOkPeCmXfxciwIHEbfy?= =?iso-8859-1?q?Xyxk7Sr4gS8tQBJwoTMXMHCyunZaEdlQs2mjPVZ+9jRWLkwORhLM7eWJ9v+d?= =?iso-8859-1?q?3L0YE8GIuhBO3KYyBMm+1U04zIZ7k2JS6LpTv3L8D03eVtTacOWbIKnX4cLn?= =?iso-8859-1?q?TRn5/qY2GlfGghPswvpghc5tENRnuFpGeSLNfuN7ttxcfcwQp/L0bCBALly6?= =?iso-8859-1?q?XwBGD6JMj1r5UMDf0CEQOkxIFfr9hRTb4GDLRzRUC66SkqmhlSK05j5RoUYw?= =?iso-8859-1?q?rQhZLoevzgtfJvXgDArs+rQGJs2h9ozyDUYddkTUh05f8nmaMhkKaZH/OEGT?= =?iso-8859-1?q?RU6Lv1BxlKQCFbidjWFDUvOitDG3J5eqtax4Vx/Gwbh6ZYHCY5sbMvGXKUxQ?= =?iso-8859-1?q?+6bpKrM5RpsNNtp2p42cO872E5xzhVzXVkja/fKGrVTVrio6ZtwzPRJScZN+?= =?iso-8859-1?q?XQp3xKAwUXkeG+1NqvEPf9Jjd4Tts2pmxB++AL2puWcEggexAu4pHU4y6vsr?= =?iso-8859-1?q?kcaBHManCtpyhJYhicZH4daPgHt/K8Ry80tqnPCyffOGgFinY62/WfpKPC3g?= =?iso-8859-1?q?MJWV+Xjgf66FujOiPw79ZRmsrKlWNuZMz1rOGcb5fG+7H3zzRlpI5Z3SBhl7?= =?iso-8859-1?q?Pz6KQfHM=3D?= MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA3PR09MB8140.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8af9b3e6-984f-4ac4-ae3d-08de9c7c4e4c X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2026 12:24:43.6310 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: T5DN6QPqhCaEzsdJOqBGrRorCLeiGG9UVnK4vL+O0Rz8g8/nRBD6hTixx0XJPzETX7sZ8lbsJy9CJ7b3piSzC6+/2JKdCFQcOKwaSeX8GDI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR09MB8577 X-Mailman-Approved-At: Fri, 17 Apr 2026 14:43:59 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Chao-ying Fu Implement initial board-level support for the P8700 Boston SoC. Reviewed-by: Leo Yu-Chi Liang Signed-off-by: Chao-ying Fu Signed-off-by: Uros Stajic --- arch/riscv/Kconfig | 11 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/boston-p8700.dts | 264 ++++++++++++++++++++++++ board/mips/boston-riscv/Kconfig | 43 ++++ board/mips/boston-riscv/MAINTAINERS | 9 + board/mips/boston-riscv/Makefile | 8 + board/mips/boston-riscv/boston-lcd.h | 20 ++ board/mips/boston-riscv/boston-regs.h | 42 ++++ board/mips/boston-riscv/boston-riscv.c | 48 +++++ board/mips/boston-riscv/checkboard.c | 43 ++++ board/mips/boston-riscv/config.mk | 15 ++ board/mips/boston-riscv/lowlevel_init.S | 18 ++ board/mips/boston-riscv/reset.c | 15 ++ configs/boston-p8700_defconfig | 98 +++++++++ drivers/clk/Kconfig | 2 +- include/configs/boston-riscv.h | 9 + 16 files changed, 645 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/dts/boston-p8700.dts create mode 100644 board/mips/boston-riscv/Kconfig create mode 100644 board/mips/boston-riscv/MAINTAINERS create mode 100644 board/mips/boston-riscv/Makefile create mode 100644 board/mips/boston-riscv/boston-lcd.h create mode 100644 board/mips/boston-riscv/boston-regs.h create mode 100644 board/mips/boston-riscv/boston-riscv.c create mode 100644 board/mips/boston-riscv/checkboard.c create mode 100644 board/mips/boston-riscv/config.mk create mode 100644 board/mips/boston-riscv/lowlevel_init.S create mode 100644 board/mips/boston-riscv/reset.c create mode 100644 configs/boston-p8700_defconfig create mode 100644 include/configs/boston-riscv.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d3380c3ac3f..edb5e6da10b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,16 @@ config TARGET_XILINX_MBV config TARGET_ASPEED_AST2700_IBEX bool "Support Ibex RISC-V cores on Aspeed AST2700 SoC" +config TARGET_MIPS_BOSTON + bool "Support Mips Boston Board" + select DM + select DM_EVENT + select DM_GPIO + select DM_SERIAL + select OF_CONTROL + select DISTRO_DEFAULTS + imply CMD_DM + endchoice config SYS_ICACHE_OFF @@ -123,6 +133,7 @@ source "board/spacemit/bananapi-f3/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" +source "board/mips/boston-riscv/Kconfig" # platform-specific options below source "arch/riscv/cpu/andes/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 8e591cb7aa9..0ec297b5c45 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb +dtb-$(CONFIG_TARGET_MIPS_BOSTON) += boston-p8700.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/boston-p8700.dts b/arch/riscv/dts/boston-p8700.dts new file mode 100644 index 00000000000..8207017c6ce --- /dev/null +++ b/arch/riscv/dts/boston-p8700.dts @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Chao-ying Fu + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "p8700"; + compatible = "mips,p8700-boston"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,p8700", "riscv"; + reg = <0>; + mmu-type = "riscv,sv39"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb"; + clocks = <&clk_boston BOSTON_CLK_CPU>; + clock-frequency = <25000000>; + bootph-all; + status = "okay"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + timer@16154000 { + compatible = "riscv,aclint-mtimer"; + reg = <0x16108050 0x8>, + <0x16154000 0x7ff8>; + interrupts-extended = <&cpu0_intc 7>; + }; + + gic: interrupt-controller { + compatible = "mti,gic"; + + interrupt-controller; + #interrupt-cells = <3>; + }; + + pci0: pci@10000000 { + device_type = "pci"; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x10000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = ; + + ranges = <0x02000000 0 0x40000000 + 0x40000000 0 0x40000000>; + + bus-range = <0x00 0xff>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci0_intc 1>, + <0 0 0 2 &pci0_intc 2>, + <0 0 0 3 &pci0_intc 3>, + <0 0 0 4 &pci0_intc 4>; + + status = "disabled"; + + pci0_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci1: pci@12000000 { + device_type = "pci"; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x12000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = ; + + ranges = <0x02000000 0 0x20000000 + 0x20000000 0 0x20000000>; + + bus-range = <0x00 0xff>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci1_intc 1>, + <0 0 0 2 &pci1_intc 2>, + <0 0 0 3 &pci1_intc 3>, + <0 0 0 4 &pci1_intc 4>; + + status = "disabled"; + + pci1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci2: pci@14000000 { + device_type = "pci"; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x14000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = ; + + ranges = <0x02000000 0 0x16000000 + 0x16000000 0 0x100000>; + + bus-range = <0x00 0xff>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci2_intc 1>, + <0 0 0 2 &pci2_intc 2>, + <0 0 0 3 &pci2_intc 3>, + <0 0 0 4 &pci2_intc 4>; + + pci2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + pci2_root@0,0,0 { + compatible = "pci10ee,7021", "pci-bridge"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_bridge@1,0,0 { + compatible = "pci8086,8800", "pci-bridge"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802", "intel,pch-gbe"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803", "intel,eg20t-gpio"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; + + mmc0: mmc@2,4,0 { + compatible = "intel,apl-sd"; + reg = <0x00022000 0 0 0 0>; + }; + + mmc1: mmc@2,4,1 { + compatible = "intel,apl-sd"; + reg = <0x00022100 0 0 0 0>; + }; + + eg20t_i2c@2,12,2 { + compatible = "pci8086,8817"; + reg = <0x00026200 0 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + rtc@0x68 { + compatible = "st,m41t81s"; + reg = <0x68>; + }; + }; + }; + }; + }; + + plat_regs: system-controller@17ffd000 { + compatible = "img,boston-platform-regs", "syscon"; + reg = <0x17ffd000 0x1000>; + bootph-all; + }; + + clk_boston: clock { + compatible = "img,boston-clock"; + #clock-cells = <1>; + regmap = <&plat_regs>; + bootph-all; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&plat_regs>; + offset = <0x10>; + mask = <0x10>; + }; + + uart0: uart@17ffe000 { + compatible = "ns16550a"; + reg = <0x17ffe000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + + interrupt-parent = <&gic>; + interrupts = ; + + clocks = <&clk_boston BOSTON_CLK_SYS>; + clock-frequency = <25000000>; + + bootph-all; + }; + + lcd: lcd@17fff000 { + compatible = "img,boston-lcd"; + reg = <0x17fff000 0x8>; + }; + + flash@18000000 { + compatible = "cfi-flash"; + reg = <0x18000000 0x8000000>; + bank-width = <2>; + }; +}; diff --git a/board/mips/boston-riscv/Kconfig b/board/mips/boston-riscv/Kconfig new file mode 100644 index 00000000000..bada4b6752d --- /dev/null +++ b/board/mips/boston-riscv/Kconfig @@ -0,0 +1,43 @@ +if TARGET_MIPS_BOSTON + +config SYS_BOARD + default "boston-riscv" + +config SYS_VENDOR + default "mips" + +config SYS_CONFIG_NAME + default "boston-riscv" + +config SYS_CPU + default "p8700" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select P8700_RISCV + imply SYS_NS16550 + +config SYS_CACHELINE_SIZE + default 64 + +config SYS_SDRAM_BASE + hex + default 0x80000000 + +config SYS_INIT_SP_ADDR + hex + default 0x80200000 + +config STANDALONE_LOAD_ADDR + hex + default 0x80200000 + +config SYS_MAX_FLASH_BANKS_DETECT + bool + default y + +config PHY_REALTEK + bool + default y + +endif diff --git a/board/mips/boston-riscv/MAINTAINERS b/board/mips/boston-riscv/MAINTAINERS new file mode 100644 index 00000000000..d03491d0f0c --- /dev/null +++ b/board/mips/boston-riscv/MAINTAINERS @@ -0,0 +1,9 @@ +BOSTON-RISCV BOARD +M: Chao-ying Fu +S: Maintained +F: board/mips/boston-riscv/ +F: include/configs/boston-riscv.h +F: arch/riscv/cpu/p8700/ +F: arch/riscv/include/asm/arch-p8700/ +F: configs/boston-p8700_defconfig +F: arch/riscv/dts/boston-p8700.dts diff --git a/board/mips/boston-riscv/Makefile b/board/mips/boston-riscv/Makefile new file mode 100644 index 00000000000..0615c677d23 --- /dev/null +++ b/board/mips/boston-riscv/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2016 Imagination Technologies + +obj-y += boston-riscv.o +obj-y += checkboard.o +obj-y += lowlevel_init.o +obj-y += reset.o diff --git a/board/mips/boston-riscv/boston-lcd.h b/board/mips/boston-riscv/boston-lcd.h new file mode 100644 index 00000000000..5f5cd0fe126 --- /dev/null +++ b/board/mips/boston-riscv/boston-lcd.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#ifndef __BOARD_BOSTON_LCD_H__ +#define __BOARD_BOSTON_LCD_H__ + +/** + * lowlevel_display() - Display a message on Boston's LCD + * @msg: The string to display + * + * Display the string @msg on the 7 character LCD display of the Boston board. + * This is typically used for debug or to present some form of status + * indication to the user, allowing faults to be identified when things go + * wrong early enough that the UART isn't up. + */ +void lowlevel_display(const char msg[static 8]); + +#endif /* __BOARD_BOSTON_LCD_H__ */ diff --git a/board/mips/boston-riscv/boston-regs.h b/board/mips/boston-riscv/boston-regs.h new file mode 100644 index 00000000000..60343368a68 --- /dev/null +++ b/board/mips/boston-riscv/boston-regs.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#ifndef __BOARD_BOSTON_REGS_H__ +#define __BOARD_BOSTON_REGS_H__ + +#ifndef BOSTON_PLAT_BASE +#define BOSTON_PLAT_BASE (0x17ffd000) +#endif +#define BOSTON_LCD_BASE (0x17fff000) + +/* + * Platform Register Definitions + */ +#define BOSTON_PLAT_CORE_CL (BOSTON_PLAT_BASE + 0x04) + +#define BOSTON_PLAT_SOFT_RST (BOSTON_PLAT_BASE + 0x10) +#define BOSTON_PLAT_SOFT_RST_SYSTEM (0x1 << 4) + +#define BOSTON_PLAT_DDR3STAT (BOSTON_PLAT_BASE + 0x14) +#define BOSTON_PLAT_DDR3STAT_CALIB (0x1 << 2) + +#define BOSTON_PLAT_BUILDCFG0 (BOSTON_PLAT_BASE + 0x34) +#define BOSTON_PLAT_BUILDCFG0_IOCU (0x1 << 0) +#define BOSTON_PLAT_BUILDCFG0_PCIE0 (0x1 << 1) +#define BOSTON_PLAT_BUILDCFG0_PCIE1 (0x1 << 2) +#define BOSTON_PLAT_BUILDCFG0_PCIE2 (0x1 << 3) +#define BOSTON_PLAT_BUILDCFG0_CFG_LTR (0xf << 4) +#define BOSTON_PLAT_BUILDCFG0_CFG_NUM (0xff << 8) +#define BOSTON_PLAT_BUILDCFG0_DP (0x1 << 24) +#define BOSTON_PLAT_BUILDCFG0_DP_MULT (0xf << 28) + +#define BOSTON_PLAT_DDRCONF0 (BOSTON_PLAT_BASE + 0x38) +#define BOSTON_PLAT_DDRCONF0_SIZE (0xf << 0) + +#define BOSTON_PLAT_NOCPCIE0ADDR (BOSTON_PLAT_BASE + 0x3c) +#define BOSTON_PLAT_NOCPCIE1ADDR (BOSTON_PLAT_BASE + 0x40) +#define BOSTON_PLAT_NOCPCIE2ADDR (BOSTON_PLAT_BASE + 0x44) + +#endif /* __BOARD_BOSTON_REGS_H__ */ diff --git a/board/mips/boston-riscv/boston-riscv.c b/board/mips/boston-riscv/boston-riscv.c new file mode 100644 index 00000000000..f3fd2ec8348 --- /dev/null +++ b/board/mips/boston-riscv/boston-riscv.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#include "boston-regs.h" +#include +#include +#include +#include + +#define PMACFG0_PMP3_SHIFT 24 +#define PMACFG0_PMP3_MASK (0xffUL << PMACFG0_PMP3_SHIFT) +#define BOSTON_IOCU_NOC_OFFSET 0x10 + +int board_early_init_r(void) +{ + if (!IS_ENABLED(CONFIG_RISCV_MMODE)) + return 0; + ulong pmacfg0 = csr_read(CSR_PMACFG0); + + /* + * Make the flash region (PMA entry corresponding to pmp3) uncached by + * setting the CCA field in CSR_PMACFG0[31:24]. + */ + pmacfg0 &= ~PMACFG0_PMP3_MASK; + pmacfg0 |= (ulong)CCA_CACHE_DISABLE << PMACFG0_PMP3_SHIFT; + + csr_write(CSR_PMACFG0, pmacfg0); + asm volatile ("fence" ::: "memory"); + + return 0; +} + +void wait_ddr_calib(void) +{ + while (!(readl((void __iomem *)BOSTON_PLAT_DDR3STAT) & + BOSTON_PLAT_DDR3STAT_CALIB)) { + /* busy-wait */ + } +} + +void setup_pcie_dma_map(void) +{ + writel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE0ADDR); + writel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE1ADDR); + writel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE2ADDR); +} diff --git a/board/mips/boston-riscv/checkboard.c b/board/mips/boston-riscv/checkboard.c new file mode 100644 index 00000000000..c7bf6734433 --- /dev/null +++ b/board/mips/boston-riscv/checkboard.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#include "boston-lcd.h" +#include "boston-regs.h" +#include +#include +#include + +int checkboard(void) +{ + u32 changelist, cfg, core, uarch; + u64 marchid; + + lowlevel_display("U-boot "); + + printf("Board: Mips Boston RISC-V\n"); + + changelist = __raw_readl((uint32_t *)BOSTON_PLAT_CORE_CL); + if (changelist > 1) { + asm volatile ("csrr %0, marchid" : "=r"(marchid)::); + core = (marchid >> MARCHID_CLASS_SHIFT) & MARCHID_CLASS_MASK; + uarch = (marchid >> MARCHID_UARCH_SHIFT) & MARCHID_UARCH_MASK; + + printf("Core: class%x uarch%x cl%x", core, uarch, changelist); + + cfg = __raw_readl((uint32_t *)BOSTON_PLAT_BUILDCFG0); + if (cfg & BOSTON_PLAT_BUILDCFG0_CFG_NUM) + printf(" config %u", + (cfg & BOSTON_PLAT_BUILDCFG0_CFG_NUM) >> 8); + if (cfg & BOSTON_PLAT_BUILDCFG0_CFG_LTR) + printf("%c", + 'a' + ((cfg & BOSTON_PLAT_BUILDCFG0_CFG_LTR) >> 4) - 1); + if (cfg & BOSTON_PLAT_BUILDCFG0_DP) + printf(", x%u debug port", + (cfg & BOSTON_PLAT_BUILDCFG0_DP_MULT) >> 28); + printf("\n"); + } + + return 0; +} diff --git a/board/mips/boston-riscv/config.mk b/board/mips/boston-riscv/config.mk new file mode 100644 index 00000000000..c1e242f1088 --- /dev/null +++ b/board/mips/boston-riscv/config.mk @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ + +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -$2 \ + $< -binary \ + -fill 0x00 -within $< -binary -range-pad 16 \ + -offset $3 + +u-boot.mcs: u-boot.bin + $(call cmd,srec_cat,intel,0x7c00000) + +# if srec_cat is present build u-boot.mcs by default +has_srec_cat = $(call try-run,srec_cat -VERSion,y,n) +INPUTS-$(has_srec_cat) += u-boot.mcs +CLEAN_FILES += u-boot.mcs diff --git a/board/mips/boston-riscv/lowlevel_init.S b/board/mips/boston-riscv/lowlevel_init.S new file mode 100644 index 00000000000..8fa85749e40 --- /dev/null +++ b/board/mips/boston-riscv/lowlevel_init.S @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#include "boston-regs.h" + +.data + +msg_ddr_cal: .ascii "DDR Cal " +msg_ddr_ok: .ascii "DDR OK " + +.text + + .globl lowlevel_display +lowlevel_display: + li t0, BOSTON_LCD_BASE + jr ra diff --git a/board/mips/boston-riscv/reset.c b/board/mips/boston-riscv/reset.c new file mode 100644 index 00000000000..8e7e0572aad --- /dev/null +++ b/board/mips/boston-riscv/reset.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Imagination Technologies + */ + +#include "boston-regs.h" +#include +#include + +void _machine_restart(void) +{ + writel(BOSTON_PLAT_SOFT_RST_SYSTEM, (void __iomem *)BOSTON_PLAT_SOFT_RST); + + udelay(1000); +} diff --git a/configs/boston-p8700_defconfig b/configs/boston-p8700_defconfig new file mode 100644 index 00000000000..498ccb15b4c --- /dev/null +++ b/configs/boston-p8700_defconfig @@ -0,0 +1,98 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x1fc00000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_TARGET_MIPS_BOSTON=y +CONFIG_DEFAULT_DEVICE_TREE="boston-p8700" + +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_BOOTDELAY=-1 + +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ARCH_RV64I=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_INIT=n +#CONFIG_CMD_BOOTEFI_SELFTEST=y +#CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MII=y +# CONFIG_OF_PRIOR_STAGE=y +CONFIG_DM_MTD=y +CONFIG_SMP=n +CONFIG_XIP=y +CONFIG_CLK_BOSTON=y +CONFIG_RISCV_ISA_C=n +CONFIG_SHOW_REGS=y +CONFIG_SYS_NS16550=y + +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_ADDR=0x1ffc0000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_USE_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_LZ4=y +CONFIG_CLK=y +CONFIG_EG20T_GPIO=y + +CONFIG_MMC=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_CPU=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_PCI=y + +CONFIG_UNIT_TEST=y +CONFIG_UT_LIB=n +CONFIG_UT_LIB_ASN1=n +CONFIG_UT_LOG=n +CONFIG_UT_TIME=y +CONFIG_UT_UNICODE=n +CONFIG_UT_ENV=n +CONFIG_UT_OVERLAY=n + +CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_TEXT_BASE=0x1fc00000 +CONFIG_SYS_MALLOC_LEN=0x00800000 +CONFIG_SYS_BOOTM_LEN=0x04000000 +CONFIG_SYS_MAX_FLASH_SECT=1024 +CONFIG_PHY_ANEG_TIMEOUT=40000 +CONFIG_NET_RETRY_COUNT=10 +CONFIG_ENV_CALLBACK_LIST_STATIC="io.coherent:io_coherent," +CONFIG_BOOTARGS="root=/dev/sda rw earlycon console=ttyS0,115200n8r" +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_PCI_BRIDGE_MEM_ALIGNMENT=0x1 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c2da7b3938b..16278ca42f3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -60,7 +60,7 @@ config CLK_BCM6345 clocks on BCM6345 SoCs. HW has no rate changing capabilities. config CLK_BOSTON - def_bool y if TARGET_BOSTON + def_bool y if TARGET_BOSTON || TARGET_MIPS_BOSTON depends on CLK select REGMAP select SYSCON diff --git a/include/configs/boston-riscv.h b/include/configs/boston-riscv.h new file mode 100644 index 00000000000..f1ee6f6032a --- /dev/null +++ b/include/configs/boston-riscv.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021, Chao-ying Fu + */ + +#ifndef __CONFIG_BOSTON_RISCV_H +#define __CONFIG_BOSTON_RISCV_H + +#endif /* __CONFIG_BOSTON_RISCV_H */ From patchwork Fri Apr 17 12:25:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Stajic X-Patchwork-Id: 2224454 X-Patchwork-Delegate: leo.liang@sifive.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=f9d9EgAo; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fxvnq0llYz1yCv for ; Fri, 17 Apr 2026 22:48:47 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DCC71843F9; Fri, 17 Apr 2026 14:44:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.b="f9d9EgAo"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1B364841C2; Fri, 17 Apr 2026 14:25:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazlp170110003.outbound.protection.outlook.com [IPv6:2a01:111:f403:c201::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 10C1B83EEF for ; Fri, 17 Apr 2026 14:25:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uros.stajic@htecgroup.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=i0H/+LrYiHYC39JRGnvBSY25+iMlwNSs+Zi5QweNKQH/gmDbn6cmcw01v2J3YF5ErDQZw8UlItPXpeQB980FnKC3SVvVQRbqXDY9rchkrMIRxgsl1OXhoWGJMchC80RBjMN2GKbheJ5lst1X2QOs5Hvxdnv9pkKd206Lf8gjNMlAEq2HYdTf8wh0IdoI5dFECDWyijRe0yql3PlMzl5JaAEUaVzS9bEpIjc4OftB1jGk4bLFXrYQecIkc6ZXJiwY8uc++i718AIKpdB17xg5v9YnD7bqCM1VUsWw4UoApKB1WK04jvY9NLe/D40QUYgdhlWKofNpJ1T4rl3aQGxYAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SnGcDATHOxzOzavt8wlv42hwS+gDK+R5BVb9Ds+6lXI=; b=KLX2ukAsihtKkfeV7n+BfIxmlLH7geh7M4rUSjlHjJtO/esb3RV/Mzv4iY1ERaMYNsUWHbEb4g/8NAlNsHDPp/g408zT35oew5WaSMgSMh05zdq2mOn6rMs98PtxI3UCJ11vxnqtfPelXzIgu6Ox8lSMJ4/fmxT4VoQ3G/oO9r3kVMWZfmvLPZm/WbqXzSk5LCHPTbxayrwvYPP3PjsH0pl+x0SnxTS84In/7KjFCm9bWG56GsCtlry3zggi2Jdvu9XKJbYfwJXYS4fHpsFV5NGDonSMbjpfE6hVWURhprJhrtHULYtp/F3cCzcJBIsxp/l+1W4FTe1qrF2d3BRP9A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=htecgroup.com; dmarc=pass action=none header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SnGcDATHOxzOzavt8wlv42hwS+gDK+R5BVb9Ds+6lXI=; b=f9d9EgAoGwCxwZzUgPFeWC6oLFRMf89EK1Ta8AaF6eH4AaPMydz5NkMGyVwJZddBP33ImtEQOW4WqYdu5ZtnrQKAjaLKol5pwTYNyYEe9yRN6K+5tDXNEvP4lFYbZGxK2VXLtfOBw6RAOiV//bn70ZhXL9Zh1A9Oru6zx+t37y+jRlYsdrA47GQhfE1OEnaf7m8H8t0y6on6T0LImO7eZDJvMKCd2qnKZTesWweaYrCGMyz6K0dpXBXKRAzKPijSJw1UlBEE+Zi1f7PWkMFmg/OMBz3aoKjvSs5qEalGuTaE8tbr7rDw65c2ep770U5NTOk9Wmgb5Oba7CHLUVStWg== Received: from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20) by DB9PR09MB6861.eurprd09.prod.outlook.com (2603:10a6:10:4c9::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr 2026 12:25:19 +0000 Received: from PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81%2]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026 12:25:19 +0000 From: Uros Stajic To: "u-boot@lists.denx.de" CC: Djordje Todorovic , Leo Yu-Chi Liang , Rick Chen , Chao-ying Fu , Uros Stajic Subject: [PATCH v7 3/7] gpio: Add GPIO driver for Intel EG20T Thread-Topic: [PATCH v7 3/7] gpio: Add GPIO driver for Intel EG20T Thread-Index: AQHczmVAv4L9D4vFgE28/J4wnIJ6ng== Date: Fri, 17 Apr 2026 12:25:18 +0000 Message-ID: <20260417122213.147529-4-uros.stajic@htecgroup.com> References: <20260417122213.147529-1-uros.stajic@htecgroup.com> In-Reply-To: <20260417122213.147529-1-uros.stajic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA3PR09MB8140:EE_|DB9PR09MB6861:EE_ x-ms-office365-filtering-correlation-id: 89bb30cd-c9f5-416b-9c36-08de9c7c6376 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|1800799024|376014|366016|38070700021|18002099003|22082099003|56012099003; x-microsoft-antispam-message-info: K/1FQLV44tLkUmbLfs5HKS+B5tQNCleB9tvoSWSSioNLZFPKWDCTbwxVMmczc25D3huD4PG9yqnLIzeKrkBHKBXSnZRvr4D7ls8RLUE0p1/dyejjRTqY+RQ1qFyM+noeuzSwqjqZGVTEGPP2hpr676vKtw/Dt1r6g3p6Q8MTUu4n3FDXVMtUybCZrbXOFXViPCdFR0SP5qDM9Py7CIc4Ms6R1POkZ8g7E9qs8c2eOzhmCQLjLADub1pfhNr/6VbY4bP+MHMHWSCj7KzK+D2IL/n43n5IkosbZ7C6yWXLCU9QdSERxEkluM/LFneC37W8h1+KV4FRgRua5sHoxbWDj8ob5kQuKquVz0G9GNVdKs8IYl3JZ0LIQC4W/CSnNY6zvDG29FvQXgBEqHmuEE496qQT3/SJSvu5XkznVGyWt3uvdOHs5gJdDuyJL6ERcJPGFU27jkbRS8EgMTevZZrg9hhPPheZ55WtJWb0quqjFXyKyLgLEfAFv+SmZiLvsGo8AGlZ4yBuY43Dlo53jGnKooPehGsMlfiMBeE6S+eyFUOkDjCUrOM28rK6RT+OEPYy56h/zZobx2WIbpPbc9pxoiHx79tbTIv66mA/PZLO7QGg4uWF92e+EqCHV15eEuQ8MoAfYtnQNegiUQivtfFnge2MdhfyCMcfEEaC/ied/QgiJBb6a+U7Sq5Je9LO5YBXzGdG6HWgM/58V2TMIux+htj4WelwbaUBSdW2iZya3KLgkbr24p+BOcU4oh4ejC5ERcRngAENQSd1KMiSTy0dEbX6MRHUs86Qb4vq3hHMvDQ= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(376014)(366016)(38070700021)(18002099003)(22082099003)(56012099003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?q?7AwWFIOMO3J86K+zaOTQPRY?= =?iso-8859-1?q?Lr1tZFzKm2lFNnhPaYG14ma4Vv2wwkbjuwGVA/FkvB61vaiiWUXICDJg48Dr?= =?iso-8859-1?q?IRMWuqg42QSQQGurAYLNDKHFkH8MSzpqbSxqu6JzAkqizc64ZQQYIWfuq3S+?= =?iso-8859-1?q?HkweRh4m8STlR9xjQAaZ102QIDWtJBUePoNDyFxrEblzpdAOMPxwH+gIEZLd?= =?iso-8859-1?q?ToBhoHPfP4F3tn3XDjRkdMmja5BJlSpm4OQMKKSRbiNtFojijiYs+LXu77t+?= =?iso-8859-1?q?QcSpV9N1qCjlcD4DxtK7PZqblzTh0u31vywVW9DFcP8eXkEnf/qbV9FulXLK?= =?iso-8859-1?q?v6uyiVvxmAQwuw1yiapnGWnoZNPMuvHX9+zCBWahyGa8QAude6ej4/hX6mq7?= =?iso-8859-1?q?u4yTkZD8wPe1F8yStjs0noBS/UWtRKEXJ7VmfmFuS+VHlAA6Jf0HBAEQ6qn2?= =?iso-8859-1?q?mrFCETFxUSrELYNjcytGuNriPsipkt8ueul9oDca/EaIdd2VP/1YA5U468MB?= =?iso-8859-1?q?uLo3d9Lie35bkmrsM31acw2vSMERjciAVR237IXeMhYOT3ucBM487T4xl/Od?= =?iso-8859-1?q?akQe2GMapbn7L4RnLIqw69xc73X6GxuBdJXehMT0WGi61J4o3hDVLLdUx3Aq?= =?iso-8859-1?q?2Hy26/5fhDy3Upj5kMpglAU9AGEgy348VhYpNHQr/UKoCNIlds3aTNyimDjh?= =?iso-8859-1?q?VzrCLnKDnX8pUw8a5mSXlzZE8+vXND6CcQpnvuFp3vrli9WWhA4lNIXR1xHK?= =?iso-8859-1?q?aXHabyJpVUeh17IG2JFk12as1iGS5lPAWXOXWETA593iejeY64pOTxoL1SvM?= =?iso-8859-1?q?+iPKBfJOxkFTYCFDkUYbohA7AOvfla1/T72eIm6AfB0EeFcQ+6wOC1Y0TeSl?= =?iso-8859-1?q?kW3CIdDCs9sdKrbqBQp+/dkQyscdwbz9Y+7VchiJlq3oE8QmvJa86fF2HhpL?= =?iso-8859-1?q?oCHATUbnoXfe91IkCPGt5hAk97DvwDUwQ5OqhuwB84q+F0P3YW7n66SqHUtH?= =?iso-8859-1?q?pnuwpr+jMvOKl04btkT7zJK/DM9pA7gI/Q9O3aQ5issKmBrHxBiWrB1p2nkq?= =?iso-8859-1?q?3gN5hoprtDRQVhFciSIOmStkOWNGpCN4gyaQeOXjufFEbAGIbwEoxnrxBu60?= =?iso-8859-1?q?nAaHHW14ipcroHefAfDR02zmK47woKYSQtLlTCZptWfl6jEoszhiPFJjHsCJ?= =?iso-8859-1?q?jgeV9xiGZqBkI/38/hb/oyAgatqF94AGR8NDRGJqNTbCX6Wkc8K9yRFsmtNZ?= =?iso-8859-1?q?lgW5xY79C7Ni97+I3JHbnZ4X1IAqeXgTYn4yf1+4xZ3n2soBOv2onfBGz4Jp?= =?iso-8859-1?q?bGMs1N5XrR8wTA1uRHNuHUOA6UHrbLZ5BsurDfY0g3WejFDMN3LppHJkyTCr?= =?iso-8859-1?q?IRr5u4nvjWKudJR4sZon8X9wr69uIJTD/gpNxUqvmaZKqpXfVi7qefm4jkxv?= =?iso-8859-1?q?QODo6iftyBQR65AP0Pr6IE32yZHkMb6wl15BDVPMcA9p5lgouVeKEVCwIpm9?= =?iso-8859-1?q?NZut3nnLparnNngh/lLGjAuonYaAp6KJVpCJI81WuGdoJxmxXbWQKq7nd8Tu?= =?iso-8859-1?q?61vGHVsKHlInthIKz2tYoUAq2nWsuFvlF4ZsHn+qwxkjNoYPzooCn7yy10ub?= =?iso-8859-1?q?bfKj1biGtWTVenBTP1qNDs9QotAlVi2IEopQLSU0vXyqFLNhU4HTvWyCAA/b?= =?iso-8859-1?q?Hl3M2e4b1myxyaz6ooB9vFDC8NbG1nEgwfqeXE17HAWyvIbptzl0C7Xg8ni+?= =?iso-8859-1?q?5G6FCj6Dg6LsDNhbh6w2wViIqFj/Ua20oUegNqddSTdcYX8oLbDLoQBpK631?= =?iso-8859-1?q?3qzEA16A=3D?= MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA3PR09MB8140.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 89bb30cd-c9f5-416b-9c36-08de9c7c6376 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2026 12:25:18.9333 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Oy/HvTM0V+cnIuVGg44czQX5LotBi13fKZVb3kRBT43sES1L/9EV9Fw0A3K8L3xQwt1WCZhRzCnUYhmdNzzdtE9TV8MNtnT+W6sF/MESYNM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR09MB6861 X-Mailman-Approved-At: Fri, 17 Apr 2026 14:43:59 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Chao-ying Fu Add a GPIO driver for the Intel EG20T Platform Controller Hub, which exposes a set of 12 GPIOs via PCI MMIO. The driver implements basic GPIO operations (input/output direction, value read/write, and function query) using the U-Boot driver model infrastructure. It maps the required BAR1 region via `dm_pci_map_bar` and uses internal registers to control pin state and direction. This driver is required for platforms using EG20T, such as P8700-based systems, to access GPIOs through the standard U-Boot DM GPIO framework. Signed-off-by: Chao-ying Fu Signed-off-by: Uros Stajic --- board/mips/boston-riscv/MAINTAINERS | 1 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/eg20t-gpio.c | 141 ++++++++++++++++++++++++++++ 4 files changed, 150 insertions(+) create mode 100644 drivers/gpio/eg20t-gpio.c diff --git a/board/mips/boston-riscv/MAINTAINERS b/board/mips/boston-riscv/MAINTAINERS index d03491d0f0c..8b95f53ab32 100644 --- a/board/mips/boston-riscv/MAINTAINERS +++ b/board/mips/boston-riscv/MAINTAINERS @@ -7,3 +7,4 @@ F: arch/riscv/cpu/p8700/ F: arch/riscv/include/asm/arch-p8700/ F: configs/boston-p8700_defconfig F: arch/riscv/dts/boston-p8700.dts +F: drivers/gpio/eg20t-gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0b5466b39b8..94d77c0e6a6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -762,4 +762,11 @@ config MPFS_GPIO help Enable to support the GPIO driver on Polarfire SoC +config EG20T_GPIO + bool "Intel EG20T GPIO driver" + depends on DM_GPIO && PCI + help + Enable this to support the GPIO controller found in the Intel EG20T + Platform Controller Hub. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 863557e45ce..729723bfe48 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -82,3 +82,4 @@ obj-$(CONFIG_GPIO_SCMI) += gpio_scmi.o obj-$(CONFIG_$(PHASE_)ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o obj-$(CONFIG_MPFS_GPIO) += mpfs_gpio.o +obj-$(CONFIG_EG20T_GPIO) += eg20t-gpio.o diff --git a/drivers/gpio/eg20t-gpio.c b/drivers/gpio/eg20t-gpio.c new file mode 100644 index 00000000000..18dc5214c43 --- /dev/null +++ b/drivers/gpio/eg20t-gpio.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#include +#include +#include +#include +#include +#include + +enum { + REG_IEN = 0x00, + REG_ISTATUS = 0x04, + REG_IDISP = 0x08, + REG_ICLR = 0x0c, + REG_IMASK = 0x10, + REG_IMASKCLR = 0x14, + REG_PO = 0x18, + REG_PI = 0x1c, + REG_PM = 0x20, +}; + +struct eg20t_gpio_priv { + void *base; +}; + +static int eg20t_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct eg20t_gpio_priv *priv = dev_get_priv(dev); + u32 pm, pval; + + pm = readl(priv->base + REG_PM); + if ((pm >> offset) & 0x1) + pval = readl(priv->base + REG_PO); + else + pval = readl(priv->base + REG_PI); + + return (pval >> offset) & 0x1; +} + +static int eg20t_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct eg20t_gpio_priv *priv = dev_get_priv(dev); + u32 po; + + po = readl(priv->base + REG_PO); + if (value) + po |= 1 << offset; + else + po &= ~(1 << offset); + writel(po, priv->base + REG_PO); + + return 0; +} + +static int eg20t_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct eg20t_gpio_priv *priv = dev_get_priv(dev); + u32 pm; + + pm = readl(priv->base + REG_PM); + pm &= ~(1 << offset); + writel(pm, priv->base + REG_PM); + + return 0; +} + +static int eg20t_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct eg20t_gpio_priv *priv = dev_get_priv(dev); + u32 pm; + + pm = readl(priv->base + REG_PM); + pm |= 1 << offset; + writel(pm, priv->base + REG_PM); + + return eg20t_gpio_set_value(dev, offset, value); +} + +static int eg20t_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct eg20t_gpio_priv *priv = dev_get_priv(dev); + u32 pm; + + pm = readl(priv->base + REG_PM); + if ((pm >> offset) & 0x1) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops eg20t_gpio_ops = { + .direction_input = eg20t_gpio_direction_input, + .direction_output = eg20t_gpio_direction_output, + .get_value = eg20t_gpio_get_value, + .set_value = eg20t_gpio_set_value, + .get_function = eg20t_gpio_get_function, +}; + +static int eg20t_gpio_probe(struct udevice *dev) +{ + struct eg20t_gpio_priv *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv_; + + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); + if (!priv->base) { + debug("failed to map GPIO registers\n"); + return -EINVAL; + } + + uc_priv->gpio_count = 12; + uc_priv->bank_name = "eg20t"; + + return 0; +} + +static const struct udevice_id eg20t_gpio_ids[] = { + { .compatible = "intel,eg20t-gpio" }, + { } +}; + +U_BOOT_DRIVER(eg20t_gpio) = { + .name = "eg20t-gpio", + .id = UCLASS_GPIO, + .of_match = eg20t_gpio_ids, + .probe = eg20t_gpio_probe, + .priv_auto = sizeof(struct eg20t_gpio_priv), + .ops = &eg20t_gpio_ops, +}; + +static struct pci_device_id eg20t_gpio_supported[] = { + { PCI_VENDOR_ID_INTEL, 0x8803 }, + { }, +}; + +U_BOOT_PCI_DEVICE(eg20t_gpio, eg20t_gpio_supported); From patchwork Fri Apr 17 12:25:44 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Stajic X-Patchwork-Id: 2224455 X-Patchwork-Delegate: leo.liang@sifive.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=dPJPSHbq; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fxvp11HCdz1yCv for ; Fri, 17 Apr 2026 22:48:57 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 21D3D843FF; Fri, 17 Apr 2026 14:44:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.b="dPJPSHbq"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B7878841C2; Fri, 17 Apr 2026 14:25:50 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazlp170130007.outbound.protection.outlook.com [IPv6:2a01:111:f403:c20f::7]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B9B7B83EEF for ; Fri, 17 Apr 2026 14:25:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uros.stajic@htecgroup.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oO+q4Z+e6AO8gGM+J0s57uljbtjoQikrNgA/PEQiaRKbNg8JxUvVAGdooDPfJmUiJKm1T+tnW0r7Rr485XJ2cXeSZ4bu1tcjodkYOTWE/eYWy+fK4d1hoQJ4IvgBD5hAWrZ8Ok6qt3ov0HcxGxj4XYf8y4z/vz/RRWYoO4dPXrVvZKT6AxeG91zgAhKoUeyabyjBd+Bu3vDoXcd6DMjUHhVwzOKh3ogN7m5GU0QmglDqzfiPxOopalX26AKQzrWSb5I90/BWbm2pxo5kLjt5qzwlGhpgcS/rgFYiFcWAW986I4S8oattAvgV68oOV/zLiwjVQ5lwwl9UOv8vnwALvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dJkuNUK7c62Zz4f0E16cS5K6MLL+EQNLk5a85VTvfPs=; b=doJL1yExvdGmh6+K2k19BGoItOJQmWr/9Yp1SpNDrbXaIVkp7q3Y+KsntzweMl3pzQPFIWp7HoRsqSBvaqj8HOmlXc8jAnoQCeEZy3x9UfeSOpoGuf5Wro5NMmIcOgiZvLsWnHh37PQ5hanurfq4eB8NHQY5FFNVz7uK+X9pvCHNofgjJnwWzCefeaApMnAxKm612gjsy2OjlOlOgq2saLypiTaDQw0R6eOFp8mEUpajn1oMswK3QLrOgV3d/njCWyuqJ7wJP3PLh4fbPRFqQxHIH9UlW7eZLWfoUdCu50PEbhHIbig+EQik/3pX3tryXTkDpogdv6xb8+Y/QUglFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=htecgroup.com; dmarc=pass action=none header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dJkuNUK7c62Zz4f0E16cS5K6MLL+EQNLk5a85VTvfPs=; b=dPJPSHbqPDtM8bb6SfSfT15K8jkLPfc4qEN90V/JgbpzLBw3qeyeyHLztacXkybPpA4vGVg7YZHK1GJ5zJjf0kY2hTVAe4pOHNPf2o4RcKfU4XMHBXXTSfZX+DWSMWvzSBKpZzYq29G7zmtMUH+tJA6bIt8hrYW0Rv8TwdpSrBu3CcxzwcDiZoq+2mq44U9H9ypkLHJsJTri36jzvFcKk3TR7sT3E9YYuVgEUMg+aK2icFb4gEIZuakIFoJkkd62e2j7Gdm/pBN9HuN0VsI+D0oDSSSaRilKbM6KRkdFiAnJFk73nDAmUkmrLp4LWljzJUVVEwqNdx/4QD35HTJzVw== Received: from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20) by DB9PR09MB6861.eurprd09.prod.outlook.com (2603:10a6:10:4c9::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr 2026 12:25:44 +0000 Received: from PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81%2]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026 12:25:44 +0000 From: Uros Stajic To: "u-boot@lists.denx.de" CC: Djordje Todorovic , Leo Yu-Chi Liang , Rick Chen , Chao-ying Fu , Uros Stajic Subject: [PATCH v7 4/7] pci: xilinx: Avoid writing memory base/limit for root bridge Thread-Topic: [PATCH v7 4/7] pci: xilinx: Avoid writing memory base/limit for root bridge Thread-Index: AQHczmVQpZzQnybCnkyO0mzqHW0JbQ== Date: Fri, 17 Apr 2026 12:25:44 +0000 Message-ID: <20260417122213.147529-5-uros.stajic@htecgroup.com> References: <20260417122213.147529-1-uros.stajic@htecgroup.com> In-Reply-To: <20260417122213.147529-1-uros.stajic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA3PR09MB8140:EE_|DB9PR09MB6861:EE_ x-ms-office365-filtering-correlation-id: 64b1228e-ca28-4772-9e1b-08de9c7c7290 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|1800799024|376014|366016|38070700021|18002099003|22082099003|56012099003; x-microsoft-antispam-message-info: NQM5xAsw0d3k6CRsdzx4Mcx28wVcPzt1QxIjPxxAqzHbmxU40/azWN7epw79oriq/czPJCns1HPRDmdzy6uO2EcNm8GK1QHMlA2R3jRr0Vu4Ncj772veFBs7BZYIJR1J3kN1VcnUlYI2Z+3kWiu/viInfD6df7PaB9neAxiBGMRBe/UW6ZMeMr/zq7dC1WSv4ZbILY93HjVZBnM1idGSdbkXCi3ozQoqw2yNEEUFRAWF4GyDtEZe14tabukxzxNfhGGMBg8/yy45kF14TGSSy8CsMa44nUuzaPHbUUjYHqiLzc+dLai9PEkexUBGt0brQRr2VZNC1U5wLBJFhUXTHhnkj7qy8lEtWsEaZwPcYdM5PLzdWGAhg1nBiyslO5Tyje9XnIbE19svlRZpm3o0rm2+IClqZf9snQGvZzDSgSpYC5xiTBwh5JHlwS4KEpo3ROQZaAS1fYUj5GoiTnn8RVVAEWQctXo6kMQJpEjz365m42jr3QrCC/tn+df2MYJeRjBi+0pMpxoxVGWXZmLwm+hyanQ1/ixUmSfhmssZFqPvpEfcAZDvfbaFiUlE65gk0YFdAYFwdeewPmynVmYM0tfN8yMVg7YETcNLT6xKTXDwTiv1nROkO/GCU0J4WXnFDg4ExRNOdoRSTffthrl3j9nfP5Xjgs1xexYm9jctX8rMzVFnL4LUz2ueZ0MKAaJDMRfWew555gapxvKdsHeySnTVU+MWTbzOcOgJpxcGhsz5OuJh+DdFUw8jFXyrM8c+dkRW5RvfJFDU8r4qjISkrn0gv6Xjo0U7Jq+JWIEzuTA= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(376014)(366016)(38070700021)(18002099003)(22082099003)(56012099003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?q?yHQD86hVbuzxlSNAdRdJJG3?= =?iso-8859-1?q?oNi4tdpfgl4niIZRBLS09j1uXv1YPXsxYDApu9Iwzq0ewjaN+RCktp2qyj2f?= =?iso-8859-1?q?lK49PYM0OCcuSe9Ricqd091FDXyEFLz3JsjUWJiXdXjFYTZjhf4JUqA/XHzx?= =?iso-8859-1?q?pDTx1eubZUgDcFy7Bx192lgj7JU0Lc4A8aEeWC+Te98rKKKBqF+wrX5GzmuJ?= =?iso-8859-1?q?Ucso6WP77AaKSEB0YvRYckihRmt9aRfNX/wqvhDI+QXTZXQKfk+CeYov8gGx?= =?iso-8859-1?q?aOEayWBg0P3xtsXYpuqD+wQo1zcG3aFaq/RtB73QNv1Fa98QLWAL5IxCfqKD?= =?iso-8859-1?q?v4INL7sv19zuJO/HuCj4vAXLG+AxGuG/fpQK10+7D882FpooRf+p06ZVz+cm?= =?iso-8859-1?q?WR3EgdBFw7uDbsDPOnwj0GDdIZn1IteKXemDR3CcOHHGC6a/XfixKma2ImRu?= =?iso-8859-1?q?FFJI75dgk9hiMzzwLvW4/77mOA9jtuGNQm0S7OyV8wS4GABt9usvVaR4Kh4K?= =?iso-8859-1?q?3eN4fKBZk2Dzzh2lekpoDAFWs1ZMpphxXx76BULc6yMEPgeilc9950OBtqYK?= =?iso-8859-1?q?3Nn1uDhzOpSh3xIfd9Qn+MLO5XV898k7FGsyGAfAZlBH+UmFB39E+sZPZyuS?= =?iso-8859-1?q?aTjj0es8bd1aqyK24T4tUCMLSzQPFJz1FbKNQRFF3BI8txCCwTxEi7ZXTPYZ?= =?iso-8859-1?q?2PFldoB7AT69EGy5AhHQkRc42YIqdMMAPPgwFqAMwlRJCNdZPg0FjM9ckle8?= =?iso-8859-1?q?YtYUMgXx6MUd4bZiItqPCQpts4uLKk5U1ZjxSawQhJaIxXd5FTPVtX5j7rIx?= =?iso-8859-1?q?hBq644i6GsAIoBakNssfJa5r2FTW8s6LJEJS9JR2NEkrCFCv6hSmLgbarJhU?= =?iso-8859-1?q?xVIwaPA/YV08zY7wIWhPpN5Fb8B3cB45bmR9YvDCeei+RT+LPLjzWXUNozLB?= =?iso-8859-1?q?qf5cgjc1SwfqjRzrmUhnVhApBdkXt2lAuJIssNI9WcH/f6VzeEA2ddlTPzwz?= =?iso-8859-1?q?p6cfvdubE4tWdYA5wNrHYcUXBTTybuXdKj8zwAtOnISgkDI3g1Dq3JVTVALd?= =?iso-8859-1?q?vSjb0NIBxuULFLOdlYQ3zScG34LMzoZgpV4dymXVTIxcMuqhJAaflrdzN4yD?= =?iso-8859-1?q?CmtClu8MnNQoqPTYY6yRtwRRJwsIJMO+VFmMM8Qq0ABPEDi9pKtDcSajDXlX?= =?iso-8859-1?q?ocSn3hHd4pBuupqAcKks/FdUYNVqPOISun3AFzaAipFJmwsS4YCXLe7dxUzO?= =?iso-8859-1?q?f2TuLQyOwhoiPHkrKGwMZTH7dlpvK5Vk5BB+rbckLTRfNGabXvd8kaDzX7cz?= =?iso-8859-1?q?VcRsE25bqj2kDYG7bAy2VhBPybw8ii23DEOJ/cTO2O/CDs0rDrqufRqi468V?= =?iso-8859-1?q?eSwX9WUfTsR+LLycYmf9EQVyEdzCnrFXyRxleDMWLmgUHHtfGbPX5QLmzUPF?= =?iso-8859-1?q?zjouIvGL5iaJuVYwLDjxvsNrdvj3UM71qTDhN8vm/k0A96y0+vZwjCW1szn2?= =?iso-8859-1?q?vhhec/hZBmHlKLGGfbaJGNlD7dv1OXX6VgPXCD7/bgmwPvMGXp90Rs42DDlX?= =?iso-8859-1?q?Yc9gbHn1Pkbhy4OhtT8NoT366uiFBnAYJchQrU/tC9LE7b6CXi3qz8pez+NF?= =?iso-8859-1?q?aXbSGagsAk9xRq/esVhKsPasga0MUt8JXBx3Kz1sPh5/Hl/ie+fbLCv/ctYJ?= =?iso-8859-1?q?R+Hc4CsNOoBdAw4CalTtGdVYhDMJRdr4h04T1u9+rf7AGybvFTYXh2HJAmO7?= =?iso-8859-1?q?xtK6Ra6EKnRM9lBvitAYtrMCtIPZu1etwFGrfcGYtqOaNDDNtUU4Bpz27FeS?= =?iso-8859-1?q?DRcONyyA=3D?= MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA3PR09MB8140.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 64b1228e-ca28-4772-9e1b-08de9c7c7290 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2026 12:25:44.4667 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LQfaAYkxPlAQeG8W1/85ks/mjYJmIo+/UsHzYs5EvK6QREh2vHxFJ7VIpgBGmn1PHkypcT1UEVE22Pk+iF/zPYCMKszrVEAcSikp3zRq+XM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR09MB6861 X-Mailman-Approved-At: Fri, 17 Apr 2026 14:43:59 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Chao-ying Fu Avoid writing to PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers for bus 0, device 0 (the root bridge) in the Xilinx PCIe driver. On platforms such as the MIPS Boston board, writing to these fields results in incorrect values (e.g. base = 0x0, limit = 0x1600), which causes Linux to fail PCIe memory space assignment. As a result, Linux can boot successfully and probe the PCIe bus and all connected devices on platforms like the MIPS Boston board. Signed-off-by: Chao-ying Fu Signed-off-by: Uros Stajic --- drivers/pci/pcie_xilinx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index 63058e8e7c5..4ef20474a0b 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -132,6 +132,15 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { + if (bdf == PCI_BDF(bus->seq_, 0, 0)) { + switch (offset) { + case PCI_MEMORY_BASE: + case PCI_MEMORY_LIMIT: + /* Writing the memory base or limit causes problems */ + return 0; + } + } + return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address, bdf, offset, value, size); } From patchwork Fri Apr 17 12:26:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Stajic X-Patchwork-Id: 2224456 X-Patchwork-Delegate: leo.liang@sifive.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=kOmmOUkW; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fxvp974nJz1yCv for ; Fri, 17 Apr 2026 22:49:05 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5DCF58440E; Fri, 17 Apr 2026 14:44:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.b="kOmmOUkW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D577D83EEF; Fri, 17 Apr 2026 14:26:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazlp170110003.outbound.protection.outlook.com [IPv6:2a01:111:f403:c201::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B38F6841C2 for ; Fri, 17 Apr 2026 14:26:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uros.stajic@htecgroup.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=qT1JAstbVeuXcpQQfq3t+AIY1SlBL4AuxOE8wl7k5yNxsUxDFSo8uphcUVeSBMjxbmsDG2xozISmjJYB/FAbKuW1PpWXdUpUlyYQEDcCMykKrKbfhvBAnAcrxdvWYyZcTIkFcWznAwSEEYxrMpG/WyTldzfxkloN/Kwo8Qc1j7FYIc8JXBtlyld6qxpfKcGUHFd+/1Bc5cQdWdzQPDsaN5qrMe5dZ+JlnF5qXTa4LZNnPFMOa1kD+xxjbhOnF+Lh5NV9qeaeWtB87PNq0MeJnmankPUUqe3cPezMtta8j66RTiPgr3wv94O4vU8wh3S1oPFtVJ8NX+z8jdTbKjlvCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SzXuN+l0kB3XarvRYMb+1Ko7WA04I3MGfvCVezSGppA=; b=Klm9o69dJYnNtes2VMkebKmZw8X/H6H8LthatvzA60Z0eHjAodnKQbQasYT/WDKXVJ1ydiMVGkWQlhZnStwSaSunRR+Im+s9PPRfMyTBQSQgiq8rjF2x99aTjBjdMdtD6WO7U0rWZaAluihe5QGc4jLBKxpFMGZjyJr+L+/O7IReN60VvbtTOT1r/l0fAGjaWkpdHD5RKBgd8nVlWsMEVlqMaPTV3Lv9Rd6vIrbDIy5SvlpBti1e6CWJ3O7KQuK+zsNclFLA+zHAlehM0ElW8CrCd7qfFWLgEdQpxn13KDX0Pekr4dZQM5lXSeokQPR32cXq3bVbhS0prJC6aGr6Cw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=htecgroup.com; dmarc=pass action=none header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SzXuN+l0kB3XarvRYMb+1Ko7WA04I3MGfvCVezSGppA=; b=kOmmOUkWVMVOneLVHQCLjjvRtwJ4YaBVniWKgAuXyjhMDSmIWvOQPlSsGoD8XQcb9wWdUef+ENWQ8M06hPFZx3uWagKi/5UYXVK+Pb/uQQC+ys57Sk5Qq140Ge/aybaDYRG2/d9Sdp94DWqq8fM15QkX7E0Y7vMTIw8OQiSsUEY2Jh2cPXsRDFB3S3zXFXR9nIhpnfrf8uO2ug9hpXfVu5JMND83URGPMSMULtW7nPnqiMuOobN4eV6LhrVsWAW3TOi2BiecqQgKjOiD1wo/G/hwhKsswSMyhzEg1eeIEnCAWW4tN955V3i1a+GS8mvLsyqvnMG7g7Z398zPcSf+bw== Received: from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20) by PA4PR09MB4525.eurprd09.prod.outlook.com (2603:10a6:102:f1::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr 2026 12:26:18 +0000 Received: from PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81%2]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026 12:26:18 +0000 From: Uros Stajic To: "u-boot@lists.denx.de" CC: Djordje Todorovic , Leo Yu-Chi Liang , Rick Chen , Chao-ying Fu , Uros Stajic Subject: [PATCH v7 5/7] riscv: Add syscon driver for MIPS GIC block Thread-Topic: [PATCH v7 5/7] riscv: Add syscon driver for MIPS GIC block Thread-Index: AQHczmVkE0ki6d98zE+BpmVmcYYKQg== Date: Fri, 17 Apr 2026 12:26:18 +0000 Message-ID: <20260417122213.147529-6-uros.stajic@htecgroup.com> References: <20260417122213.147529-1-uros.stajic@htecgroup.com> In-Reply-To: <20260417122213.147529-1-uros.stajic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA3PR09MB8140:EE_|PA4PR09MB4525:EE_ x-ms-office365-filtering-correlation-id: 531f6abb-6e30-43b4-c1f3-08de9c7c86bc x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|366016|1800799024|376014|38070700021|56012099003|22082099003|18002099003; x-microsoft-antispam-message-info: uOlfdfPBpTx6XH+qIe868ATW2nEi3zeHC2X8zQHb05YW3yh6QdJaGyQ/6dKmRfGzFvYkon/6OWRK/JPqdh35e6VNJcKlUW2jfZIZVEGJXwizj/JhRw6c6ZMWhscYd9QSTXVP+Q9q0OaPHEGugDvWeEF83mmmoa89IkZ+vPz0FEuOmHOYGn+EiEOUffdiSnz4j9i5L1Scie/5JKQXCZzlPnA2gEIHQrzTXQ5avBt+mCMbzqBxmDXpnMmpEdlvXzZMgYPFY5ZOZ5Er/cvUBo1VzmJPUBS2XvSB7ydT6xO3E2Saz5DBR/ZCyJFGFdz0LwO12VjsZHNbYWH2rcS9I/0xl0K+KM4m6i09K59MxxoxhRKQm6aGb7yJaAi+GW53wrpvfQ6YPv7lLE76+7//+MljCN8Niui2qCnx7XLGDf6zNMTbctll0YZ6QJw723d7DUE9WidrrvwMmo4dwxoQNRvQDDu16vjIx56mFvpvU76RzRuVENaB0zjsmCySG+l09LJs5SYF30rbDuMYYkwbvR8+vJcqEGNv4XD3xpszkPcySEbhVpqBRNnYw8IurOuTQmodtbcIoDxiwUG4XeuWzEyr25UQub5jHr0p5Bn9e+RfyKJLq12p9/oQsDLEotgD5275pGINtdNYfXH4shG+dVkiJV/FLcUlYN5YmZNmufoubFBQQ4O2k3BsixFSYesfmk34oHBs8Hc4Ca6NLnhxjiBDMWUQ6SH9GLoNG4OTekwsVf3tmoKfbhfWL3oG59N1lKTqR/+vi4PN4tnKOJGG6dZWLR1IbPITK8sflBywI69jbUA= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(1800799024)(376014)(38070700021)(56012099003)(22082099003)(18002099003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?q?+NUVc6dY2OYSjDjecdd5gfV?= =?iso-8859-1?q?AaOCkqAlGp7rOYtF827WBx41ko0X1MI9OZRXF158HGIqiWCQIgDZHGXlcOsj?= =?iso-8859-1?q?edXuhpmxJRtowFOLX/LzNwLYZg3FVPktJzRGs7T0gnr5X9S5D1/eybuWRExS?= =?iso-8859-1?q?YoYhcXOFbUY8vm0iNhnHp/PCGMLlwllw+T7iRcQ1Tt7FPuTyClinYAYT3g0K?= =?iso-8859-1?q?yXMUQh7vVRbrUiROgTEEDCKoRxILBIT6A768y90/WgYZffq54R2Y13rv07ay?= =?iso-8859-1?q?4cGgYHa0B99F6NlUU0AcGfSIPJ9ANbczuya69HotaJnFK4geqJe8RSky2WYN?= =?iso-8859-1?q?jysp/rKZKJUdEZIBoCzmHHxDBKEM4UbA3Oc+edv9zt17t+gXnRK5PHmHrWMM?= =?iso-8859-1?q?djRFWzMf4o9c2eZvQMJIKtweKZdth5wTqu7ep9ZeVsrekAfvQrT+NPitd41T?= =?iso-8859-1?q?0f80j2tZB3ODL2154i+Thoacx6sU2wWZDiexIjEGXAcDiLLicwPDJx00VtvB?= =?iso-8859-1?q?ILtqxLldfwwerpPSmii4fpcWzNMuQw5iNfqqO9TTgH6kRHVcmAQl1qgSSpkd?= =?iso-8859-1?q?T3zQTLFd9aw3OE7H73ccqQhRj+qpOuKJCSn9R97xbdJT/3lHVKo+I+CQzn+0?= =?iso-8859-1?q?y3fZgWAmhCkgrLKeg/ygfqwewv8Rd6Jt5Tp0Xz1KMu9EZrykF0I0bMpn39jK?= =?iso-8859-1?q?cN+kJp/IioT0AgQ6/4vnXuc3MoetJAPOgTvuH7urCHIBY/hkcIEnYn7djRaV?= =?iso-8859-1?q?3OtG1bgF++tteinxV4aKxQ5bktjTPf8fVuWDVOaR/VD+A1acL3YQZ77w9hOB?= =?iso-8859-1?q?V00IVFMEp1d3rJBzwmpC9ycrdmPfpQ98kgq6xKQC1BCk5WG5LmKEN5egWMK3?= =?iso-8859-1?q?1iwdGOb7HJhm6VXlkiVM6vaO7dC7m3RDlSextUTNuXQ861gu+wpf027XS0NO?= =?iso-8859-1?q?8Ui1nP0KcQJqEqpLK0M1mQhZVwV7a4p0AAawjYN/IERexar/NZJPtd/vzFOv?= =?iso-8859-1?q?BbnH2zY5ro7O7y+tj8FgY8f3sYh5hovIIHFhp2L2AI8+RKwKD9MzNl9bN442?= =?iso-8859-1?q?FILZFDmNwzNm5Ew4pRI8WUtiuxxr7KnL3hydPd4vmU3ZvaQJP5w9I0fbhb7F?= =?iso-8859-1?q?4MAGBkoOWHGH14HklKY/FX5DC/I2pfSVF5MpTbs4TnLpjLfVGnUIEwMBTOPa?= =?iso-8859-1?q?rBAWwA4xQKfiO3Uq8DPVTWHSNSspZBhfQvAX6ShB/hmKNOqgqf1ICxaq72Pd?= =?iso-8859-1?q?pDZ/7w2rEN+2Flh0PSoFDRzIZYoBKFEa7ZGi6hZ4zp7gNWE0GCZiG0wStJeQ?= =?iso-8859-1?q?m+bsTC4qz1bbV2a4X5s5vRXO9BirT4/qU+O7oMfcbMxIeQUVWgciPCYdHNpw?= =?iso-8859-1?q?OZOfQOrTOcRUMgBnGYGwXyvru9jYQATxd4mq5LGZArH3bfBYtY/QGpRMioM1?= =?iso-8859-1?q?frL6dgFWLLAYDPwPirIsOt5glwnBriLzh38ObdLpfJAKGlzRJfRlVfPEIV2I?= =?iso-8859-1?q?o22jpah/f1P3rptK/IrJF0wlGKNNpfnhv8JlsACJ5YARAD9Sl/Y1McO+mUeu?= =?iso-8859-1?q?ti/6swO5Y+UXP0Ee1m5Emcg5mfHx7GjYFr3TG8Y4UBxi7atZkF9lsORj/fpA?= =?iso-8859-1?q?FcbKSpRRqgGVL2fjKWOwxe425VT5nzscSUzccVroir5CVbVqgHPpJ5iGax1J?= =?iso-8859-1?q?og9XTPISQyy120FAOiQaNLLSXspKVc4quG4uwv8e+2ULi+zpVh1lWVlaqANm?= =?iso-8859-1?q?v8oKUzw0EpxRIFtvmci5XFPlaz16/VhnJRKWwaVzBNnAKvN96zv+fDUPQr65?= =?iso-8859-1?q?WMGtIIxU=3D?= MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA3PR09MB8140.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 531f6abb-6e30-43b4-c1f3-08de9c7c86bc X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2026 12:26:18.3534 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cH9pUQBc5d2RkwYDxdgNWGrvVNKjYETYXWOyx1E6Yqm4frwfNZ1bpdh9AMstJsBvfSqo8sjwbq2vBliYjIUNCtj2c5q1pq8OC7ULqJhz4lc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR09MB4525 X-Mailman-Approved-At: Fri, 17 Apr 2026 14:43:59 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Chao-ying Fu Add a UCLASS_SYSCON driver with DT match for the MIPS GIC block, so it can be accessed via syscon/regmap. Signed-off-by: Chao-ying Fu Signed-off-by: Uros Stajic --- arch/riscv/Kconfig | 11 +++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/mips_gic.c | 47 +++++++++++++++++++++++++++++ board/mips/boston-riscv/MAINTAINERS | 1 + 4 files changed, 60 insertions(+) create mode 100644 arch/riscv/lib/mips_gic.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index edb5e6da10b..df2f4484b00 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -412,6 +412,17 @@ config SIFIVE_CACHE help This enables the operations to configure SiFive cache +config MIPS_GIC + bool + depends on RISCV_MMODE || SPL_RISCV_MMODE + select REGMAP + select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL + help + The MIPS GIC block holds memory-mapped control and status registers + associated with software and timer interrupts. + config ANDES_PLICSW bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index a527b3e9ae3..f0f5e40a20b 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y) obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o +obj-$(CONFIG_MIPS_GIC) += mips_gic.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o diff --git a/arch/riscv/lib/mips_gic.c b/arch/riscv/lib/mips_gic.c new file mode 100644 index 00000000000..7d761c58e74 --- /dev/null +++ b/arch/riscv/lib/mips_gic.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Chao-ying Fu + * + * U-Boot syscon driver for MIPS GIC. + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int riscv_init_ipi(void) +{ + return 0; +} + +int riscv_send_ipi(int hart) +{ + return 0; +} + +int riscv_clear_ipi(int hart) +{ + return 0; +} + +int riscv_get_ipi(int hart, int *pending) +{ + return 0; +} + +static const struct udevice_id mips_gic_ids[] = { + { .compatible = "mips,gic0", .data = RISCV_SYSCON_PLICSW }, + { } +}; + +U_BOOT_DRIVER(mips_gic) = { + .name = "mips_gic", + .id = UCLASS_SYSCON, + .of_match = mips_gic_ids, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/board/mips/boston-riscv/MAINTAINERS b/board/mips/boston-riscv/MAINTAINERS index 8b95f53ab32..47f2dd180b7 100644 --- a/board/mips/boston-riscv/MAINTAINERS +++ b/board/mips/boston-riscv/MAINTAINERS @@ -8,3 +8,4 @@ F: arch/riscv/include/asm/arch-p8700/ F: configs/boston-p8700_defconfig F: arch/riscv/dts/boston-p8700.dts F: drivers/gpio/eg20t-gpio.c +F: arch/riscv/lib/mips_gic.c From patchwork Fri Apr 17 12:26:53 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Stajic X-Patchwork-Id: 2224457 X-Patchwork-Delegate: leo.liang@sifive.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=TiuFOCor; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fxvpM1fptz1yCv for ; Fri, 17 Apr 2026 22:49:15 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 984278441A; Fri, 17 Apr 2026 14:44:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.b="TiuFOCor"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 092CE841C2; Fri, 17 Apr 2026 14:26:59 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from MRWPR03CU001.outbound.protection.outlook.com (mail-francesouthazlp170110003.outbound.protection.outlook.com [IPv6:2a01:111:f403:c207::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 08F2C83EEF for ; Fri, 17 Apr 2026 14:26:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uros.stajic@htecgroup.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fzQVJSiTwF7vxjRQXwHzb38OyDAVM2nJYxHhGuImCi6qtLZ4xChQUnPImleK6yvISTHg2uO1jDQSpUeBEYzvWDL9DpcJxYDAGhdXGZE1/0wkDJGAVvwTBA/0GvfRvxzTjYvyCufgeBGHhkqYdTaTr4+qmAa8nOd1cW4HxV+aMU/zoKrqH01mhmn/MLvhXHpSIESfjF6OWfubaLhMRRYChxYBXOWLvt2l196zFFvmemi9LX5ZBTA52QHXv5HFxsjKYgrydB/RE3X+E547pR3xOKDLRHOakS07E8+BhhQd4DaMkLFAKNyMkvSTNFF2iUiLeh6uJQaDXILdgim9/Vladw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X6V4qRQCDqTfY4t1bIpU/JnrDc91aC/XNAKl4T/VxVQ=; b=ZSjrIsvujctl83cf+lp1JVKNOB6vcsHHlMGeeWC9pkOU08E8UPd+qgkKmbkrN/RkBtbuZvYg+J0eLbbWjj8GRrxIPIu3p7bI1S4jgEa/4aFSLodlaXxqCL+SMxiV35/TqkZToI1QoHjrrRM9swFTgVbBmZBMYGczvlWo1CqV5fB57fGWTI3GzEpHi8i+GF960sIRA2KwgZS9HcyBEXC+o4yTW8Mu+M0KoJxuX6H9BACAIxX6L2NU53SMfcejtzJ9cCFRgG3x+0761rgNaTS3WHKnRMxnwOvRf2xZsJ+bzDX9xUQZH/3CbAYdsIS2ccygmvgoHPUlV84AuoZn3GFUIg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=htecgroup.com; dmarc=pass action=none header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X6V4qRQCDqTfY4t1bIpU/JnrDc91aC/XNAKl4T/VxVQ=; b=TiuFOCorsuqA25YtlkMgwNDzZef6/4tg9heDPq1a4h/8v3q7pnt+XED96+v5+qHVF3aMvDhILpvaC40qWl/GYtYKt2nWsQ3lbL+Qc6kAuzFXisH4/jnbTnhqM4q228emQaxxaVqQQd1VA2O/XHaoI4HUiJFCPGvYBocxaCnOxgSWnS6BPYablnNuaQQKu+J5ZIjDFbRYK/a8wC8CW8G1tKsyPr00WgGPNlmnyq5+A881/klovG2dkPTQt+64CFp/5E0gVvh/0FB7edD4sDYWtJfZJNbGo4EKC7tkVInZh+loIShtgBuQlRtO8AbAYNX+jxObMuUiBeQ0oKi9rjcavw== Received: from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20) by DB9PR09MB6059.eurprd09.prod.outlook.com (2603:10a6:10:3d8::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr 2026 12:26:53 +0000 Received: from PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81%2]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026 12:26:53 +0000 From: Uros Stajic To: "u-boot@lists.denx.de" CC: Djordje Todorovic , Leo Yu-Chi Liang , Rick Chen , Chao-ying Fu , Uros Stajic Subject: [PATCH v7 6/7] net: pch_gbe: Add PHY reset and MAC address fallback for RISC-V Thread-Topic: [PATCH v7 6/7] net: pch_gbe: Add PHY reset and MAC address fallback for RISC-V Thread-Index: AQHczmV5YUFfYrhlr0qHd0EfcBT0mA== Date: Fri, 17 Apr 2026 12:26:53 +0000 Message-ID: <20260417122213.147529-7-uros.stajic@htecgroup.com> References: <20260417122213.147529-1-uros.stajic@htecgroup.com> In-Reply-To: <20260417122213.147529-1-uros.stajic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA3PR09MB8140:EE_|DB9PR09MB6059:EE_ x-ms-office365-filtering-correlation-id: 0a79740a-33ce-4126-9c70-08de9c7c9bd8 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|376014|1800799024|366016|38070700021|56012099003|18002099003|22082099003; x-microsoft-antispam-message-info: xKsdd//KmI6iXFiK56AFxczhrCz8MFsW90uVwywBS7a+Db1SJiFjK9U790N+OAaNhwES9oqi8V7NvDLfU4ZXUIMsBesyKTU5QciDBTimInpWx9PAlYfd/SjNx5vBd90Y456pjaWKZecvXvkp2+du4wgu3lwbXGhJl/PVI5AxSTHdeobq6TMIE9ur99UiehGjhZDAPVHQUHnNhoEjE6qdUFOySRqkrJBFCkLpKdl+qBN1fPZsnLytZyHLbeV7gPwM/7+KxmKCdP2Yo7/V0wwIRI04lvUa3zkwu6m48NAtRX6Wjx7ZHstxlx+IjX6Ligrcb4de20sRIjaIaDyBuxlj7wau0mZMox0X6G/Pqj7q5CNlkyfHCHMY6H93oEys/PDh+LG3g4cInEdpGgPNc/6uJ+5XEwqPTKQ14M+5kM6a+xFqVQSkdStYI2mpGRVoVOp2t9bblu06UhbcOVN36gERpAP4JTclAk9waVVFUXmkvIKPt3l4T0YUbzI9F5cW7lcfTujsPAJE3rfni/5ARtSw7325s5qyXCOwFSmiBeG9lQ1J7q4NSN8NUgGIPb1cAnqPzsplEFwpzNqLvpe743OvXrqSXIzrL8M44k8/nSTw7uZRiM4BblTTw2G9ePZNJbSUogCkDzPjSZFvKawq9andKSdNPr42qXzCFokSi3MQABn6fg0qsK6DesWCzIzd4DZCb8CQBLXXdROgiy0TsUmDOMFu7j+4h10xHiHvTxiHIYDpyIQaTAXUSu1Qyys8rO8HOFB1cwC9cFSrsYbhLJ/va7/kTnSBw79A6bDFXfUit6U= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(376014)(1800799024)(366016)(38070700021)(56012099003)(18002099003)(22082099003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?q?7WtoJe6dLWgbh4oUNdthsMl?= =?iso-8859-1?q?gol9ekIW3XSPtfWkmBngZGu0+9stCsfTZoTjLUEI7tt5LQq1Rdb2UB/grcCu?= =?iso-8859-1?q?bkztQSv+o2Y7iEd/P3lPWI6wTzQEOBcafQW+Uuy9viazKWKixCyBVOzTSPgq?= =?iso-8859-1?q?O53b/NMS7OhWdZ/FnckM4Zp4X7x2qOLOFVd98zHNe4aXoecfhkn23fkQUGn/?= =?iso-8859-1?q?V29Uq4uB8s4p6QnwmkWE2/HglFha0poVC7n9pY8pP46SGL/O/tlnxlt8+2S+?= =?iso-8859-1?q?27I+sFlBfP0UN1zhrDVTPUkzYekPYraEVXtGiCvTlP17zn5T4uQaiTHOJ95O?= =?iso-8859-1?q?5VRDYt6hJGU14FHETmI5F3UfEUTFTWqYul2u8YtdoS3tFdqRSz8muynEBtuO?= =?iso-8859-1?q?FrJ5hDa/5WjRcEnTNLK+pFc/6/PPFQRsSIkoIypJbSGQ4dNN13rJ/FZffJva?= =?iso-8859-1?q?46vAQ4vyLPdlQTFuCN6WahHzDZwEgJxVvV+xLic9y6181LHDIi8rFlF7DdDU?= =?iso-8859-1?q?3KMa8Vc56/a8MlY66fdAZ7qzMiCVhCALx7ZHp7zZHsJ7GZn5xvI5ZY4w0Sg5?= =?iso-8859-1?q?EHEWchXh1nhSWud6XnLUfA3XOCZQjp+eeTKfLCdUFYeYW7DoxZ1niIE8WCee?= =?iso-8859-1?q?9kEq9L5Rlo4A63HK9zSM5mwCpqy+7019aa9X1jHrkXNa4hQK+90t/quu/xf2?= =?iso-8859-1?q?om+2jw0qLWOGumDQtuyZ+r8otlnv3oY0aNpAxwuHwleiDI1hrA0KyEWDJGnL?= =?iso-8859-1?q?ZLC/LJXeM9OlcVIqCrjXFARMPloq9hBbMg8zzHq60zaXpoFXWQrEkWFmWic/?= =?iso-8859-1?q?TjnsqS8OENRcAqwViZeGkOcrb3n6EIErE73iF8uGOFR8jyH89AhAuONF8rq7?= =?iso-8859-1?q?PZcsGDdsQThDlox5U889HrfDHYqfYGSqzfV+cnXpkdJ/s4VuTR96RPmarS8T?= =?iso-8859-1?q?1fhFgBKDqM3tHpSvBcb+NgO8pDsSc3VjCya/T8RlVHV2XJOMqtgLO4hhDf7X?= =?iso-8859-1?q?Wx+bCDm1TT70Oe4EN6a3gI52GCwOD+d178Khjr5Ud6aqWF2C0Tq6HnbNGznW?= =?iso-8859-1?q?siYrBYFkZEe7LbXQbP4wYm/1iWZWY1rVgaNncXEE3vvraHUkba98QibHLWaJ?= =?iso-8859-1?q?x6C3ImZ27TWXgrbZdL4DSo8JeQe+yZRsridNxH+8/Ds6fgcvbLhrAr9pl25z?= =?iso-8859-1?q?8f+SZoZ6wX8JLHBBQrOnySMmP3WMKe1CSN9QyvGDxjN/JIZJ0BqMnDxlBaMA?= =?iso-8859-1?q?z2jwbgzAbinBmR++gEz/btHNKMdD5Lt7Oy1kLibE5/gRKoTi1zVGA+3eyfGZ?= =?iso-8859-1?q?oxtPBCXC3EP0F+qGNpNS1Fusf1f48M2Wl556/cy7e2KzapEXJWz3IPB+YFmS?= =?iso-8859-1?q?FimYL2AxcQIOktfpJaxJdPv0xe1XvE+AOCztUXw4PrAavyMzhnSaFg9jS3bi?= =?iso-8859-1?q?4hgdXUc309bMljZ2/j0oHNGzH0X47Lb6aqzfB5GtfBVG0sBjV3DVOiIH0td7?= =?iso-8859-1?q?VZ9n0Uo2j0E9SxUsv9ugRAfuiSf8hMtOIbywQMFYckfkc3JOTrhY7AF7ClYa?= =?iso-8859-1?q?O+0rdKIJlxBqdBE+2sCd63Ga+UCwzLbsQ+xHIw6vnq1EtTdXcDav7sziSqRe?= =?iso-8859-1?q?V/AOBcfr4Rq/WxlnC/P1pVIcFP+27VKVJmWRFBk1JphG+r643u2P0LA8EUyG?= =?iso-8859-1?q?307paj8jDo59qIyImcUCC8WX6wQ438gRhGnpYvOjtss9wUj35J65j7AOsNUf?= =?iso-8859-1?q?3+QmXGHma4Y/sfB8lZC7rH8L3HfeAgA6bm3cgDivFWaAjzgPiP0MTZYH6Ali?= =?iso-8859-1?q?zmRjqiR0=3D?= MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA3PR09MB8140.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0a79740a-33ce-4126-9c70-08de9c7c9bd8 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2026 12:26:53.7490 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jhcD1IZ0kJh4OeshwJbtRqVyQ9mdsXha8flmLMQk3ltS1/uE9dmt/BSgbYuAMnJE5XSOHq8Jw+C6cC2SyjYodZEZBL96qQLAykGy3sbTSX8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR09MB6059 X-Mailman-Approved-At: Fri, 17 Apr 2026 14:43:59 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Chao-ying Fu Add optional PHY reset support via GPIO defined in the device tree. Improve robustness by handling probe errors and falling back to the environment-provided MAC address if no hardware MAC is found. Signed-off-by: Chao-ying Fu Signed-off-by: Uros Stajic --- board/mips/boston-riscv/Kconfig | 4 ++++ drivers/net/pch_gbe.c | 37 +++++++++++++++++++++++++++++++-- drivers/net/pch_gbe.h | 1 + 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/board/mips/boston-riscv/Kconfig b/board/mips/boston-riscv/Kconfig index bada4b6752d..f11ae736db4 100644 --- a/board/mips/boston-riscv/Kconfig +++ b/board/mips/boston-riscv/Kconfig @@ -40,4 +40,8 @@ config PHY_REALTEK bool default y +config TFTP_FILE_NAME_MAX_LEN + int "Maximum length of TFTP file name" + default 256 + endif diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index adeca3d040d..380dc339e50 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include "pch_gbe.h" +#include #if !defined(CONFIG_PHYLIB) # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB" @@ -33,6 +35,13 @@ static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr) macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff; debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo); + if (!macid_lo && !macid_hi) { + if (eth_env_get_enetaddr("ethaddr", addr)) + return; + + printf("No MAC found in either EG20T H/W or environment"); + } + addr[0] = (u8)(macid_hi & 0xff); addr[1] = (u8)((macid_hi >> 8) & 0xff); addr[2] = (u8)((macid_hi >> 16) & 0xff); @@ -74,6 +83,14 @@ static int pch_gbe_reset(struct udevice *dev) priv->rx_idx = 0; priv->tx_idx = 0; + if (dm_gpio_is_valid(&priv->gpio_phy_reset)) { + /* Reset the PHY */ + dm_gpio_set_value(&priv->gpio_phy_reset, 1); + udelay(15000); + dm_gpio_set_value(&priv->gpio_phy_reset, 0); + udelay(5000); + } + writel(PCH_GBE_ALL_RST, &mac_regs->reset); /* @@ -450,6 +467,11 @@ static int pch_gbe_probe(struct udevice *dev) plat->iobase = (ulong)iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; + err = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &priv->gpio_phy_reset, GPIOD_IS_OUT); + if (err && (err != -ENOENT)) + return err; + /* Read MAC address from SROM and initialize dev->enetaddr with it */ pch_gbe_mac_read(priv->mac_regs, plat->enetaddr); @@ -459,9 +481,17 @@ static int pch_gbe_probe(struct udevice *dev) err = pch_gbe_reset(dev); if (err) - return err; + goto out_err; + + err = pch_gbe_phy_init(dev); + if (err) + goto out_err; - return pch_gbe_phy_init(dev); + return 0; +out_err: + if (dm_gpio_is_valid(&priv->gpio_phy_reset)) + dm_gpio_free(dev, &priv->gpio_phy_reset); + return err; } static int pch_gbe_remove(struct udevice *dev) @@ -472,6 +502,9 @@ static int pch_gbe_remove(struct udevice *dev) mdio_unregister(priv->bus); mdio_free(priv->bus); + if (dm_gpio_is_valid(&priv->gpio_phy_reset)) + dm_gpio_free(dev, &priv->gpio_phy_reset); + return 0; } diff --git a/drivers/net/pch_gbe.h b/drivers/net/pch_gbe.h index 7e0fdbfd5a3..dcbb94094bc 100644 --- a/drivers/net/pch_gbe.h +++ b/drivers/net/pch_gbe.h @@ -292,6 +292,7 @@ struct pch_gbe_priv { struct udevice *dev; int rx_idx; int tx_idx; + struct gpio_desc gpio_phy_reset; }; #endif /* _PCH_GBE_H_ */ From patchwork Fri Apr 17 12:27:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Stajic X-Patchwork-Id: 2224458 X-Patchwork-Delegate: leo.liang@sifive.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=LO6hDpa6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fxvpW6p0gz1yCv for ; Fri, 17 Apr 2026 22:49:23 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D507D843D4; Fri, 17 Apr 2026 14:44:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.b="LO6hDpa6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2C08384214; Fri, 17 Apr 2026 14:27:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from DUZPR83CU001.outbound.protection.outlook.com (mail-northeuropeazlp170120005.outbound.protection.outlook.com [IPv6:2a01:111:f403:c200::5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DA26E83FC0 for ; Fri, 17 Apr 2026 14:27:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=htecgroup.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uros.stajic@htecgroup.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OO7i7JUpK5LJVuNfNF2nn2R0uOujKOl3T5teXlv8oOt/bUENBOyLDVWqqsBWZduVycuDez3fsi0KIbWALfbezpUUiKc5LI3AvsJt2soBELnLE9yqEZjLDsCWF/MAvbo+AE16Ur4CkcDR30TaS5QCJLo+uS9D8j+0cwRU8Ho7off+o0mkbJyB70WPkXF5EN6tMN0bOWNdnnKjhpK0XdRQQDwMcNNkwfTU8g2b+afBCGRtv7cwldGaJf2XKehO+d2K6v9v4JEOh7IxhRNTflEx6YWopI/YLOami7MDTkys2qWevwbRK6Dt7MW3TivLor2Fx+NwNMGLVswNKL1TmYBH0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tNGrQU56nbbJNJC2too1e7vZFM9oUUAj/ujP6qVBM0o=; b=G2JNqCX3MkQplyam2tSGOmNJQ20KnKL9W+oOU4LLYhvvrGa7Qn2qkep8BKa9bl1u2fhX3OL0m8YNtTJiB8XNhpGTy6Lv4wEbaVBUisHz8XQsjhGeZ25+Hs72bFKoEcX7xdHu/5j0r9QZ+SUIBxMQCip84wkOFCLcvfgxV7RAG8689JP8MVoVOj2Hya7YZehEqQXC9LqoRDm7zfuZ5CzncqQiK85IB3BRYZYMOy8Vb22VNrOfyKXxDHBszRKdaIFFt+Zigl/wibeUMqYYSyR3zR8/MYb16H8irlp4SsPW9HM7mMfkeA9Ok4pMl8IghJPw4dYluBoLW3QITi2UJtV2UA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=htecgroup.com; dmarc=pass action=none header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tNGrQU56nbbJNJC2too1e7vZFM9oUUAj/ujP6qVBM0o=; b=LO6hDpa6bj7GWHbw9yVNYZcpI4vsal7CJna4tV/JsF6NZr3+fuwQpoAHYUDc5c//S3RehcAdCF/GLyv+r6P8vrVXpRSn6uZg1xnKUWAThwkdDtiRJwGb5oDVtMKF647FqHcyOinYMfn/nqibIUb0LMbVBYdnRN6H62qEAoi5ZoAMKTiOnsJdr7BF2zr41F9v00JB04Z433dBzVLjrVYrEjZb91BD1j8FZ2BgpM5iubVURMddNOcH0sDoCYIACWUmyxu8Ic0mYzG+XmmcSzzpmoApH/qje6yCdrhqnB9fziZicOHHgUdA2IQrkKiC9C0c8v6RGt8olG8Ar+dBdzcI5Q== Received: from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20) by DB9PR09MB6059.eurprd09.prod.outlook.com (2603:10a6:10:3d8::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr 2026 12:27:23 +0000 Received: from PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com ([fe80::ca17:d4db:b6cd:fb81%2]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026 12:27:23 +0000 From: Uros Stajic To: "u-boot@lists.denx.de" CC: Djordje Todorovic , Leo Yu-Chi Liang , Rick Chen , Chao-ying Fu , Uros Stajic Subject: [PATCH v7 7/7] riscv: p8700: Add Coherence Manager (CM) and IOCU support Thread-Topic: [PATCH v7 7/7] riscv: p8700: Add Coherence Manager (CM) and IOCU support Thread-Index: AQHczmWLXQc6s/I9+ke6RVNxMaOzeQ== Date: Fri, 17 Apr 2026 12:27:23 +0000 Message-ID: <20260417122213.147529-8-uros.stajic@htecgroup.com> References: <20260417122213.147529-1-uros.stajic@htecgroup.com> In-Reply-To: <20260417122213.147529-1-uros.stajic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA3PR09MB8140:EE_|DB9PR09MB6059:EE_ x-ms-office365-filtering-correlation-id: 19c16975-878a-447a-8d9e-08de9c7cadba x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|376014|1800799024|366016|38070700021|56012099003|18002099003|22082099003; x-microsoft-antispam-message-info: PJl37gZmgkxqdR2ZJtASKa6Lod7q7CoW17rirTqToPGFNj6XWuQ1dbGG6V+Nf03QO3Le0QmUOBY7FdNcJH7LITl3j0/FNK04VciOz5UZMZsJJUE+KRLszYFU7tQRv9u3LWc8K/Jw43U1cCKXnA57oaNXuX61DfYIGspbiH0CxZdBGSYQPOkHT79auR6BKFlL4Otpmf4VkCclNZ6Cstnp9C/gClb4BsYfwGczHoLFVpjjoVho3aZeIIz30b8wNtkr/kD+wKjGw8yDjj7ycmaVOYJmpd11rTVUL9eW5XYbSw0jO1VEmPWlrttIAlMg2xsjY6QmSKw0x0o8F9MHSyRX1vkuFdrEKBHApkKSFdEsRxTS1SPDVSSBMFZcWW44P2Olf6vuDzY0EG7N4/Gjb/APFPdA+EM+UT8a91vXcKWBEVxGWp+mFBM0b7Gy0pxeGOhPHWe0mLyLYcNUkeG1rr/Jgb+dgM73CagVu358jZVatc5HTOrr+EcCCJDwh1KqAgQ6IQc2EMgS4ta2j+rLfw11D0UCkcqSCcwYDahWGVjJ2d29FSeo0pia35a88k3UebKb8YBJxmPWpcLU2SX4/OVwxF5CMlqMweEPfETmfWjYdNk0Pg4XitBxRHn/KxKW3LyFWBbndnQf3rY8Kbwq0DS89K4nMos/wxt//3qXv0/VYkYarx966u3EztuKSDiS7C46vm0ok8yzEquJmuxB1eCeP3Y29KvW4z//iF8EOVOw+rxku9SGVGcipUHiTm/oCbdU6ko6jx1Tq2pdcisxdZBbsvmLRhzWy6wDIdFEQJUapXA= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(376014)(1800799024)(366016)(38070700021)(56012099003)(18002099003)(22082099003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?q?fbGFG6x+IjvH4XBeCQlBBjM?= =?iso-8859-1?q?+ZOtxIde3zzWgKGIqGSH0OqrViAKOI/SPq37OMdo6Qob/Rf0s1EzTDuFWSJW?= =?iso-8859-1?q?OhRZVXnhWYlgx1EPSnsKY7eppAEcislr/i/4TBCq6X9D/HfsA/Si9qq5YdL6?= =?iso-8859-1?q?dBtZ3YPRW+C/MDir4TAoc5kABNnpWNgXZ8QoT5XpMXlMgsEguTPZT9hSHAjQ?= =?iso-8859-1?q?M7DJa1cyn+AHZJITIY/JcTE6e5Q4eLi/grF5FCIQgeG5hFu0G0/5IaGqmuLk?= =?iso-8859-1?q?/ZfIVQtAY46CIQlErmExRG29LHO64LVF5JOHSchWZb3iz8GrymOFsCGWMKJd?= =?iso-8859-1?q?9bn7tyh5dw2dx0yC+V6JgAJcWkx00ApHRGVR4pm5lT3DbWmiJheN2xWqNgBc?= =?iso-8859-1?q?MT7KoIbxw4KxdAtRsDzagCDk8JYoHhxdVfRreirFOiJqBNQIvy8/t/iqvnXc?= =?iso-8859-1?q?SBM/akCr7bLjkV32dbSzjKRpltrDpGzbprEHt6SN+kd3qmblI9cWTPBqDMYi?= =?iso-8859-1?q?XVZsOJyWAepyCh3pqzl/ybhFLky48Sv7nNUU1DZa/EJNQ87kI1xOFrROt8OC?= =?iso-8859-1?q?cMZrW5FRt3IRwoy9lYGnb71Qnu36QcZmQIUU3x0UXWFrosZEy1NqVGQI97jR?= =?iso-8859-1?q?hfOfZyalzvZsbzp+C4yvh+BSzMCWDzPcil1W59wfGOxzAMgfVGWNzZ0w7Le7?= =?iso-8859-1?q?xHn/xcK5ldtw08L7CchcDIHlLJYKE+pmLascKHSzAx1xtDxUFBV8gsr2WBVF?= =?iso-8859-1?q?v5bNsbFlZSwB4AmrT5MvIciu9nN3SEB1/ZAZ7OGq8Gpo0f5oxqFdzy8Y6KOg?= =?iso-8859-1?q?Zd3ITcHt8ghvOOxfpiQKJlsvpKgEwGro9Z/HzO+us4oDRJsBkyhLvEBg6MNQ?= =?iso-8859-1?q?ypfw6HyucrCOEldeJF5DdEKLSjOm2+wdwR1fCFA7roiJulWlGIHpp8rggUEk?= =?iso-8859-1?q?uRxyrXFJR6lN/itrK64RRiK6FSTWXvqVkwZYPDE4RG159Q1t8qJuiNGUSCpJ?= =?iso-8859-1?q?g+zIOIU3gVb/gV6h28TSJbGh6iFltKkz43IYir6FmwIOi8kxpBZ08G/BJcCY?= =?iso-8859-1?q?yncRT7TWBMiWfTkjikLEYVGR5v8o2997uvq4m+QjaBI84+EViM5WPJdN+qex?= =?iso-8859-1?q?SSnaLoYH/2GtJ+/YoC3jaixAMr8n4QHBU/11iEvEmbkVVHBg+1YLW51lmxw0?= =?iso-8859-1?q?jDvH71G6rZ5sxj1TGMAb/x8xpFsJPMJ+FxPy4UOcUvneWBTv8DLKTddnP4Mo?= =?iso-8859-1?q?zbdTZBoUZWyAyOE4160SNy+ze8l3Pd7tgQFEPRencZK2JVn1N+mn7Uu/TdES?= =?iso-8859-1?q?uTLt7fACSIMmzfzwOnURnbK05p/Uv3cDhjCg67pbtnXefaikywn2rGTqD0VR?= =?iso-8859-1?q?7AI83b+pBQm8kKcdLY1o2HvoGCnC7GFvNJ0nJkVsl8P8kJADgsMEkNG33s4a?= =?iso-8859-1?q?7O8AayKK3yJVGQIsRxrlY9k6wtzw/FLMupHnwW7MaVazSeIc58GLBKyq4TGo?= =?iso-8859-1?q?20sik9RfBc7X+yT+hGCWNoawc492UFHXUsXrZaB+ZJG4dD8Xw+xypjRWBYk+?= =?iso-8859-1?q?mQFFy5RrpTPmlaj7CsGRuqIO4Y/0haDRRbUlwhlbAFmqtiUYjw2Zq/up8ifb?= =?iso-8859-1?q?BGldlGCLuHa9CIjtK0o+VL9h6as9JzVhrJ4Dw42J4DHSyC8CjEqxF6soMeZt?= =?iso-8859-1?q?vp9DLMoJ0IwNk2H1XmaBFO/ZKkylrTE7aVxYc08sGww428oeWPEcQUrKWp1F?= =?iso-8859-1?q?HCST0ZZ3F08Ve2DU+gm+3iaMY59DQQW6iMY2m/RSN9l0sICXJCdOh/urBI/a?= =?iso-8859-1?q?A6/nLFog=3D?= MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA3PR09MB8140.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 19c16975-878a-447a-8d9e-08de9c7cadba X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2026 12:27:23.7454 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: neE/Exuf1+Cx3dJ3+gbJ18lUjj87k3Bp+JjINCb1IX694kOIRjkajesNvnodk10G6RABS6nvZN4K5rS/7qK85erIbwAVYdRU5O+VvMpZioU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR09MB6059 X-Mailman-Approved-At: Fri, 17 Apr 2026 14:43:59 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Chao-ying Fu Add support for Coherence Manager (CM) and IOCU discovery and configuration on the P8700 platform. Signed-off-by: Chao-ying Fu Signed-off-by: Uros Stajic --- arch/riscv/cpu/p8700/Makefile | 2 + arch/riscv/cpu/p8700/cache.c | 6 ++ arch/riscv/cpu/p8700/cm-iocu.c | 75 ++++++++++++++++ arch/riscv/cpu/p8700/cm.c | 92 +++++++++++++++++++ arch/riscv/cpu/p8700/p8700.c | 2 + arch/riscv/include/asm/arch-p8700/cm.h | 61 +++++++++++++ arch/riscv/include/asm/arch-p8700/p8700.h | 32 +++++++ arch/riscv/include/asm/global_data.h | 4 + board/mips/boston-riscv/Makefile | 1 + board/mips/boston-riscv/boston-riscv.c | 11 +++ board/mips/boston-riscv/iocu.c | 102 ++++++++++++++++++++++ 11 files changed, 388 insertions(+) create mode 100644 arch/riscv/cpu/p8700/cm-iocu.c create mode 100644 arch/riscv/cpu/p8700/cm.c create mode 100644 arch/riscv/include/asm/arch-p8700/cm.h create mode 100644 board/mips/boston-riscv/iocu.c diff --git a/arch/riscv/cpu/p8700/Makefile b/arch/riscv/cpu/p8700/Makefile index 04291375a29..45f68bbda3d 100644 --- a/arch/riscv/cpu/p8700/Makefile +++ b/arch/riscv/cpu/p8700/Makefile @@ -3,6 +3,8 @@ # Copyright (C) 2021, Chao-ying Fu obj-y += cache.o +obj-y += cm.o +obj-y += cm-iocu.o obj-y += cpu.o obj-y += dram.o obj-y += p8700.o diff --git a/arch/riscv/cpu/p8700/cache.c b/arch/riscv/cpu/p8700/cache.c index 06e60156394..1343637eea7 100644 --- a/arch/riscv/cpu/p8700/cache.c +++ b/arch/riscv/cpu/p8700/cache.c @@ -48,6 +48,9 @@ static void probe_cache_config(void) void flush_dcache_range(unsigned long start, unsigned long end) { + if (dma_is_coherent()) + return; + if (lsize == 0) probe_cache_config(); @@ -71,6 +74,9 @@ void flush_dcache_range(unsigned long start, unsigned long end) void invalidate_dcache_range(unsigned long start, unsigned long end) { + if (dma_is_coherent()) + return; + if (lsize == 0) probe_cache_config(); diff --git a/arch/riscv/cpu/p8700/cm-iocu.c b/arch/riscv/cpu/p8700/cm-iocu.c new file mode 100644 index 00000000000..5850647d20f --- /dev/null +++ b/arch/riscv/cpu/p8700/cm-iocu.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MIPS Coherence Manager (CM) Support + * + * Copyright (c) 2016 Imagination Technologies Ltd. + */ +#include +#include +#include + +__weak bool plat_iocu_usable(unsigned int cluster, unsigned int iocu) +{ + return true; +} + +static int init_cluster_iocus(unsigned int cluster) +{ + DECLARE_GLOBAL_DATA_PTR; + void __iomem *global_gcrs; + u32 cfg, num_iocus, num_iocus_usable, local_cluster; + int i; + + local_cluster = mips_cluster_id(); + + global_gcrs = mips_cm_base(); + if (cluster != local_cluster) { + // FIXME + return 1; + } + + cfg = __raw_readl(global_gcrs + GCR_CONFIG); + num_iocus = cfg >> GCR_CONFIG_NUMIOCU_SHIFT; + num_iocus &= GCR_CONFIG_NUMIOCU_MASK; + gd->arch.num_iocus += num_iocus; + + /* Discover how many IOCUs are usable */ + num_iocus_usable = num_iocus; + for (i = num_iocus - 1; i >= 0; i--) { + if (!plat_iocu_usable(cluster, i)) + num_iocus_usable--; + } + gd->arch.num_iocus_usable += num_iocus_usable; + + /* If the cluster has no usable IOCUs there's nothing to do */ + if (num_iocus_usable == 0) { + if (cluster != local_cluster) + power_down_cluster(cluster); + + return 0; + } + + /* If the IOCUs are in the local cluster we're good to go already */ + if (cluster == local_cluster) + return 0; + + /* Ensure that the cluster's L2 cache is initialised */ + return init_cluster_l2(cluster); +} + +int mips_cm_init_iocus(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int cluster; + int err; + + for (cluster = 0; cluster < mips_cm_num_clusters(); cluster++) { + err = init_cluster_iocus(cluster); + if (err) { + gd->arch.num_iocus_usable = err; + return 0; + } + } + + return 0; +} diff --git a/arch/riscv/cpu/p8700/cm.c b/arch/riscv/cpu/p8700/cm.c new file mode 100644 index 00000000000..ce7485c564d --- /dev/null +++ b/arch/riscv/cpu/p8700/cm.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MIPS Coherence Manager (CM) Support + * + * Copyright (c) 2016 Imagination Technologies Ltd. + */ + +#include +#include +#include + +static void mips_cpc_init(void) +{ +} + +__weak const struct mmio_region *get_mmio_regions(void) +{ + return NULL; +} + +static void p8700_setup_mmio_limits(void) +{ + void __iomem *gcrs = mips_cm_base(); + const struct mmio_region *rgn = get_mmio_regions(); + unsigned int num_clusters = mips_cm_num_clusters(); + unsigned int limit = MIPS_CM_MMIO_LIMIT / num_clusters; + unsigned int i, reg_off; + + if (!rgn) + return; + + if (num_clusters != 1) { + // FIXME! Need to support multiple clusters. + return; + } + + reg_off = GCR_MMIO0_BOTTOM; + + for (i = 0; rgn[i].addr_high; i++) { + __raw_writeq(rgn[i].addr_high & GCR_MMIO0_TOP_ADDR, + gcrs + reg_off + (GCR_MMIO0_TOP - GCR_MMIO0_BOTTOM)); + + __raw_writeq((rgn[i].addr_low & GCR_MMIO0_BOTTOM_ADDR) | + (rgn[i].port << GCR_MMIO0_BOTTOM_PORT_SHIFT) | + (rgn[i].enable ? GCR_MMIO0_BOTTOM_ENABLE : 0), + gcrs + reg_off); + reg_off += GCR_MMIO1_BOTTOM - GCR_MMIO0_BOTTOM; + } + + __raw_writel(limit, gcrs + GCR_MMIO_REQ_LIMIT); +} + +int power_up_cluster(unsigned int cluster) +{ + return 0; +} + +int power_down_cluster(unsigned int cluster) +{ + return 0; +} + +int init_cluster_l2(unsigned int cluster) +{ + return 0; +} + +int mips_cm_init(void) +{ + int err; + + mips_cpc_init(); + + err = mips_cm_init_iocus(); + if (err) + return err; + + p8700_setup_mmio_limits(); + + return 0; +} + +int arch_cpu_init(void) +{ + int err; + + err = mips_cm_init(); + if (err) + return err; + + return 0; +} diff --git a/arch/riscv/cpu/p8700/p8700.c b/arch/riscv/cpu/p8700/p8700.c index 41d5547c511..802ec65ffb2 100644 --- a/arch/riscv/cpu/p8700/p8700.c +++ b/arch/riscv/cpu/p8700/p8700.c @@ -10,3 +10,5 @@ __weak void wait_ddr_calib(void) { } __weak void setup_pcie_dma_map(void) { } + +__weak bool dma_is_coherent(void) { return false; } diff --git a/arch/riscv/include/asm/arch-p8700/cm.h b/arch/riscv/include/asm/arch-p8700/cm.h new file mode 100644 index 00000000000..ab5ea7385b2 --- /dev/null +++ b/arch/riscv/include/asm/arch-p8700/cm.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021, Chao-ying Fu + */ + +#ifndef __P8700_CM_H__ +#define __P8700_CM_H__ + +#include + +struct mmio_region { + phys_addr_t addr_low; + phys_addr_t addr_high; + unsigned int port : 4; + unsigned int enable : 1; +}; + +const struct mmio_region *get_mmio_regions(void); + +void setup_redirect(unsigned int cluster, unsigned int core, + unsigned int vp, unsigned int block); + +int mips_cm_init_iocus(void); + +int power_up_cluster(unsigned int cluster); +int power_down_cluster(unsigned int cluster); +int init_cluster_l2(unsigned int cluster); + +static inline void *mips_cm_base(void) +{ + return (void *)CM_BASE; +} + +static inline void *mips_cpc_base(void) +{ + return (void *)CPC_BASE; +} + +static inline unsigned int mips_cm_num_clusters(void) +{ + u32 cfg; + + cfg = __raw_readl(mips_cm_base() + GCR_CONFIG); + cfg >>= GCR_CONFIG_NUMCLUSTERS_SHIFT; + cfg &= GCR_CONFIG_NUMCLUSTERS_MASK; + + return cfg; +} + +static inline unsigned int mips_cluster_id(void) +{ + u32 temp; + + asm volatile("csrr %0, mhartid" : "=r"(temp)); + temp >>= MHARTID_CLUSTER_SHIFT; + temp &= MHARTID_CLUSTER_MASK; + + return temp; +} + +#endif /* __P8700_CM_H__ */ diff --git a/arch/riscv/include/asm/arch-p8700/p8700.h b/arch/riscv/include/asm/arch-p8700/p8700.h index d6cc125d76a..98ce5ba3ffb 100644 --- a/arch/riscv/include/asm/arch-p8700/p8700.h +++ b/arch/riscv/include/asm/arch-p8700/p8700.h @@ -65,6 +65,10 @@ #define CM_BASE CONFIG_RISCV_CM_BASE #define CPC_BASE (CM_BASE + 0x8000) +/* Block offsets */ +#define GCR_OFF_GLOBAL 0x0000 +#define GCR_OFF_LOCAL 0x2000 + /* CPC Block offsets */ #define CPC_OFF_LOCAL 0x2000 @@ -75,6 +79,33 @@ #define CPC_Cx_CMD 0x0000 #define CPC_Cx_CMD_RESET 0x4 +/* GCR_CONFIG */ +#define GCR_CONFIG 0x0000 +#define GCR_REV 0x0030 +#define GCR_CONFIG_NUMCLUSTERS_SHIFT 23 +#define GCR_CONFIG_NUMCLUSTERS_MASK 0x7f +#define GCR_CONFIG_NUMIOCU_SHIFT 8 +#define GCR_CONFIG_NUMIOCU_MASK 0xf +#define GCR_CONFIG_NUMCORES_SHIFT 0 +#define GCR_CONFIG_NUMCORES_MASK 0xff + +/* GCR_REV CM versions */ +#define GCR_REV_CM3 0x0800 +#define GCR_REV_CM3_5 0x0900 + +#define GCR_MMIO_REQ_LIMIT 0x06f8 +#define GCR_MMIO0_BOTTOM 0x0700 +#define GCR_MMIO0_BOTTOM_ADDR (0xffffffffull << 16) +#define GCR_MMIO0_BOTTOM_PORT_SHIFT 2 +#define GCR_MMIO0_BOTTOM_PORT (0xf << 2) +#define GCR_MMIO0_BOTTOM_DISABLE_LIMIT (0x1 << 1) +#define GCR_MMIO0_BOTTOM_ENABLE (0x1 << 0) +#define GCR_MMIO0_TOP 0x0708 +#define GCR_MMIO0_TOP_ADDR (0xffffffffull << 16) +#define GCR_MMIO1_BOTTOM 0x0710 + +#define MIPS_CM_MMIO_LIMIT 4 + #define P8700_GCR_C0_COH_EN 0x20f8 #define P8700_GCR_C1_COH_EN 0x21f8 #define P8700_GCR_C2_COH_EN 0x22f8 @@ -97,5 +128,6 @@ void wait_ddr_calib(void); void setup_pcie_dma_map(void); +bool dma_is_coherent(void); #endif /* __P8700_H__ */ diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 33f2b5ec5c8..198eacd1e07 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -44,6 +44,10 @@ struct arch_global_data { ulong smbios_start; /* Start address of SMBIOS table */ #endif struct resume_data *resume; +#if CONFIG_IS_ENABLED(P8700_RISCV) + int num_iocus; + int num_iocus_usable; +#endif }; #include diff --git a/board/mips/boston-riscv/Makefile b/board/mips/boston-riscv/Makefile index 0615c677d23..c67c001d4e6 100644 --- a/board/mips/boston-riscv/Makefile +++ b/board/mips/boston-riscv/Makefile @@ -4,5 +4,6 @@ obj-y += boston-riscv.o obj-y += checkboard.o +obj-y += iocu.o obj-y += lowlevel_init.o obj-y += reset.o diff --git a/board/mips/boston-riscv/boston-riscv.c b/board/mips/boston-riscv/boston-riscv.c index f3fd2ec8348..4af918c8c81 100644 --- a/board/mips/boston-riscv/boston-riscv.c +++ b/board/mips/boston-riscv/boston-riscv.c @@ -46,3 +46,14 @@ void setup_pcie_dma_map(void) writel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE1ADDR); writel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE2ADDR); } + +bool dma_is_coherent(void) +{ + u32 pcie0_off = readl((void __iomem *)BOSTON_PLAT_NOCPCIE0ADDR); + u32 pcie1_off = readl((void __iomem *)BOSTON_PLAT_NOCPCIE1ADDR); + u32 pcie2_off = readl((void __iomem *)BOSTON_PLAT_NOCPCIE2ADDR); + + return pcie0_off == BOSTON_IOCU_NOC_OFFSET && + pcie1_off == BOSTON_IOCU_NOC_OFFSET && + pcie2_off == BOSTON_IOCU_NOC_OFFSET; +} diff --git a/board/mips/boston-riscv/iocu.c b/board/mips/boston-riscv/iocu.c new file mode 100644 index 00000000000..807f09804a3 --- /dev/null +++ b/board/mips/boston-riscv/iocu.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2016 Imagination Technologies Ltd. + */ + +#include "boston-regs.h" +#include +#include +#include +#include +#include + +static const struct mmio_region mmio_regions[] = { + { 0x10000000, 0x160f0000, .enable = 1 }, + { 0x17ff0000, 0x17ff0000, .enable = 1 }, + { 0 }, +}; + +const struct mmio_region *get_mmio_regions(void) +{ + return mmio_regions; +} + +static int set_io_coherent(bool coherent) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!coherent) { + printf("I/O: Non-Coherent (Forced by environment)\n"); + goto noncoherent; + } + + if (gd->arch.num_iocus_usable < 0) { + printf("I/O: Non-Coherent (IOCU init error %d)\n", + gd->arch.num_iocus_usable); + goto noncoherent; + } + + if (gd->arch.num_iocus == 0) { + printf("I/O: Non-Coherent (No IOCU)\n"); + goto noncoherent; + } + + if (gd->arch.num_iocus_usable == 0) { + printf("I/O: Non-Coherent (IOCU not connected)\n"); + goto noncoherent; + } + + /* + * We have some number of connected IOCUs. Map all PCIe DMA access to + * hit the IOCU by offsetting the addresses as they pass from the PCIe + * controller to the NoC. + */ + writel(0x10, (u32 *)BOSTON_PLAT_NOCPCIE0ADDR); + writel(0x10, (u32 *)BOSTON_PLAT_NOCPCIE1ADDR); + writel(0x10, (u32 *)BOSTON_PLAT_NOCPCIE2ADDR); + + printf("I/O: Coherent\n"); + return 0; + +noncoherent: + /* Map all PCIe DMA access to its default, non-IOCU, target */ + writel(0x00, (u32 *)BOSTON_PLAT_NOCPCIE0ADDR); + writel(0x00, (u32 *)BOSTON_PLAT_NOCPCIE1ADDR); + writel(0x00, (u32 *)BOSTON_PLAT_NOCPCIE2ADDR); + + return 0; +} + +static int on_io_coherent(const char *name, const char *value, + enum env_op op, int flags) +{ + switch (op) { + case env_op_create: + case env_op_overwrite: + if (!strcmp(value, "0")) { + set_io_coherent(false); + } else if (!strcmp(value, "1")) { + set_io_coherent(true); + } else { + printf("### io.coherent must equal 0 or 1\n"); + return -EINVAL; + } + return 0; + + case env_op_delete: + set_io_coherent(true); + return 0; + + default: + return 0; + } +} + +U_BOOT_ENV_CALLBACK(io_coherent, on_io_coherent); + +static int p8700_misc_init_f(void) +{ + return set_io_coherent(env_get_yesno("io.coherent") != 0); +} + +EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, p8700_misc_init_f);