From patchwork Thu Mar 19 08:29:46 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yu-Chi Liang X-Patchwork-Id: 2213080 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fbzRY0pjTz1xyt for ; Thu, 19 Mar 2026 19:30:49 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ABA5383FC0; Thu, 19 Mar 2026 09:30:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B152083F2D; Thu, 19 Mar 2026 09:30:37 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B6DD183E16 for ; Thu, 19 Mar 2026 09:30:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62J8TtpH014939; Thu, 19 Mar 2026 16:29:55 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Mar 2026 16:29:55 +0800 From: Leo Yu-Chi Liang To: CC: , , , , , , , , , , , , Subject: [PATCH 1/6] riscv: sbi: Add Andes vendor extension and PMA call wrappers Date: Thu, 19 Mar 2026 16:29:46 +0800 Message-ID: <20260319082951.3310908-1-ycliang@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 62J8TtpH014939 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for the Andes SBI vendor extension (EXT_ID 0x0900031E) with function IDs for PMA (Physical Memory Attribute) operations: probe, set, and free. These SBI calls allow S-mode software to configure memory attributes through OpenSBI, which is needed for setting up noncached memory regions on Andes RISC-V platforms. Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/sbi.h | 22 ++++++++++++++++ arch/riscv/lib/sbi.c | 51 ++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 47124dbaac8..8642954d272 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -37,6 +37,7 @@ enum sbi_ext_id { SBI_EXT_FWFT = 0x46574654, SBI_EXT_DBTR = 0x44425452, SBI_EXT_MPXY = 0x4D505859, + SBI_EXT_ANDES = 0x0900031E, }; enum sbi_ext_base_fid { @@ -98,6 +99,23 @@ enum sbi_srst_reset_reason { SBI_SRST_RESET_REASON_SYS_FAILURE, }; +enum sbi_ext_andes_fid { + SBI_EXT_ANDES_FID0 = 0, + SBI_EXT_ANDES_IOCP_SW_WORKAROUND, + SBI_EXT_ANDES_PMA_PROBE, + SBI_EXT_ANDES_PMA_SET, + SBI_EXT_ANDES_PMA_FREE, +}; + +/* Andes PMA configuration flags */ +#define ANDES_PMACFG_ETYP_OFFSET 0 +#define ANDES_PMACFG_ETYP_NAPOT (3 << ANDES_PMACFG_ETYP_OFFSET) +#define ANDES_PMACFG_ETYP_OFF (0 << ANDES_PMACFG_ETYP_OFFSET) +#define ANDES_PMACFG_ETYP_MASK (3 << ANDES_PMACFG_ETYP_OFFSET) +#define ANDES_PMACFG_MTYP_OFFSET 2 +#define ANDES_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << ANDES_PMACFG_MTYP_OFFSET) +#define ANDES_PMACFG_MTYP_DEV_NOBUF (0 << ANDES_PMACFG_MTYP_OFFSET) + enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, SBI_EXT_DBCN_CONSOLE_READ, @@ -176,4 +194,8 @@ int sbi_get_mimpid(long *mimpid); void sbi_srst_reset(unsigned long type, unsigned long reason); int sbi_dbcn_write_byte(unsigned char ch); +int sbi_pma_probe(void); +int sbi_pma_set(unsigned long pa, unsigned long size, unsigned long flags); +int sbi_pma_free(unsigned long pa); + #endif diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 35a7d3b12f5..f8a2da5c271 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -220,6 +220,57 @@ int sbi_dbcn_write_byte(unsigned char ch) return ret.error; } +/** + * sbi_pma_probe() - Probe for Andes PMA support + * + * Return: Number of PMA entries on success, SBI error on failure + */ +int sbi_pma_probe(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_ANDES, SBI_EXT_ANDES_PMA_PROBE, + 0, 0, 0, 0, 0, 0); + if (ret.error) + return ret.error; + + return ret.value; +} + +/** + * sbi_pma_set() - Set a PMA region + * @pa: Physical address of the region + * @size: Size of the region + * @flags: PMA configuration flags + * + * Return: 0 on success, SBI error on failure + */ +int sbi_pma_set(unsigned long pa, unsigned long size, unsigned long flags) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_ANDES, SBI_EXT_ANDES_PMA_SET, + pa, size, flags, 0, 0, 0); + + return ret.error; +} + +/** + * sbi_pma_free() - Free a PMA region + * @pa: Physical address of the region to free + * + * Return: 0 on success, SBI error on failure + */ +int sbi_pma_free(unsigned long pa) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_ANDES, SBI_EXT_ANDES_PMA_FREE, + pa, 0, 0, 0, 0, 0); + + return ret.error; +} + #ifdef CONFIG_SBI_V01 /** From patchwork Thu Mar 19 08:29:47 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yu-Chi Liang X-Patchwork-Id: 2213079 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fbzRP6jhmz1xyt for ; Thu, 19 Mar 2026 19:30:41 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 66D0B83F2D; Thu, 19 Mar 2026 09:30:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A878283FA4; Thu, 19 Mar 2026 09:30:37 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 38BB883F2D for ; Thu, 19 Mar 2026 09:30:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62J8Tte2014940; Thu, 19 Mar 2026 16:29:55 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Mar 2026 16:29:55 +0800 From: Leo Yu-Chi Liang To: CC: , , , , , , , , , , , , Subject: [PATCH 2/6] riscv: Extend noncached memory support to RISC-V Date: Thu, 19 Mar 2026 16:29:47 +0800 Message-ID: <20260319082951.3310908-2-ycliang@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260319082951.3310908-1-ycliang@andestech.com> References: <20260319082951.3310908-1-ycliang@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 62J8Tte2014940 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Extend the SYS_HAS_NONCACHED_MEMORY Kconfig to support RISC-V in addition to ARM and MIPS, and add FTMAC100 to the list of drivers that benefit from noncached memory. The ftmac100 DMA descriptors needs to be marked uncacheable to stay coherent for SW and HW on noncoherent platforms. Also add MMU_SECTION_SIZE definition (1MB) to the RISC-V system header, matching the MIPS convention used by the noncached memory infrastructure. Signed-off-by: Leo Yu-Chi Liang --- arch/Kconfig | 2 +- arch/riscv/include/asm/system.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index fb3e8d598e7..b05f249b661 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -529,7 +529,7 @@ endmenu config SYS_HAS_NONCACHED_MEMORY bool "Enable reserving a non-cached memory area for drivers" - depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH) + depends on (ARM || MIPS || RISCV) && (RTL8169 || MEDIATEK_ETH || FTMAC100) help This is useful for drivers that would otherwise require a lot of explicit cache maintenance. For some drivers it's also impossible to diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h index 87a804bfd5f..b71bbeef1e2 100644 --- a/arch/riscv/include/asm/system.h +++ b/arch/riscv/include/asm/system.h @@ -25,6 +25,12 @@ struct event; csr_set(CSR_SSTATUS, __flags & SR_SIE); \ } while (0) +#ifdef CONFIG_SYS_NONCACHED_MEMORY +/* 1MB granularity */ +#define MMU_SECTION_SHIFT 20 +#define MMU_SECTION_SIZE BIT(MMU_SECTION_SHIFT) +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ + /* Hook to set up the CPU (called from SPL too) */ int riscv_cpu_setup(void); From patchwork Thu Mar 19 08:37:10 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yu-Chi Liang X-Patchwork-Id: 2213086 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fbzc06MPYz1y1P for ; Thu, 19 Mar 2026 19:38:08 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C2F5383FE1; Thu, 19 Mar 2026 09:37:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 06CB183DA6; Thu, 19 Mar 2026 09:37:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 98C2383E36 for ; Thu, 19 Mar 2026 09:37:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62J8bI6K017660; Thu, 19 Mar 2026 16:37:18 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Mar 2026 16:37:18 +0800 From: Leo Yu-Chi Liang To: CC: , , , , , , , , , , , , Subject: [PATCH 3/6] riscv: andes: Implement noncached memory using SBI PMA Date: Thu, 19 Mar 2026 16:37:10 +0800 Message-ID: <20260319083713.3456894-1-ycliang@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 62J8bI6K017660 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Implement noncached memory region management for Andes RISC-V platforms using SBI PMA (Physical Memory Attribute) calls: - noncached_init(): Compute region below malloc area, probe PMA support via sbi_pma_probe(), then configure the region as non-cacheable bufferable using sbi_pma_set() with NAPOT and NON_CACHE_BUF flags. - noncached_alloc(): Bump allocator from the noncached region. - noncached_set_region(): No-op since PMA handles attributes. - noncached_free(): Release PMA entry, with probe-before-free guard to avoid calling free on unsupported firmware. Also call noncached_free() in cleanup_before_linux() before cache_flush() so the PMA entry is released before handing off to Linux. Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/cpu/andes/Makefile | 1 + arch/riscv/cpu/andes/cpu.c | 3 ++ arch/riscv/cpu/andes/noncache.c | 79 +++++++++++++++++++++++++++++++++ include/cpu_func.h | 1 + 4 files changed, 84 insertions(+) create mode 100644 arch/riscv/cpu/andes/noncache.c diff --git a/arch/riscv/cpu/andes/Makefile b/arch/riscv/cpu/andes/Makefile index 35a1a2fb836..f3602f6f598 100644 --- a/arch/riscv/cpu/andes/Makefile +++ b/arch/riscv/cpu/andes/Makefile @@ -6,3 +6,4 @@ obj-y := cpu.o obj-y += cache.o obj-y += spl.o +obj-$(CONFIG_SYS_HAS_NONCACHED_MEMORY) += noncache.o diff --git a/arch/riscv/cpu/andes/cpu.c b/arch/riscv/cpu/andes/cpu.c index feb755a4f0d..3aa89d86b6b 100644 --- a/arch/riscv/cpu/andes/cpu.c +++ b/arch/riscv/cpu/andes/cpu.c @@ -22,6 +22,9 @@ int cleanup_before_linux(void) { disable_interrupts(); + if (IS_ENABLED(CONFIG_SYS_HAS_NONCACHED_MEMORY)) + noncached_free(); + cache_flush(); return 0; diff --git a/arch/riscv/cpu/andes/noncache.c b/arch/riscv/cpu/andes/noncache.c new file mode 100644 index 00000000000..9886a757620 --- /dev/null +++ b/arch/riscv/cpu/andes/noncache.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +static unsigned long noncached_start; +static unsigned long noncached_end; +static unsigned long noncached_next; + +void noncached_set_region(void) +{ +} + +int noncached_init(void) +{ + phys_addr_t start, end; + size_t size; + int ret; + + /* If this calculation changes, update board_f.c:reserve_noncached() */ + end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; + size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); + start = end - size; + + debug("mapping memory %pa-%pa non-cached\n", &start, &end); + + ret = sbi_pma_probe(); + if (ret <= 0) { + debug("PMA probe failed: %d\n", ret); + return ret; + } + + ret = sbi_pma_set(start, size, + ANDES_PMACFG_ETYP_NAPOT | + ANDES_PMACFG_MTYP_MEM_NON_CACHE_BUF); + if (ret) { + debug("PMA set failed: %d\n", ret); + return ret; + } + + noncached_start = start; + noncached_end = end; + noncached_next = start; + + return 0; +} + +phys_addr_t noncached_alloc(size_t size, size_t align) +{ + phys_addr_t next = ALIGN(noncached_next, align); + + if (next >= noncached_end || (noncached_end - next) < size) + return 0; + + debug("allocated %zu bytes of uncached memory @%pa\n", size, &next); + noncached_next = next + size; + + return next; +} + +void noncached_free(void) +{ + if (!noncached_start) + return; + + if (sbi_pma_probe() <= 0) + return; + + sbi_pma_free(noncached_start); +} diff --git a/include/cpu_func.h b/include/cpu_func.h index 70a41ead3f7..061d497d454 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -100,6 +100,7 @@ int noncached_init(void); void noncached_set_region(void); phys_addr_t noncached_alloc(size_t size, size_t align); +void noncached_free(void); enum { /* Disable caches (else flush caches but leave them active) */ From patchwork Thu Mar 19 08:37:11 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yu-Chi Liang X-Patchwork-Id: 2213085 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fbzbq4z4hz1y1P for ; Thu, 19 Mar 2026 19:37:59 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 89B7D83E36; Thu, 19 Mar 2026 09:37:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 03FE883F8A; Thu, 19 Mar 2026 09:37:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, RDNS_NONE,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (unknown [60.248.187.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5422683DA6 for ; Thu, 19 Mar 2026 09:37:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62J8bIUD017661; Thu, 19 Mar 2026 16:37:18 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Mar 2026 16:37:18 +0800 From: Leo Yu-Chi Liang To: CC: , , , , , , , , , , , , Subject: [PATCH 4/6] cache: andes-l2: Add writeback-invalidate operation Date: Thu, 19 Mar 2026 16:37:11 +0800 Message-ID: <20260319083713.3456894-2-ycliang@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260319083713.3456894-1-ycliang@andestech.com> References: <20260319083713.3456894-1-ycliang@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 62J8bIUD017661 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add a wbinval operation to the cache uclass that performs writeback-invalidate without the disable/enable cycle that the existing disable path uses. This is needed for flush_dcache_all() to properly flush both L1 and L2 caches. Implement andes_l2_wbinval_all() in the Andes L2 cache driver which issues the L2_WBINVAL_ALL command while keeping the cache enabled. Update flush_dcache_all() in the Andes cache code to also call L2 wbinval when CONFIG_ANDES_L2_CACHE is enabled. Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/cpu/andes/cache.c | 4 ++++ drivers/cache/cache-andes-l2.c | 24 ++++++++++++++++++++++++ drivers/cache/cache-uclass.c | 10 ++++++++++ include/cache.h | 16 ++++++++++++++++ 4 files changed, 54 insertions(+) diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c index bb57498d75a..3b325d77954 100644 --- a/arch/riscv/cpu/andes/cache.c +++ b/arch/riscv/cpu/andes/cache.c @@ -44,6 +44,10 @@ static void cache_ops(int (*ops)(struct udevice *dev)) void flush_dcache_all(void) { csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); + +#ifdef CONFIG_ANDES_L2_CACHE + cache_ops(cache_wbinval); +#endif } void flush_dcache_range(unsigned long start, unsigned long end) diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c index 45a4f216b07..5ceccf609e5 100644 --- a/drivers/cache/cache-andes-l2.c +++ b/drivers/cache/cache-andes-l2.c @@ -91,6 +91,29 @@ static int andes_l2_enable(struct udevice *dev) return 0; } +static int andes_l2_wbinval_all(struct udevice *dev) +{ + struct andes_l2_plat *plat = dev_get_plat(dev); + volatile struct l2cache *regs = plat->regs; + u8 hart = gd->arch.boot_hart; + + void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); + void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart); + + if ((regs) && (readl(®s->control) & L2_ENABLE)) { + writel(L2_WBINVAL_ALL, cctlcmd); + + while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) { + if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) { + printf("L2 flush illegal! hanging..."); + hang(); + } + } + } + + return 0; +} + static int andes_l2_disable(struct udevice *dev) { struct andes_l2_plat *plat = dev_get_plat(dev); @@ -192,6 +215,7 @@ static const struct udevice_id andes_l2_cache_ids[] = { static const struct cache_ops andes_l2_cache_ops = { .enable = andes_l2_enable, .disable = andes_l2_disable, + .wbinval = andes_l2_wbinval_all, }; U_BOOT_DRIVER(andes_l2_cache) = { diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c index 300e7bc86e1..8e77c9e2f4e 100644 --- a/drivers/cache/cache-uclass.c +++ b/drivers/cache/cache-uclass.c @@ -38,6 +38,16 @@ int cache_disable(struct udevice *dev) return ops->disable(dev); } +int cache_wbinval(struct udevice *dev) +{ + struct cache_ops *ops = cache_get_ops(dev); + + if (!ops->wbinval) + return -ENOSYS; + + return ops->wbinval(dev); +} + UCLASS_DRIVER(cache) = { .id = UCLASS_CACHE, .name = "cache", diff --git a/include/cache.h b/include/cache.h index 296ae3c8b48..45b27ab989c 100644 --- a/include/cache.h +++ b/include/cache.h @@ -42,6 +42,14 @@ struct cache_ops { * @return 0 if OK, -ve on error */ int (*disable)(struct udevice *dev); + + /** + * wbinval() - Writeback and invalidate cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*wbinval)(struct udevice *dev); }; #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops) @@ -70,4 +78,12 @@ int cache_enable(struct udevice *dev); * Return: 0 if OK, -ve on error */ int cache_disable(struct udevice *dev); + +/** + * cache_wbinval() - Writeback and invalidate cache + * + * @dev: Device to check (UCLASS_CACHE) + * Return: 0 if OK, -ve on error + */ +int cache_wbinval(struct udevice *dev); #endif From patchwork Thu Mar 19 08:37:12 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yu-Chi Liang X-Patchwork-Id: 2213087 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4fbzcB32dMz1y1P for ; Thu, 19 Mar 2026 19:38:18 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4C18C83FF5; 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dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 62J8bIe9017662 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Change TX and RX DMA descriptors from inline arrays embedded in struct ftmac100_data to dynamically allocated pointers. When CONFIG_SYS_NONCACHED_MEMORY is enabled, allocate descriptors from the noncached memory region using noncached_alloc(); otherwise fall back to memalign(). Signed-off-by: Leo Yu-Chi Liang --- drivers/net/ftmac100.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index fa0b3dbb6d1..f7f7db56130 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -30,8 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; #define FTMAC100_MDIO_TIMEOUT_USEC 10000 struct ftmac100_data { - struct ftmac100_txdes txdes[1]; - struct ftmac100_rxdes rxdes[PKTBUFSRX]; + struct ftmac100_txdes *txdes; + struct ftmac100_rxdes *rxdes; int rx_index; const char *name; struct ftmac100 *ftmac100; @@ -403,12 +403,35 @@ static int ftmac100_mdio_init(struct udevice *dev) return 0; } +static void *ftmac100_alloc_descs(unsigned int num, unsigned int size) +{ +#ifdef CONFIG_SYS_NONCACHED_MEMORY + return (void *)noncached_alloc(num * size, + ARCH_DMA_MINALIGN); +#else + return memalign(ARCH_DMA_MINALIGN, num * size); +#endif +} + static int ftmac100_probe(struct udevice *dev) { struct ftmac100_data *priv = dev_get_priv(dev); priv->name = dev->name; int ret = 0; + priv->txdes = ftmac100_alloc_descs(1, sizeof(struct ftmac100_txdes)); + if (!priv->txdes) { + dev_err(dev, "Failed to allocate tx descriptors\n"); + return -ENOMEM; + } + + priv->rxdes = ftmac100_alloc_descs(PKTBUFSRX, + sizeof(struct ftmac100_rxdes)); + if (!priv->rxdes) { + dev_err(dev, "Failed to allocate rx descriptors\n"); + return -ENOMEM; + } + ret = ftmac100_mdio_init(dev); if (ret) { dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); From patchwork Thu Mar 19 08:37:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yu-Chi Liang X-Patchwork-Id: 2213088 X-Patchwork-Delegate: tim609@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; 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Thu, 19 Mar 2026 09:38:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=reject dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62J8bJtp017663; Thu, 19 Mar 2026 16:37:19 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Mar 2026 16:37:18 +0800 From: Leo Yu-Chi Liang To: CC: , , , , , , , , , , , , Subject: [PATCH 6/6] configs: ae350: Enable noncached memory support Date: Thu, 19 Mar 2026 16:37:13 +0800 Message-ID: <20260319083713.3456894-4-ycliang@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260319083713.3456894-1-ycliang@andestech.com> References: <20260319083713.3456894-1-ycliang@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 62J8bJtp017663 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enable CONFIG_SYS_HAS_NONCACHED_MEMORY and set CONFIG_SYS_NONCACHED_MEMORY to 1MB (0x100000) on all AE350 S-mode defconfigs where SBI is available: ae350_rv{32,64}_spl_defconfig ae350_rv{32,64}_spl_xip_defconfig ae350_rv{32,64}_falcon_defconfig ae350_rv{32,64}_falcon_xip_defconfig Signed-off-by: Leo Yu-Chi Liang --- configs/ae350_rv32_falcon_defconfig | 2 ++ configs/ae350_rv32_falcon_xip_defconfig | 2 ++ configs/ae350_rv32_spl_defconfig | 2 ++ configs/ae350_rv32_spl_xip_defconfig | 2 ++ configs/ae350_rv64_falcon_defconfig | 2 ++ configs/ae350_rv64_falcon_xip_defconfig | 2 ++ configs/ae350_rv64_spl_defconfig | 2 ++ configs/ae350_rv64_spl_xip_defconfig | 2 ++ 8 files changed, 16 insertions(+) diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig index 659be8287ba..08d27d7c823 100644 --- a/configs/ae350_rv32_falcon_defconfig +++ b/configs/ae350_rv32_falcon_defconfig @@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig index 93b80ef789d..42f0d5f4e60 100644 --- a/configs/ae350_rv32_falcon_xip_defconfig +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -55,6 +55,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 4b0f52ff42b..146e3650708 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index f076f36c73c..c994331e75f 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -54,6 +54,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig index c7c44671419..5dd58047aeb 100644 --- a/configs/ae350_rv64_falcon_defconfig +++ b/configs/ae350_rv64_falcon_defconfig @@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig index ae9c7cfd933..78e1ea118ac 100644 --- a/configs/ae350_rv64_falcon_xip_defconfig +++ b/configs/ae350_rv64_falcon_xip_defconfig @@ -55,6 +55,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index af000ca58ce..22c710661e0 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 8c6e2773723..d2b29c19397 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -54,6 +54,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_FTMAC100=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_NONCACHED_MEMORY=0x100000 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y