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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 06:42:02.5730 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c90e9dd0-66cf-4f68-3c76-08de5a4a844e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7549 Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra264. The number of pins is slightly different, but the programming model remains the same. Add a new header, include/dt-bindings/gpio/tegra264-gpio.h, that defines port IDs as well as the TEGRA264_MAIN_GPIO() helper, both of which are used in conjunction to create a unique specifier for each pin. On Tegra, GPIO wake events are latched and routed via the PMC. Document the standard DT property, wakeup-parent, which is a phandle to the PMC interrupt controller that provides the parent wake interrupt domain for the GPIO controller. If the property is absent the driver falls back to a compatible-based lookup. Signed-off-by: Prathamesh Shete --- Changes in v2: * Update DT binding to use “wakeup-parent” (drop custom nvidia,pmc). * Require “wakeup-parent” for Tegra264 compatibles in the binding. * Rename header file to "nvidia,tegra264-gpio.h". --- .../bindings/gpio/nvidia,tegra186-gpio.yaml | 24 +++++++ .../dt-bindings/gpio/nvidia,tegra264-gpio.h | 62 +++++++++++++++++++ 2 files changed, 86 insertions(+) create mode 100644 include/dt-bindings/gpio/nvidia,tegra264-gpio.h diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 2bd620a1099b..b74fc3a8d80d 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -86,6 +86,9 @@ properties: - nvidia,tegra234-gpio - nvidia,tegra234-gpio-aon - nvidia,tegra256-gpio + - nvidia,tegra264-gpio + - nvidia,tegra264-gpio-uphy + - nvidia,tegra264-gpio-aon reg-names: items: @@ -110,6 +113,12 @@ properties: ports, in the order the HW manual describes them. The number of entries required varies depending on compatible value. + wakeup-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the parent interrupt controller used for wake-up. + On Tegra, this typically references the PMC interrupt controller. + gpio-controller: true gpio-ranges: @@ -157,6 +166,8 @@ allOf: - nvidia,tegra194-gpio - nvidia,tegra234-gpio - nvidia,tegra256-gpio + - nvidia,tegra264-gpio + - nvidia,tegra264-gpio-uphy then: properties: interrupts: @@ -171,12 +182,25 @@ allOf: - nvidia,tegra186-gpio-aon - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio-aon + - nvidia,tegra264-gpio-aon then: properties: interrupts: minItems: 1 maxItems: 4 + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra264-gpio + - nvidia,tegra264-gpio-uphy + - nvidia,tegra264-gpio-aon + then: + required: + - wakeup-parent + required: - compatible - reg diff --git a/include/dt-bindings/gpio/nvidia,tegra264-gpio.h b/include/dt-bindings/gpio/nvidia,tegra264-gpio.h new file mode 100644 index 000000000000..689cf5c67c0c --- /dev/null +++ b/include/dt-bindings/gpio/nvidia,tegra264-gpio.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for binding nvidia,tegra264-gpio*. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA264_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA264_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA264_MAIN_GPIO_PORT_T 0 +#define TEGRA264_MAIN_GPIO_PORT_U 1 +#define TEGRA264_MAIN_GPIO_PORT_V 2 +#define TEGRA264_MAIN_GPIO_PORT_W 3 +#define TEGRA264_MAIN_GPIO_PORT_AL 4 +#define TEGRA264_MAIN_GPIO_PORT_Y 5 +#define TEGRA264_MAIN_GPIO_PORT_Z 6 +#define TEGRA264_MAIN_GPIO_PORT_X 7 +#define TEGRA264_MAIN_GPIO_PORT_H 8 +#define TEGRA264_MAIN_GPIO_PORT_J 9 +#define TEGRA264_MAIN_GPIO_PORT_K 10 +#define TEGRA264_MAIN_GPIO_PORT_L 11 +#define TEGRA264_MAIN_GPIO_PORT_M 12 +#define TEGRA264_MAIN_GPIO_PORT_P 13 +#define TEGRA264_MAIN_GPIO_PORT_Q 14 +#define TEGRA264_MAIN_GPIO_PORT_R 15 +#define TEGRA264_MAIN_GPIO_PORT_S 16 +#define TEGRA264_MAIN_GPIO_PORT_F 17 +#define TEGRA264_MAIN_GPIO_PORT_G 18 + +#define TEGRA264_MAIN_GPIO(port, offset) \ + ((TEGRA264_MAIN_GPIO_PORT_##port * 8) + (offset)) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA264_AON_GPIO_PORT_AA 0 +#define TEGRA264_AON_GPIO_PORT_BB 1 +#define TEGRA264_AON_GPIO_PORT_CC 2 +#define TEGRA264_AON_GPIO_PORT_DD 3 +#define TEGRA264_AON_GPIO_PORT_EE 4 + +#define TEGRA264_AON_GPIO(port, offset) \ + ((TEGRA264_AON_GPIO_PORT_##port * 8) + (offset)) + +#define TEGRA264_UPHY_GPIO_PORT_A 0 +#define TEGRA264_UPHY_GPIO_PORT_B 1 +#define TEGRA264_UPHY_GPIO_PORT_C 2 +#define TEGRA264_UPHY_GPIO_PORT_D 3 +#define TEGRA264_UPHY_GPIO_PORT_E 4 + +#define TEGRA264_UPHY_GPIO(port, offset) \ + ((TEGRA264_UPHY_GPIO_PORT_##port * 8) + (offset)) + +#endif + From patchwork Fri Jan 23 06:41:39 2026 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 06:42:13.7941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69f7f0cc-4ad0-42fc-e4db-08de5a4a8b02 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8481 Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra264. Use the "wakeup-parent" phandle from the GPIO device tree node to ensure the GPIO driver associates with the intended PMC device. Relying only on compatible-based lookup can select an unexpected PMC node, so fall back to compatible-based lookup when the phandle is not present. Signed-off-by: Prathamesh Shete Reviewed-by: Jon Hunter --- Changes in v2: * Use “wakeup-parent” instead of "nvidia,pmc" and include the renamed header. --- drivers/gpio/gpio-tegra186.c | 90 +++++++++++++++++++++++++++++++++++- 1 file changed, 88 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index b1498b59a921..9c874f07be75 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2025 NVIDIA Corporation + * Copyright (c) 2016-2026 NVIDIA Corporation * * Author: Thierry Reding * Dipen Patel @@ -21,6 +21,7 @@ #include #include #include +#include /* security registers */ #define TEGRA186_GPIO_CTL_SCR 0x0c @@ -1001,7 +1002,9 @@ static int tegra186_gpio_probe(struct platform_device *pdev) if (gpio->soc->num_irqs_per_bank > 1) tegra186_gpio_init_route_mapping(gpio); - np = of_find_matching_node(NULL, tegra186_pmc_of_match); + np = of_parse_phandle(pdev->dev.of_node, "wakeup-parent", 0); + if (!np) + np = of_find_matching_node(NULL, tegra186_pmc_of_match); if (np) { if (of_device_is_available(np)) { irq->parent_domain = irq_find_host(np); @@ -1277,6 +1280,80 @@ static const struct tegra_gpio_soc tegra241_aon_soc = { .has_vm_support = false, }; +#define TEGRA264_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ + TEGRA_GPIO_PORT(TEGRA264_MAIN, _name, _bank, _port, _pins) + +static const struct tegra_gpio_port tegra264_main_ports[] = { + TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8), + TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5), + TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8), + TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8), + TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8), + TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8), + TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6), + TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8), + TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8), + TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8), + TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2), + TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7), + TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8), + TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8), + TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8), + TEGRA264_MAIN_GPIO_PORT(X, 0, 7, 6), + TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8), + TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8), + TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3), +}; + +static const struct tegra_gpio_soc tegra264_main_soc = { + .num_ports = ARRAY_SIZE(tegra264_main_ports), + .ports = tegra264_main_ports, + .name = "tegra264-gpio", + .instance = 0, + .num_irqs_per_bank = 8, + .has_vm_support = true, +}; + +#define TEGRA264_AON_GPIO_PORT(_name, _bank, _port, _pins) \ + TEGRA_GPIO_PORT(TEGRA264_AON, _name, _bank, _port, _pins) + +static const struct tegra_gpio_port tegra264_aon_ports[] = { + TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8), + TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2), + TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8), + TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8), + TEGRA264_AON_GPIO_PORT(EE, 0, 4, 4) +}; + +static const struct tegra_gpio_soc tegra264_aon_soc = { + .num_ports = ARRAY_SIZE(tegra264_aon_ports), + .ports = tegra264_aon_ports, + .name = "tegra264-gpio-aon", + .instance = 1, + .num_irqs_per_bank = 8, + .has_vm_support = true, +}; + +#define TEGRA264_UPHY_GPIO_PORT(_name, _bank, _port, _pins) \ + TEGRA_GPIO_PORT(TEGRA264_UPHY, _name, _bank, _port, _pins) + +static const struct tegra_gpio_port tegra264_uphy_ports[] = { + TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6), + TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8), + TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3), + TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 8), + TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4), +}; + +static const struct tegra_gpio_soc tegra264_uphy_soc = { + .num_ports = ARRAY_SIZE(tegra264_uphy_ports), + .ports = tegra264_uphy_ports, + .name = "tegra264-gpio-uphy", + .instance = 2, + .num_irqs_per_bank = 8, + .has_vm_support = true, +}; + #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins) @@ -1368,6 +1445,15 @@ static const struct of_device_id tegra186_gpio_of_match[] = { }, { .compatible = "nvidia,tegra256-gpio", .data = &tegra256_main_soc + }, { + .compatible = "nvidia,tegra264-gpio", + .data = &tegra264_main_soc + }, { + .compatible = "nvidia,tegra264-gpio-aon", + .data = &tegra264_aon_soc + }, { + .compatible = "nvidia,tegra264-gpio-uphy", + .data = &tegra264_uphy_soc }, { /* sentinel */ } From patchwork Fri Jan 23 06:41:40 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 2188055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 06:42:24.2605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3dfbb495-b6c8-43b0-86fa-08de5a4a913d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF8ECEC29A9 Add device tree nodes for MAIN, AON and UPHY GPIO controller instances. Signed-off-by: Prathamesh Shete Reviewed-by: Jon Hunter --- Changes in v2: * Update Tegra264 GPIO nodes to use “wakeup-parent”. --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 88 ++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index f137565da804..cf4de2c517fa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3277,6 +3277,50 @@ status = "disabled"; }; + gpio_main: gpio@c300000 { + compatible = "nvidia,tegra264-gpio"; + reg = <0x00 0x0c300000 0x0 0x4000>, + <0x00 0x0c310000 0x0 0x4000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + serial@c4e0000 { compatible = "nvidia,tegra264-utc"; reg = <0x0 0x0c4e0000 0x0 0x8000>, @@ -3347,6 +3391,22 @@ #interrupt-cells = <2>; interrupt-controller; }; + + gpio_aon: gpio@cf00000 { + compatible = "nvidia,tegra264-gpio-aon"; + reg = <0x0 0x0cf00000 0x0 0x10000>, + <0x0 0x0cf10000 0x0 0x1000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; /* TOP_MMIO */ @@ -3726,6 +3786,34 @@ ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */ <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */ + + gpio_uphy: gpio@8300000 { + compatible = "nvidia,tegra264-gpio-uphy"; + reg = <0x00 0x08300000 0x0 0x2000>, + <0x00 0x08310000 0x0 0x2000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; cpus {