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NXP LPC32xx Motor Control PWM has an interrupt line shared with TIMER4, and the interrupt may be used to report events from programmable counters e.g. timer counter limit (period), match counter (pulse-width), or from counters on input lines of PWM channels. As a reference and for more details see NXP LPC32xx User Manual, table 595. Signed-off-by: Vladimir Zapolskiy --- .../devicetree/bindings/pwm/nxp,lpc3220-pwm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/nxp,lpc3220-pwm.yaml b/Documentation/devicetree/bindings/pwm/nxp,lpc3220-pwm.yaml index cdd83ac29caf..53520f005acb 100644 --- a/Documentation/devicetree/bindings/pwm/nxp,lpc3220-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/nxp,lpc3220-pwm.yaml @@ -32,6 +32,16 @@ required: allOf: - $ref: pwm.yaml# + - if: + properties: + compatible: + contains: + enum: + - nxp,lpc3220-motor-pwm + then: + properties: + interrupts: + maxItems: 1 unevaluatedProperties: false From patchwork Sat Jan 10 01:45:24 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 2182216 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Sat, 10 Jan 2026 01:45:43 +0000 (UTC) From: Vladimir Zapolskiy To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: Piotr Wojtaszczyk , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] arm: dts: lpc32xx: add interrupts property to Motor Control PWM Date: Sat, 10 Jan 2026 03:45:24 +0200 Message-ID: <20260110014524.3379187-3-vz@mleia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260110014524.3379187-1-vz@mleia.com> References: <20260110014524.3379187-1-vz@mleia.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-49551924 X-CRM114-CacheID: sfid-20260110_014544_070900_8715560B X-CRM114-Status: UNSURE ( 9.46 ) X-CRM114-Notice: Please train this message. Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt controller, the interrupt serves as period (timer limit), pulse-width (match) and capture event interrupt. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 7fa91d1ac9ea..e94df78def18 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -322,6 +322,7 @@ i2c2: i2c@400a8000 { mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled";