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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:38:49 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 1/9] pwm: tiehrpwm: prefix register and field definitions Date: Thu, 27 Nov 2025 21:36:26 -0300 Message-ID: <20251128003634.247529-2-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Prefix all eHRPWM register offsets, bitfields and related constants with the TIEHRPWM_ prefix to make their origin explicit and avoid clashes with other PWM drivers or platforms. While at it, update all users in pwm-tiehrpwm.c to use the new names, including the period tracking and prescaler helpers, without changing any underlying values. This patch is a mechanical rename-only change. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 257 +++++++++++++++++++------------------ 1 file changed, 131 insertions(+), 126 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 7a86cb090f76..b6020b2210db 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -17,77 +17,81 @@ /* EHRPWM registers and bits definitions */ /* Time base module registers */ -#define TBCTL 0x00 -#define TBPRD 0x0A - -#define TBCTL_PRDLD_MASK BIT(3) -#define TBCTL_PRDLD_SHDW 0 -#define TBCTL_PRDLD_IMDT BIT(3) -#define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ - BIT(8) | BIT(7)) -#define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) -#define TBCTL_CTRMODE_UP 0 -#define TBCTL_CTRMODE_DOWN BIT(0) -#define TBCTL_CTRMODE_UPDOWN BIT(1) -#define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) - -#define TBCTL_HSPCLKDIV_SHIFT 7 -#define TBCTL_CLKDIV_SHIFT 10 - -#define CLKDIV_MAX 7 -#define HSPCLKDIV_MAX 7 -#define PERIOD_MAX 0x10000 +#define TIEHRPWM_TBCTL 0x00 +#define TIEHRPWM_TBPRD 0x0A + +#define TIEHRPWM_TBCTL_PRDLD_MASK BIT(3) +#define TIEHRPWM_TBCTL_PRDLD_SHDW 0 +#define TIEHRPWM_TBCTL_PRDLD_IMDT BIT(3) +#define TIEHRPWM_TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ + BIT(8) | BIT(7)) +#define TIEHRPWM_TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) +#define TIEHRPWM_TBCTL_CTRMODE_UP 0 +#define TIEHRPWM_TBCTL_CTRMODE_DOWN BIT(0) +#define TIEHRPWM_TBCTL_CTRMODE_UPDOWN BIT(1) +#define TIEHRPWM_TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) + +#define TIEHRPWM_TBCTL_HSPCLKDIV_SHIFT 7 +#define TIEHRPWM_TBCTL_CLKDIV_SHIFT 10 + +#define TIEHRPWM_CLKDIV_MAX 7 +#define TIEHRPWM_HSPCLKDIV_MAX 7 +#define TIEHRPWM_PERIOD_MAX 0x10000 /* compare module registers */ -#define CMPA 0x12 -#define CMPB 0x14 +#define TIEHRPWM_CMPA 0x12 +#define TIEHRPWM_CMPB 0x14 /* Action qualifier module registers */ -#define AQCTLA 0x16 -#define AQCTLB 0x18 -#define AQSFRC 0x1A -#define AQCSFRC 0x1C - -#define AQCTL_CBU_MASK (BIT(9) | BIT(8)) -#define AQCTL_CBU_FRCLOW BIT(8) -#define AQCTL_CBU_FRCHIGH BIT(9) -#define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) -#define AQCTL_CAU_MASK (BIT(5) | BIT(4)) -#define AQCTL_CAU_FRCLOW BIT(4) -#define AQCTL_CAU_FRCHIGH BIT(5) -#define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) -#define AQCTL_PRD_MASK (BIT(3) | BIT(2)) -#define AQCTL_PRD_FRCLOW BIT(2) -#define AQCTL_PRD_FRCHIGH BIT(3) -#define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) -#define AQCTL_ZRO_MASK (BIT(1) | BIT(0)) -#define AQCTL_ZRO_FRCLOW BIT(0) -#define AQCTL_ZRO_FRCHIGH BIT(1) -#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) - -#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_ZRO_FRCHIGH) -#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_ZRO_FRCLOW) -#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_ZRO_FRCHIGH) -#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_ZRO_FRCLOW) - -#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) -#define AQSFRC_RLDCSF_ZRO 0 -#define AQSFRC_RLDCSF_PRD BIT(6) -#define AQSFRC_RLDCSF_ZROPRD BIT(7) -#define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) - -#define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) -#define AQCSFRC_CSFB_FRCDIS 0 -#define AQCSFRC_CSFB_FRCLOW BIT(2) -#define AQCSFRC_CSFB_FRCHIGH BIT(3) -#define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) -#define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) -#define AQCSFRC_CSFA_FRCDIS 0 -#define AQCSFRC_CSFA_FRCLOW BIT(0) -#define AQCSFRC_CSFA_FRCHIGH BIT(1) -#define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) - -#define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ +#define TIEHRPWM_AQCTLA 0x16 +#define TIEHRPWM_AQCTLB 0x18 +#define TIEHRPWM_AQSFRC 0x1A +#define TIEHRPWM_AQCSFRC 0x1C + +#define TIEHRPWM_AQCTL_CBU_MASK (BIT(9) | BIT(8)) +#define TIEHRPWM_AQCTL_CBU_FRCLOW BIT(8) +#define TIEHRPWM_AQCTL_CBU_FRCHIGH BIT(9) +#define TIEHRPWM_AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) +#define TIEHRPWM_AQCTL_CAU_MASK (BIT(5) | BIT(4)) +#define TIEHRPWM_AQCTL_CAU_FRCLOW BIT(4) +#define TIEHRPWM_AQCTL_CAU_FRCHIGH BIT(5) +#define TIEHRPWM_AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) +#define TIEHRPWM_AQCTL_PRD_MASK (BIT(3) | BIT(2)) +#define TIEHRPWM_AQCTL_PRD_FRCLOW BIT(2) +#define TIEHRPWM_AQCTL_PRD_FRCHIGH BIT(3) +#define TIEHRPWM_AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) +#define TIEHRPWM_AQCTL_ZRO_MASK (BIT(1) | BIT(0)) +#define TIEHRPWM_AQCTL_ZRO_FRCLOW BIT(0) +#define TIEHRPWM_AQCTL_ZRO_FRCHIGH BIT(1) +#define TIEHRPWM_AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) + +#define TIEHRPWM_AQCTL_CHANA_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ + TIEHRPWM_AQCTL_ZRO_FRCHIGH) +#define TIEHRPWM_AQCTL_CHANA_POLINVERSED (TIEHRPWM_AQCTL_CAU_FRCHIGH | \ + TIEHRPWM_AQCTL_ZRO_FRCLOW) +#define TIEHRPWM_AQCTL_CHANB_POLNORMAL (TIEHRPWM_AQCTL_CBU_FRCLOW | \ + TIEHRPWM_AQCTL_ZRO_FRCHIGH) +#define TIEHRPWM_AQCTL_CHANB_POLINVERSED (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ + TIEHRPWM_AQCTL_ZRO_FRCLOW) + +#define TIEHRPWM_AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) +#define TIEHRPWM_AQSFRC_RLDCSF_ZRO 0 +#define TIEHRPWM_AQSFRC_RLDCSF_PRD BIT(6) +#define TIEHRPWM_AQSFRC_RLDCSF_ZROPRD BIT(7) +#define TIEHRPWM_AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) + +#define TIEHRPWM_AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) +#define TIEHRPWM_AQCSFRC_CSFB_FRCDIS 0 +#define TIEHRPWM_AQCSFRC_CSFB_FRCLOW BIT(2) +#define TIEHRPWM_AQCSFRC_CSFB_FRCHIGH BIT(3) +#define TIEHRPWM_AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) +#define TIEHRPWM_AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) +#define TIEHRPWM_AQCSFRC_CSFA_FRCDIS 0 +#define TIEHRPWM_AQCSFRC_CSFA_FRCLOW BIT(0) +#define TIEHRPWM_AQCSFRC_CSFA_FRCHIGH BIT(1) +#define TIEHRPWM_AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) + +#define TIEHRPWM_NUM_PWM_CHANNEL 2 /* EHRPWM channels */ struct ehrpwm_context { u16 tbctl; @@ -103,7 +107,7 @@ struct ehrpwm_context { struct ehrpwm_pwm_chip { unsigned long clk_rate; void __iomem *mmio_base; - unsigned long period_cycles[NUM_PWM_CHANNEL]; + unsigned long period_cycles[TIEHRPWM_NUM_PWM_CHANNEL]; struct clk *tbclk; struct ehrpwm_context ctx; }; @@ -146,8 +150,8 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, { unsigned int clkdiv, hspclkdiv; - for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { - for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) { + for (clkdiv = 0; clkdiv <= TIEHRPWM_CLKDIV_MAX; clkdiv++) { + for (hspclkdiv = 0; hspclkdiv <= TIEHRPWM_HSPCLKDIV_MAX; hspclkdiv++) { /* * calculations for prescaler value : * prescale_div = HSPCLKDIVIDER * CLKDIVIDER. @@ -162,8 +166,8 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, *prescale_div = (1 << clkdiv) * (hspclkdiv ? (hspclkdiv * 2) : 1); if (*prescale_div >= rqst_prescaler) { - *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | - (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT); + *tb_clk_div = (clkdiv << TIEHRPWM_TBCTL_CLKDIV_SHIFT) | + (hspclkdiv << TIEHRPWM_TBCTL_HSPCLKDIV_SHIFT); return 0; } } @@ -204,7 +208,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * Period values should be same for multiple PWM channels as IP uses * same period register for multiple channels. */ - for (i = 0; i < NUM_PWM_CHANNEL; i++) { + for (i = 0; i < TIEHRPWM_NUM_PWM_CHANNEL; i++) { if (pc->period_cycles[i] && (pc->period_cycles[i] != period_cycles)) { /* @@ -224,7 +228,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pc->period_cycles[pwm->hwpwm] = period_cycles; /* Configure clock prescaler to support Low frequency PWM wave */ - if (set_prescale_div(DIV_ROUND_UP(period_cycles, PERIOD_MAX), &ps_divval, + if (set_prescale_div(DIV_ROUND_UP(period_cycles, TIEHRPWM_PERIOD_MAX), &ps_divval, &tb_divval)) { dev_err(pwmchip_parent(chip), "Unsupported values\n"); return -EINVAL; @@ -240,52 +244,53 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pm_runtime_get_sync(pwmchip_parent(chip)); /* Update clock prescaler values */ - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_CLKDIV_MASK, tb_divval); if (pwm->hwpwm == 1) { /* Channel 1 configured with compare B register */ - cmp_reg = CMPB; + cmp_reg = TIEHRPWM_CMPB; - aqctl_reg = AQCTLB; - aqctl_mask = AQCTL_CBU_MASK; + aqctl_reg = TIEHRPWM_AQCTLB; + aqctl_mask = TIEHRPWM_AQCTL_CBU_MASK; if (polarity == PWM_POLARITY_INVERSED) - aqctl_val = AQCTL_CHANB_POLINVERSED; + aqctl_val = TIEHRPWM_AQCTL_CHANB_POLINVERSED; else - aqctl_val = AQCTL_CHANB_POLNORMAL; + aqctl_val = TIEHRPWM_AQCTL_CHANB_POLNORMAL; /* if duty_cycle is big, don't toggle on CBU */ if (duty_cycles > period_cycles) - aqctl_val &= ~AQCTL_CBU_MASK; + aqctl_val &= ~TIEHRPWM_AQCTL_CBU_MASK; } else { /* Channel 0 configured with compare A register */ - cmp_reg = CMPA; + cmp_reg = TIEHRPWM_CMPA; - aqctl_reg = AQCTLA; - aqctl_mask = AQCTL_CAU_MASK; + aqctl_reg = TIEHRPWM_AQCTLA; + aqctl_mask = TIEHRPWM_AQCTL_CAU_MASK; if (polarity == PWM_POLARITY_INVERSED) - aqctl_val = AQCTL_CHANA_POLINVERSED; + aqctl_val = TIEHRPWM_AQCTL_CHANA_POLINVERSED; else - aqctl_val = AQCTL_CHANA_POLNORMAL; + aqctl_val = TIEHRPWM_AQCTL_CHANA_POLNORMAL; /* if duty_cycle is big, don't toggle on CAU */ if (duty_cycles > period_cycles) - aqctl_val &= ~AQCTL_CAU_MASK; + aqctl_val &= ~TIEHRPWM_AQCTL_CAU_MASK; } - aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK; + aqctl_mask |= TIEHRPWM_AQCTL_PRD_MASK | TIEHRPWM_AQCTL_ZRO_MASK; ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); /* Configure shadow loading on Period register */ - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_PRDLD_MASK, + TIEHRPWM_TBCTL_PRDLD_SHDW); - ehrpwm_write(pc->mmio_base, TBPRD, period_cycles - 1); + ehrpwm_write(pc->mmio_base, TIEHRPWM_TBPRD, period_cycles - 1); /* Configure ehrpwm counter for up-count mode */ - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, - TBCTL_CTRMODE_UP); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_CTRMODE_MASK, + TIEHRPWM_TBCTL_CTRMODE_UP); if (!(duty_cycles > period_cycles)) ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); @@ -306,18 +311,18 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) /* Disabling Action Qualifier on PWM output */ if (pwm->hwpwm) { - aqcsfrc_val = AQCSFRC_CSFB_FRCDIS; - aqcsfrc_mask = AQCSFRC_CSFB_MASK; + aqcsfrc_val = TIEHRPWM_AQCSFRC_CSFB_FRCDIS; + aqcsfrc_mask = TIEHRPWM_AQCSFRC_CSFB_MASK; } else { - aqcsfrc_val = AQCSFRC_CSFA_FRCDIS; - aqcsfrc_mask = AQCSFRC_CSFA_MASK; + aqcsfrc_val = TIEHRPWM_AQCSFRC_CSFA_FRCDIS; + aqcsfrc_mask = TIEHRPWM_AQCSFRC_CSFA_MASK; } /* Changes to shadow mode */ - ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, - AQSFRC_RLDCSF_ZRO); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_AQSFRC, TIEHRPWM_AQSFRC_RLDCSF_MASK, + TIEHRPWM_AQSFRC_RLDCSF_ZRO); - ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_AQCSFRC, aqcsfrc_mask, aqcsfrc_val); /* Enable TBCLK */ ret = clk_enable(pc->tbclk); @@ -337,25 +342,25 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) /* Action Qualifier puts PWM output low forcefully */ if (pwm->hwpwm) { - aqcsfrc_val = AQCSFRC_CSFB_FRCLOW; - aqcsfrc_mask = AQCSFRC_CSFB_MASK; + aqcsfrc_val = TIEHRPWM_AQCSFRC_CSFB_FRCLOW; + aqcsfrc_mask = TIEHRPWM_AQCSFRC_CSFB_MASK; } else { - aqcsfrc_val = AQCSFRC_CSFA_FRCLOW; - aqcsfrc_mask = AQCSFRC_CSFA_MASK; + aqcsfrc_val = TIEHRPWM_AQCSFRC_CSFA_FRCLOW; + aqcsfrc_mask = TIEHRPWM_AQCSFRC_CSFA_MASK; } /* Update shadow register first before modifying active register */ - ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, - AQSFRC_RLDCSF_ZRO); - ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_AQSFRC, TIEHRPWM_AQSFRC_RLDCSF_MASK, + TIEHRPWM_AQSFRC_RLDCSF_ZRO); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_AQCSFRC, aqcsfrc_mask, aqcsfrc_val); /* * Changes to immediate action on Action Qualifier. This puts * Action Qualifier control on PWM output from next TBCLK */ - ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, - AQSFRC_RLDCSF_IMDT); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_AQSFRC, TIEHRPWM_AQSFRC_RLDCSF_MASK, + TIEHRPWM_AQSFRC_RLDCSF_IMDT); - ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_AQCSFRC, aqcsfrc_mask, aqcsfrc_val); /* Disabling TBCLK on PWM disable */ clk_disable(pc->tbclk); @@ -421,7 +426,7 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) struct clk *clk; int ret; - chip = devm_pwmchip_alloc(&pdev->dev, NUM_PWM_CHANNEL, sizeof(*pc)); + chip = devm_pwmchip_alloc(&pdev->dev, TIEHRPWM_NUM_PWM_CHANNEL, sizeof(*pc)); if (IS_ERR(chip)) return PTR_ERR(chip); pc = to_ehrpwm_pwm_chip(chip); @@ -495,14 +500,14 @@ static void ehrpwm_pwm_save_context(struct pwm_chip *chip) pm_runtime_get_sync(pwmchip_parent(chip)); - pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); - pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); - pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); - pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB); - pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA); - pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB); - pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC); - pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC); + pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TIEHRPWM_TBCTL); + pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TIEHRPWM_TBPRD); + pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, TIEHRPWM_CMPA); + pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, TIEHRPWM_CMPB); + pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, TIEHRPWM_AQCTLA); + pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, TIEHRPWM_AQCTLB); + pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, TIEHRPWM_AQSFRC); + pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, TIEHRPWM_AQCSFRC); pm_runtime_put_sync(pwmchip_parent(chip)); } @@ -511,14 +516,14 @@ static void ehrpwm_pwm_restore_context(struct pwm_chip *chip) { struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); - ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd); - ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa); - ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb); - ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla); - ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb); - ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc); - ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc); - ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl); + ehrpwm_write(pc->mmio_base, TIEHRPWM_TBPRD, pc->ctx.tbprd); + ehrpwm_write(pc->mmio_base, TIEHRPWM_CMPA, pc->ctx.cmpa); + ehrpwm_write(pc->mmio_base, TIEHRPWM_CMPB, pc->ctx.cmpb); + ehrpwm_write(pc->mmio_base, TIEHRPWM_AQCTLA, pc->ctx.aqctla); + ehrpwm_write(pc->mmio_base, TIEHRPWM_AQCTLB, pc->ctx.aqctlb); + ehrpwm_write(pc->mmio_base, TIEHRPWM_AQSFRC, pc->ctx.aqsfrc); + ehrpwm_write(pc->mmio_base, TIEHRPWM_AQCSFRC, pc->ctx.aqcsfrc); + ehrpwm_write(pc->mmio_base, TIEHRPWM_TBCTL, pc->ctx.tbctl); } static int ehrpwm_pwm_suspend(struct device *dev) From patchwork Fri Nov 28 00:36:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:38:54 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 2/9] pwm: tiehrpwm: drop _MASK suffix from TBCTL PRDLD field Date: Thu, 27 Nov 2025 21:36:27 -0300 Message-ID: <20251128003634.247529-3-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rename TIEHRPWM_TBCTL_PRDLD_MASK to TIEHRPWM_TBCTL_PRDLD so the macro name describes the PRDLD field itself instead of carrying a _MASK suffix. Update the single user in ehrpwm_pwm_config() accordingly. The value of the bit definition is unchanged. No functional change. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index b6020b2210db..f8625394c056 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -20,7 +20,7 @@ #define TIEHRPWM_TBCTL 0x00 #define TIEHRPWM_TBPRD 0x0A -#define TIEHRPWM_TBCTL_PRDLD_MASK BIT(3) +#define TIEHRPWM_TBCTL_PRDLD BIT(3) #define TIEHRPWM_TBCTL_PRDLD_SHDW 0 #define TIEHRPWM_TBCTL_PRDLD_IMDT BIT(3) #define TIEHRPWM_TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ @@ -283,7 +283,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); /* Configure shadow loading on Period register */ - ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_PRDLD_MASK, + ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_PRDLD, TIEHRPWM_TBCTL_PRDLD_SHDW); ehrpwm_write(pc->mmio_base, TIEHRPWM_TBPRD, period_cycles - 1); From patchwork Fri Nov 28 00:36:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:38:57 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 3/9] pwm: tiehrpwm: use GENMASK() and FIELD_PREP() for register fields Date: Thu, 27 Nov 2025 21:36:28 -0300 Message-ID: <20251128003634.247529-4-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert the TIEHRPWM TBCTL, AQCTL, AQSFRC and AQCSFRC field definitions to use GENMASK() and FIELD_PREP() instead of open-coded bit masks and shifted literals. This makes the eHRPWM register layout more explicit, reduces hand-rolled bit arithmetic and aligns the driver with common kernel bitfield patterns. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 88 ++++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 41 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index f8625394c056..0802f0553587 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -13,6 +13,7 @@ #include #include #include +#include /* EHRPWM registers and bits definitions */ @@ -21,15 +22,16 @@ #define TIEHRPWM_TBPRD 0x0A #define TIEHRPWM_TBCTL_PRDLD BIT(3) -#define TIEHRPWM_TBCTL_PRDLD_SHDW 0 -#define TIEHRPWM_TBCTL_PRDLD_IMDT BIT(3) -#define TIEHRPWM_TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ - BIT(8) | BIT(7)) -#define TIEHRPWM_TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) -#define TIEHRPWM_TBCTL_CTRMODE_UP 0 -#define TIEHRPWM_TBCTL_CTRMODE_DOWN BIT(0) -#define TIEHRPWM_TBCTL_CTRMODE_UPDOWN BIT(1) -#define TIEHRPWM_TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) +#define TIEHRPWM_TBCTL_PRDLD_SHDW FIELD_PREP(TIEHRPWM_TBCTL_PRDLD, 0) +#define TIEHRPWM_TBCTL_PRDLD_IMDT FIELD_PREP(TIEHRPWM_TBCTL_PRDLD, 1) + +#define TIEHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 7) + +#define TIEHRPWM_TBCTL_CTRMODE_MASK GENMASK(1, 0) +#define TIEHRPWM_TBCTL_CTRMODE_UP FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 0) +#define TIEHRPWM_TBCTL_CTRMODE_DOWN FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 1) +#define TIEHRPWM_TBCTL_CTRMODE_UPDOWN FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 2) +#define TIEHRPWM_TBCTL_CTRMODE_FREEZE FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 3) #define TIEHRPWM_TBCTL_HSPCLKDIV_SHIFT 7 #define TIEHRPWM_TBCTL_CLKDIV_SHIFT 10 @@ -48,22 +50,25 @@ #define TIEHRPWM_AQSFRC 0x1A #define TIEHRPWM_AQCSFRC 0x1C -#define TIEHRPWM_AQCTL_CBU_MASK (BIT(9) | BIT(8)) -#define TIEHRPWM_AQCTL_CBU_FRCLOW BIT(8) -#define TIEHRPWM_AQCTL_CBU_FRCHIGH BIT(9) -#define TIEHRPWM_AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) -#define TIEHRPWM_AQCTL_CAU_MASK (BIT(5) | BIT(4)) -#define TIEHRPWM_AQCTL_CAU_FRCLOW BIT(4) -#define TIEHRPWM_AQCTL_CAU_FRCHIGH BIT(5) -#define TIEHRPWM_AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) -#define TIEHRPWM_AQCTL_PRD_MASK (BIT(3) | BIT(2)) -#define TIEHRPWM_AQCTL_PRD_FRCLOW BIT(2) -#define TIEHRPWM_AQCTL_PRD_FRCHIGH BIT(3) -#define TIEHRPWM_AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) -#define TIEHRPWM_AQCTL_ZRO_MASK (BIT(1) | BIT(0)) -#define TIEHRPWM_AQCTL_ZRO_FRCLOW BIT(0) -#define TIEHRPWM_AQCTL_ZRO_FRCHIGH BIT(1) -#define TIEHRPWM_AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) +#define TIEHRPWM_AQCTL_CBU_MASK GENMASK(9, 8) +#define TIEHRPWM_AQCTL_CBU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 1) +#define TIEHRPWM_AQCTL_CBU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 2) +#define TIEHRPWM_AQCTL_CBU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 3) + +#define TIEHRPWM_AQCTL_CAU_MASK GENMASK(5, 4) +#define TIEHRPWM_AQCTL_CAU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 1) +#define TIEHRPWM_AQCTL_CAU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 2) +#define TIEHRPWM_AQCTL_CAU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 3) + +#define TIEHRPWM_AQCTL_PRD_MASK GENMASK(3, 2) +#define TIEHRPWM_AQCTL_PRD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 1) +#define TIEHRPWM_AQCTL_PRD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 2) +#define TIEHRPWM_AQCTL_PRD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 3) + +#define TIEHRPWM_AQCTL_ZRO_MASK GENMASK(1, 0) +#define TIEHRPWM_AQCTL_ZRO_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 1) +#define TIEHRPWM_AQCTL_ZRO_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 2) +#define TIEHRPWM_AQCTL_ZRO_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 3) #define TIEHRPWM_AQCTL_CHANA_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ TIEHRPWM_AQCTL_ZRO_FRCHIGH) @@ -74,22 +79,23 @@ #define TIEHRPWM_AQCTL_CHANB_POLINVERSED (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ TIEHRPWM_AQCTL_ZRO_FRCLOW) -#define TIEHRPWM_AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) -#define TIEHRPWM_AQSFRC_RLDCSF_ZRO 0 -#define TIEHRPWM_AQSFRC_RLDCSF_PRD BIT(6) -#define TIEHRPWM_AQSFRC_RLDCSF_ZROPRD BIT(7) -#define TIEHRPWM_AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) - -#define TIEHRPWM_AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) -#define TIEHRPWM_AQCSFRC_CSFB_FRCDIS 0 -#define TIEHRPWM_AQCSFRC_CSFB_FRCLOW BIT(2) -#define TIEHRPWM_AQCSFRC_CSFB_FRCHIGH BIT(3) -#define TIEHRPWM_AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) -#define TIEHRPWM_AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) -#define TIEHRPWM_AQCSFRC_CSFA_FRCDIS 0 -#define TIEHRPWM_AQCSFRC_CSFA_FRCLOW BIT(0) -#define TIEHRPWM_AQCSFRC_CSFA_FRCHIGH BIT(1) -#define TIEHRPWM_AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) +#define TIEHRPWM_AQSFRC_RLDCSF_MASK GENMASK(7, 6) +#define TIEHRPWM_AQSFRC_RLDCSF_ZRO FIELD_PREP(TIEHRPWM_AQSFRC_RLDCSF_MASK, 0) +#define TIEHRPWM_AQSFRC_RLDCSF_PRD FIELD_PREP(TIEHRPWM_AQSFRC_RLDCSF_MASK, 1) +#define TIEHRPWM_AQSFRC_RLDCSF_ZROPRD FIELD_PREP(TIEHRPWM_AQSFRC_RLDCSF_MASK, 2) +#define TIEHRPWM_AQSFRC_RLDCSF_IMDT FIELD_PREP(TIEHRPWM_AQSFRC_RLDCSF_MASK, 3) + +#define TIEHRPWM_AQCSFRC_CSFB_MASK GENMASK(3, 2) +#define TIEHRPWM_AQCSFRC_CSFB_FRCDIS FIELD_PREP(TIEHRPWM_AQCSFRC_CSFB_MASK, 0) +#define TIEHRPWM_AQCSFRC_CSFB_FRCLOW FIELD_PREP(TIEHRPWM_AQCSFRC_CSFB_MASK, 1) +#define TIEHRPWM_AQCSFRC_CSFB_FRCHIGH FIELD_PREP(TIEHRPWM_AQCSFRC_CSFB_MASK, 2) +#define TIEHRPWM_AQCSFRC_CSFB_DISSWFRC FIELD_PREP(TIEHRPWM_AQCSFRC_CSFB_MASK, 3) + +#define TIEHRPWM_AQCSFRC_CSFA_MASK GENMASK(1, 0) +#define TIEHRPWM_AQCSFRC_CSFA_FRCDIS FIELD_PREP(TIEHRPWM_AQCSFRC_CSFA_MASK, 0) +#define TIEHRPWM_AQCSFRC_CSFA_FRCLOW FIELD_PREP(TIEHRPWM_AQCSFRC_CSFA_MASK, 1) +#define TIEHRPWM_AQCSFRC_CSFA_FRCHIGH FIELD_PREP(TIEHRPWM_AQCSFRC_CSFA_MASK, 2) +#define TIEHRPWM_AQCSFRC_CSFA_DISSWFRC FIELD_PREP(TIEHRPWM_AQCSFRC_CSFA_MASK, 3) #define TIEHRPWM_NUM_PWM_CHANNEL 2 /* EHRPWM channels */ From patchwork Fri Nov 28 00:36:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:00 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 4/9] pwm: tiehrpwm: derive PERIOD_MAX from TBPRD field Date: Thu, 27 Nov 2025 21:36:29 -0300 Message-ID: <20251128003634.247529-5-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Replace the open-coded PERIOD_MAX constant (0x10000) with a definition derived from the TBPRD field layout. Introduce TIEHRPWM_TBPRD_TBPRD to describe the 16-bit TBPRD field and compute TIEHRPWM_PERIOD_MAX as FIELD_MAX(TIEHRPWM_TBPRD_TBPRD) + 1. This keeps the effective upper bound unchanged while tying it directly to the hardware register layout instead of a hard-coded literal. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 0802f0553587..4b8b4a9e7379 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -38,7 +38,9 @@ #define TIEHRPWM_CLKDIV_MAX 7 #define TIEHRPWM_HSPCLKDIV_MAX 7 -#define TIEHRPWM_PERIOD_MAX 0x10000 + +#define TIEHRPWM_TBPRD_TBPRD GENMASK(15, 0) +#define TIEHRPWM_PERIOD_MAX (FIELD_MAX(TIEHRPWM_TBPRD_TBPRD) + 1) /* compare module registers */ #define TIEHRPWM_CMPA 0x12 From patchwork Fri Nov 28 00:36:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:03 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 5/9] pwm: tiehrpwm: use FIELD_PREP() for prescaler fields Date: Thu, 27 Nov 2025 21:36:30 -0300 Message-ID: <20251128003634.247529-6-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Refactor TBCTL prescaler handling to use GENMASK() and FIELD_PREP() instead of open-coded shifts. Split the prescaler bits into TIEHRPWM_TBCTL_CLKDIV_MASK and TIEHRPWM_TBCTL_HSPCLKDIV_MASK and introduce TIEHRPWM_TBCTL_PRESCALE_MASK to cover both fields. Use FIELD_PREP() in set_prescale_div() to build the prescaler value, and update ehrpwm_modify() to clear and program both fields in a single call. The removed *_SHIFT macros are no longer needed. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 4b8b4a9e7379..41af1bf74cbb 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -25,7 +25,10 @@ #define TIEHRPWM_TBCTL_PRDLD_SHDW FIELD_PREP(TIEHRPWM_TBCTL_PRDLD, 0) #define TIEHRPWM_TBCTL_PRDLD_IMDT FIELD_PREP(TIEHRPWM_TBCTL_PRDLD, 1) -#define TIEHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 7) +#define TIEHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 10) +#define TIEHRPWM_TBCTL_HSPCLKDIV_MASK GENMASK(9, 7) +#define TIEHRPWM_TBCTL_PRESCALE_MASK (TIEHRPWM_TBCTL_CLKDIV_MASK | \ + TIEHRPWM_TBCTL_HSPCLKDIV_MASK) #define TIEHRPWM_TBCTL_CTRMODE_MASK GENMASK(1, 0) #define TIEHRPWM_TBCTL_CTRMODE_UP FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 0) @@ -33,9 +36,6 @@ #define TIEHRPWM_TBCTL_CTRMODE_UPDOWN FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 2) #define TIEHRPWM_TBCTL_CTRMODE_FREEZE FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 3) -#define TIEHRPWM_TBCTL_HSPCLKDIV_SHIFT 7 -#define TIEHRPWM_TBCTL_CLKDIV_SHIFT 10 - #define TIEHRPWM_CLKDIV_MAX 7 #define TIEHRPWM_HSPCLKDIV_MAX 7 @@ -174,8 +174,8 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, *prescale_div = (1 << clkdiv) * (hspclkdiv ? (hspclkdiv * 2) : 1); if (*prescale_div >= rqst_prescaler) { - *tb_clk_div = (clkdiv << TIEHRPWM_TBCTL_CLKDIV_SHIFT) | - (hspclkdiv << TIEHRPWM_TBCTL_HSPCLKDIV_SHIFT); + *tb_clk_div = FIELD_PREP(TIEHRPWM_TBCTL_CLKDIV_MASK, clkdiv) | + FIELD_PREP(TIEHRPWM_TBCTL_HSPCLKDIV_MASK, hspclkdiv); return 0; } } @@ -252,7 +252,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pm_runtime_get_sync(pwmchip_parent(chip)); /* Update clock prescaler values */ - ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_CLKDIV_MASK, tb_divval); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_PRESCALE_MASK, tb_divval); if (pwm->hwpwm == 1) { /* Channel 1 configured with compare B register */ From patchwork Fri Nov 28 00:36:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:09 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 6/9] pwm: tiehrpwm: factor out AQ force codes and polarity presets Date: Thu, 27 Nov 2025 21:36:31 -0300 Message-ID: <20251128003634.247529-7-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce named constants for the Action-Qualifier force action codes and use them to build the CAU/CAD/CBU/CBD/PRD/ZRO bitfield helpers instead of repeating hard-coded numeric values in each field. While at it, split the channel polarity presets into explicit up-count and down-count variants for both channels. This keeps the resulting AQCTL programming unchanged but makes the configuration easier to read and extend. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 85 +++++++++++++++++++++++++++++--------- 1 file changed, 65 insertions(+), 20 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 41af1bf74cbb..e8bcf1ffa770 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -52,33 +52,78 @@ #define TIEHRPWM_AQSFRC 0x1A #define TIEHRPWM_AQCSFRC 0x1C +/* Action-Qualifier force action codes (per 2-bit field) */ +#define TIEHRPWM_AQCTL_FRCLOW 0x1 +#define TIEHRPWM_AQCTL_FRCHIGH 0x2 +#define TIEHRPWM_AQCTL_FRCTOGGLE 0x3 + +/* Action-Qualifier bitfields for compare/period/zero events */ #define TIEHRPWM_AQCTL_CBU_MASK GENMASK(9, 8) -#define TIEHRPWM_AQCTL_CBU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 1) -#define TIEHRPWM_AQCTL_CBU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 2) -#define TIEHRPWM_AQCTL_CBU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 3) +#define TIEHRPWM_AQCTL_CBU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CBU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CBU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) + +#define TIEHRPWM_AQCTL_CBD_MASK GENMASK(11, 10) +#define TIEHRPWM_AQCTL_CBD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CBD_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CBD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CBD_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CBD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CBD_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) #define TIEHRPWM_AQCTL_CAU_MASK GENMASK(5, 4) -#define TIEHRPWM_AQCTL_CAU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 1) -#define TIEHRPWM_AQCTL_CAU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 2) -#define TIEHRPWM_AQCTL_CAU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 3) +#define TIEHRPWM_AQCTL_CAU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CAU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CAU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) + +#define TIEHRPWM_AQCTL_CAD_MASK GENMASK(7, 6) +#define TIEHRPWM_AQCTL_CAD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CAD_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CAD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CAD_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CAD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CAD_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) #define TIEHRPWM_AQCTL_PRD_MASK GENMASK(3, 2) -#define TIEHRPWM_AQCTL_PRD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 1) -#define TIEHRPWM_AQCTL_PRD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 2) -#define TIEHRPWM_AQCTL_PRD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 3) +#define TIEHRPWM_AQCTL_PRD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_PRD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_PRD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) #define TIEHRPWM_AQCTL_ZRO_MASK GENMASK(1, 0) -#define TIEHRPWM_AQCTL_ZRO_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 1) -#define TIEHRPWM_AQCTL_ZRO_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 2) -#define TIEHRPWM_AQCTL_ZRO_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 3) +#define TIEHRPWM_AQCTL_ZRO_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_ZRO_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_ZRO_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) + +/* Action-Qualifier polarity presets for up-count mode */ +#define TIEHRPWM_AQCTL_CHA_UP_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ + TIEHRPWM_AQCTL_ZRO_FRCHIGH) +#define TIEHRPWM_AQCTL_CHA_UP_POLINVERSE (TIEHRPWM_AQCTL_CAU_FRCHIGH | \ + TIEHRPWM_AQCTL_ZRO_FRCLOW) +#define TIEHRPWM_AQCTL_CHB_UP_POLNORMAL (TIEHRPWM_AQCTL_CBU_FRCLOW | \ + TIEHRPWM_AQCTL_ZRO_FRCHIGH) +#define TIEHRPWM_AQCTL_CHB_UP_POLINVERSE (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ + TIEHRPWM_AQCTL_ZRO_FRCLOW) -#define TIEHRPWM_AQCTL_CHANA_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ +/* Action-Qualifier polarity presets for down-count mode */ +#define TIEHRPWM_AQCTL_CHA_DN_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ TIEHRPWM_AQCTL_ZRO_FRCHIGH) -#define TIEHRPWM_AQCTL_CHANA_POLINVERSED (TIEHRPWM_AQCTL_CAU_FRCHIGH | \ +#define TIEHRPWM_AQCTL_CHA_DN_POLINVERSE (TIEHRPWM_AQCTL_CAU_FRCHIGH | \ TIEHRPWM_AQCTL_ZRO_FRCLOW) -#define TIEHRPWM_AQCTL_CHANB_POLNORMAL (TIEHRPWM_AQCTL_CBU_FRCLOW | \ +#define TIEHRPWM_AQCTL_CHB_DN_POLNORMAL (TIEHRPWM_AQCTL_CBU_FRCLOW | \ TIEHRPWM_AQCTL_ZRO_FRCHIGH) -#define TIEHRPWM_AQCTL_CHANB_POLINVERSED (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ +#define TIEHRPWM_AQCTL_CHB_DN_POLINVERSE (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ TIEHRPWM_AQCTL_ZRO_FRCLOW) #define TIEHRPWM_AQSFRC_RLDCSF_MASK GENMASK(7, 6) @@ -262,9 +307,9 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, aqctl_mask = TIEHRPWM_AQCTL_CBU_MASK; if (polarity == PWM_POLARITY_INVERSED) - aqctl_val = TIEHRPWM_AQCTL_CHANB_POLINVERSED; + aqctl_val = TIEHRPWM_AQCTL_CHB_UP_POLINVERSE; else - aqctl_val = TIEHRPWM_AQCTL_CHANB_POLNORMAL; + aqctl_val = TIEHRPWM_AQCTL_CHB_UP_POLNORMAL; /* if duty_cycle is big, don't toggle on CBU */ if (duty_cycles > period_cycles) @@ -278,9 +323,9 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, aqctl_mask = TIEHRPWM_AQCTL_CAU_MASK; if (polarity == PWM_POLARITY_INVERSED) - aqctl_val = TIEHRPWM_AQCTL_CHANA_POLINVERSED; + aqctl_val = TIEHRPWM_AQCTL_CHA_UP_POLINVERSE; else - aqctl_val = TIEHRPWM_AQCTL_CHANA_POLNORMAL; + aqctl_val = TIEHRPWM_AQCTL_CHA_UP_POLNORMAL; /* if duty_cycle is big, don't toggle on CAU */ if (duty_cycles > period_cycles) From patchwork Fri Nov 28 00:36:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.39.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:11 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 7/9] pwm: tiehrpwm: unify AQ setup and cover compare-down events Date: Thu, 27 Nov 2025 21:36:32 -0300 Message-ID: <20251128003634.247529-8-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Refactor ehrpwm_pwm_config() to share the Action-Qualifier setup between channels A and B. Select the channel-specific compare register, AQCTL register and polarity presets (up/down, normal/inverse) once, then derive the AQCTL value from the requested polarity. While doing so, extend the AQCTL mask to include both up- and down-compare fields (CAU/CAD for channel A, CBU/CBD for channel B) and clear all compare actions when the duty cycle exceeds the period, instead of only masking CAU/CBU. For the currently used up-count mode this does not change the effective output waveform, but it keeps the compare-down configuration consistent with the compare-up presets and makes the logic easier to extend (e.g. to up-down modes) in future changes. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 52 ++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index e8bcf1ffa770..6a792faa62ce 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -242,6 +242,8 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, unsigned int i, cmp_reg; unsigned long long c; u16 aqctl_val, aqctl_mask; + u16 up_normal, up_inverse; + u16 dn_normal, dn_inverse; unsigned int aqctl_reg; if (period_ns > NSEC_PER_SEC) @@ -299,39 +301,39 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* Update clock prescaler values */ ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_PRESCALE_MASK, tb_divval); + /* Select channel-specific registers and presets once */ if (pwm->hwpwm == 1) { - /* Channel 1 configured with compare B register */ - cmp_reg = TIEHRPWM_CMPB; - + /* Channel B uses CMPB and AQCTLB */ + cmp_reg = TIEHRPWM_CMPB; aqctl_reg = TIEHRPWM_AQCTLB; - aqctl_mask = TIEHRPWM_AQCTL_CBU_MASK; - - if (polarity == PWM_POLARITY_INVERSED) - aqctl_val = TIEHRPWM_AQCTL_CHB_UP_POLINVERSE; - else - aqctl_val = TIEHRPWM_AQCTL_CHB_UP_POLNORMAL; - - /* if duty_cycle is big, don't toggle on CBU */ - if (duty_cycles > period_cycles) - aqctl_val &= ~TIEHRPWM_AQCTL_CBU_MASK; + aqctl_mask = TIEHRPWM_AQCTL_CBU_MASK | TIEHRPWM_AQCTL_CBD_MASK; + up_normal = TIEHRPWM_AQCTL_CHB_UP_POLNORMAL; + up_inverse = TIEHRPWM_AQCTL_CHB_UP_POLINVERSE; + dn_normal = TIEHRPWM_AQCTL_CHB_DN_POLNORMAL; + dn_inverse = TIEHRPWM_AQCTL_CHB_DN_POLINVERSE; } else { - /* Channel 0 configured with compare A register */ - cmp_reg = TIEHRPWM_CMPA; - + /* Channel A uses CMPA and AQCTLA */ + cmp_reg = TIEHRPWM_CMPA; aqctl_reg = TIEHRPWM_AQCTLA; - aqctl_mask = TIEHRPWM_AQCTL_CAU_MASK; + aqctl_mask = TIEHRPWM_AQCTL_CAU_MASK | TIEHRPWM_AQCTL_CAD_MASK; - if (polarity == PWM_POLARITY_INVERSED) - aqctl_val = TIEHRPWM_AQCTL_CHA_UP_POLINVERSE; - else - aqctl_val = TIEHRPWM_AQCTL_CHA_UP_POLNORMAL; - - /* if duty_cycle is big, don't toggle on CAU */ - if (duty_cycles > period_cycles) - aqctl_val &= ~TIEHRPWM_AQCTL_CAU_MASK; + up_normal = TIEHRPWM_AQCTL_CHA_UP_POLNORMAL; + up_inverse = TIEHRPWM_AQCTL_CHA_UP_POLINVERSE; + dn_normal = TIEHRPWM_AQCTL_CHA_DN_POLNORMAL; + dn_inverse = TIEHRPWM_AQCTL_CHA_DN_POLINVERSE; } + /* Select polarity (up + down) */ + if (polarity == PWM_POLARITY_INVERSED) + aqctl_val = up_inverse | dn_inverse; + else + aqctl_val = up_normal | dn_normal; + + /* If duty is larger than period, don't toggle on compare events */ + if (duty_cycles > period_cycles) + aqctl_val &= ~aqctl_mask; + aqctl_mask |= TIEHRPWM_AQCTL_PRD_MASK | TIEHRPWM_AQCTL_ZRO_MASK; ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); From patchwork Fri Nov 28 00:36:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:14 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 8/9] pwm: tiehrpwm: tidy period conflict check Date: Thu, 27 Nov 2025 21:36:33 -0300 Message-ID: <20251128003634.247529-9-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Tidy ehrpwm_pwm_config(): drop redundant parentheses and keep the period conflict condition on a single line to follow kernel style. This change addresses a style warning reported by checkpatch.pl. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 6a792faa62ce..d472d717abca 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -264,8 +264,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * same period register for multiple channels. */ for (i = 0; i < TIEHRPWM_NUM_PWM_CHANNEL; i++) { - if (pc->period_cycles[i] && - (pc->period_cycles[i] != period_cycles)) { + if (pc->period_cycles[i] && pc->period_cycles[i] != period_cycles) { /* * Allow channel to reconfigure period if no other * channels being configured. From patchwork Fri Nov 28 00:36:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael V. 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Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 9/9] pwm: tiehrpwm: handle already-running channels at probe Date: Thu, 27 Nov 2025 21:36:34 -0300 Message-ID: <20251128003634.247529-10-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some systems leave eHRPWM outputs running when Linux probes the driver, for example when firmware or the bootloader configured and enabled a channel before handing control to the kernel. So far, the driver always assumed both channels were disabled at probe time and started with zero tbclk and runtime PM references. Teach ehrpwm_pwm_probe() to take a best-effort snapshot of AQCSFRC and AQCTLA/B before touching clocks or runtime PM, and treat channels that are configured and not software-forced in AQCSFRC as "pre-enabled". For each such channel, take one tbclk enable and one pm_runtime_get_sync() reference so that later per-channel enable/disable paths cannot underflow the clock or runtime PM usage counts. If the eHRPWM block is power-gated or its clock is disabled while we probe, the AQ* registers are expected to read back as 0 and the driver will simply treat the instance as fully disabled, preserving the previous behaviour. Error paths unwind both tbclk and runtime PM references per channel to keep the reference counts balanced. This makes tiehrpwm robust when attaching to hardware that is already driving PWM outputs at probe time. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 81 +++++++++++++++++++++++++++++++++++--- 1 file changed, 75 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index d472d717abca..b2503a675484 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -478,13 +478,20 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) struct ehrpwm_pwm_chip *pc; struct pwm_chip *chip; struct clk *clk; - int ret; + int ret, ch_idx, ch_disable; + u16 aqcsfrc_reg, aqctla_reg, aqctlb_reg; + bool enabled_ch[TIEHRPWM_NUM_PWM_CHANNEL] = { false, false }; chip = devm_pwmchip_alloc(&pdev->dev, TIEHRPWM_NUM_PWM_CHANNEL, sizeof(*pc)); if (IS_ERR(chip)) return PTR_ERR(chip); + pc = to_ehrpwm_pwm_chip(chip); + pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pc->mmio_base)) + return PTR_ERR(pc->mmio_base); + clk = devm_clk_get(&pdev->dev, "fck"); if (IS_ERR(clk)) { if (of_device_is_compatible(np, "ti,am33xx-ecap")) { @@ -493,6 +500,22 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) } } + /* + * Best-effort snapshot of AQCSFRC/AQCTLx before touching clocks or + * runtime PM. If the eHRPWM block is power-gated or its clock is + * disabled these registers are expected to read as 0, which we + * interpret as "channel not configured / disabled". + */ + aqcsfrc_reg = ehrpwm_read(pc->mmio_base, TIEHRPWM_AQCSFRC); + aqctla_reg = ehrpwm_read(pc->mmio_base, TIEHRPWM_AQCTLA); + aqctlb_reg = ehrpwm_read(pc->mmio_base, TIEHRPWM_AQCTLB); + + if (aqctla_reg != 0 && !FIELD_GET(TIEHRPWM_AQCSFRC_CSFA_MASK, aqcsfrc_reg)) + enabled_ch[0] = true; + + if (aqctlb_reg != 0 && !FIELD_GET(TIEHRPWM_AQCSFRC_CSFB_MASK, aqcsfrc_reg)) + enabled_ch[1] = true; + if (IS_ERR(clk)) return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Failed to get fck\n"); @@ -504,10 +527,6 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) chip->ops = &ehrpwm_pwm_ops; - pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(pc->mmio_base)) - return PTR_ERR(pc->mmio_base); - /* Acquire tbclk for Time Base EHRPWM submodule */ pc->tbclk = devm_clk_get(&pdev->dev, "tbclk"); if (IS_ERR(pc->tbclk)) @@ -519,17 +538,67 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) return ret; } + /* + * For channels that were already running when we probed, take one + * tbclk enable per channel, so that later per-channel disable paths + * cannot underflow the clock reference count. + */ + for (ch_idx = 0; ch_idx < TIEHRPWM_NUM_PWM_CHANNEL; ch_idx++) { + if (enabled_ch[ch_idx]) { + ret = clk_enable(pc->tbclk); + if (ret) { + dev_err_probe(&pdev->dev, ret, + "clk_enable(tbclk) failed for ch %d\n", + ch_idx); + + for (ch_disable = 0; ch_disable < ch_idx; ch_disable++) { + if (enabled_ch[ch_disable]) + clk_disable(pc->tbclk); + } + + goto err_clk_unprepare; + } + } + } + ret = pwmchip_add(chip); if (ret < 0) { dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); - goto err_clk_unprepare; + goto err_disable_tbclk; } platform_set_drvdata(pdev, chip); pm_runtime_enable(&pdev->dev); + /* + * Treat channels that were configured and not software-forced at probe + * time as "pre-enabled": take a runtime PM reference so the eHRPWM block + * stays powered while such channels exist. Consumers still get/put PM + * on top of this bias via pwm_enable()/pwm_disable(). + */ + for (ch_idx = 0; ch_idx < TIEHRPWM_NUM_PWM_CHANNEL; ch_idx++) { + if (enabled_ch[ch_idx]) { + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) { + for (ch_disable = 0; ch_disable <= ch_idx; ch_disable++) { + if (enabled_ch[ch_disable]) + pm_runtime_put_noidle(&pdev->dev); + } + + pwmchip_remove(chip); + pm_runtime_disable(&pdev->dev); + goto err_disable_tbclk; + } + } + } + return 0; +err_disable_tbclk: + for (ch_idx = 0; ch_idx < TIEHRPWM_NUM_PWM_CHANNEL; ch_idx++) { + if (enabled_ch[ch_idx]) + clk_disable(pc->tbclk); + } err_clk_unprepare: clk_unprepare(pc->tbclk);