From patchwork Sat Sep 23 06:18:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 817768 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="J8nraHO9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xzgCc0mBXz9tWf for ; Sat, 23 Sep 2017 16:18:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750778AbdIWGSu (ORCPT ); Sat, 23 Sep 2017 02:18:50 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:33825 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750741AbdIWGSu (ORCPT ); Sat, 23 Sep 2017 02:18:50 -0400 Received: by mail-pf0-f195.google.com with SMTP id g65so1348210pfe.1; Fri, 22 Sep 2017 23:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=B55Jtl/UdWWlLcOGtXHV6ZA8DqznrUo5ydm9PdycNPg=; b=J8nraHO9VOjAhOyoh5d9+/pn4tpEJuo/0PGwK/hwlslhcWMJtzWFht5GlbDxKmOAx5 xUTPyNeZT9RDVHN2XE9sukfx6rbnRM+CNfz1aQM2lZA+wM79hreMcODUXSFMlSVVGcDz Mm2YwcA/kA0kFECbpORuOTIbPKhFM7kNtEK9QK08fqFZd0mNXePipY30arOGS7pV6Y6A RRzZR/tFq4Z46c3iNzeHUacwNyTaevMZqKJwRxBr3NLFuxJe9ozfQTNH8+V+YWprOHDB B+4TuY4R7I6xWXyuX5rUyLvwrWL8EIEcAKnDcPd44ceAqcp6fKMNzNAXgyna9GDYbf27 IsCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=B55Jtl/UdWWlLcOGtXHV6ZA8DqznrUo5ydm9PdycNPg=; b=TU1z3dJFmyHpjIwe+RNDgXtZIIauscDMcGyrMTFds4diEjJzW/3nlvnsTAnQgnlfJA VK1C3p6pMyGqcKibW26SDppOi60349uxiPhwebhkyelBR06m0R+/hEJ9TZeaspz1mUHZ 4PyRYXCzma++b0pe/nntx5MahEayz/hgJBK6m0W7ouuO0mNrkuqbPtqD6MdBG5l3LKXc YJMMc+bZIra/tTjw4aNmxHWeL+6vrTbW4HOpctcMme8qmUvIPJ8/fuiJ2LYbtmmFnogk 4x48iR31TJPK6uYaFnIb6OcDW036SdbALeK5ZkrD6vpTu8une/i41tEow91ogejYJQFC AOBQ== X-Gm-Message-State: AHPjjUg//4JV6UNvyafmNRcufZcLhIbD4je7E8AXaOk6e9w90Ofow6tB /QBxRA8QOd5f/12WrX2bVcI= X-Google-Smtp-Source: AOwi7QDGaYwUvd9idrnw0rIsOXalBYVjiVq+ZMHtru66W8YxKKFQEQd1VOz0nz7JlEBQNSPoP8j7Tw== X-Received: by 10.84.248.13 with SMTP id p13mr1282681pll.447.1506147529406; Fri, 22 Sep 2017 23:18:49 -0700 (PDT) Received: from localhost (198-0-214-85-static.hfc.comcastbusiness.net. [198.0.214.85]) by smtp.gmail.com with ESMTPSA id f13sm2188468pfj.127.2017.09.22.23.18.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Sep 2017 23:18:48 -0700 (PDT) From: Thierry Reding X-Google-Original-From: Thierry Reding To: Bjorn Helgaas Cc: Thierry Reding , Jonathan Hunter , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] PCI: tegra: Use generic accessors where possible Date: Fri, 22 Sep 2017 23:18:41 -0700 Message-Id: <20170923061841.6123-1-treding@nvidia.com> X-Mailer: git-send-email 2.14.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Tegra PCI host controller can generate configuration space accesses with byte, word and dword granularity for devices. Only root ports can't have their configuration space accessed in this way. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 9c40da54f88a..e8e1ddbaabc9 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -491,12 +491,32 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, return addr; } +static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + if (bus->number == 0) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + if (bus->number == 0) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + static struct pci_ops tegra_pcie_ops = { .add_bus = tegra_pcie_add_bus, .remove_bus = tegra_pcie_remove_bus, .map_bus = tegra_pcie_map_bus, - .read = pci_generic_config_read32, - .write = pci_generic_config_write32, + .read = tegra_pcie_config_read, + .write = tegra_pcie_config_write, }; static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)