From patchwork Fri May 25 06:20:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: xswang@marvell.com X-Patchwork-Id: 920261 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40sbvv11tVz9s08 for ; Fri, 25 May 2018 16:30:02 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9A741C21DF3; Fri, 25 May 2018 06:29:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8CE49C21DB6; Fri, 25 May 2018 06:29:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C070BC21BE5; Fri, 25 May 2018 06:29:06 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lists.denx.de (Postfix) with ESMTPS id 4849AC21C2C for ; Fri, 25 May 2018 06:29:06 +0000 (UTC) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w4P6PBFa026180; Thu, 24 May 2018 23:28:56 -0700 Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2j2kegvmyw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 May 2018 23:28:56 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 24 May 2018 23:28:54 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 24 May 2018 23:28:54 -0700 Received: from mshsrv05.marvell.com (unknown [10.38.120.46]) by maili.marvell.com (Postfix) with ESMTP id A9DBF3F703F; Thu, 24 May 2018 23:28:53 -0700 (PDT) From: To: Date: Fri, 25 May 2018 14:20:51 +0800 Message-ID: <1527229253-5912-1-git-send-email-xswang@marvell.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-05-25_02:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1805250078 Cc: Stefan Roese , Evan Wang Subject: [U-Boot] [PATCH v2 1/3] mvebu: pinctrl: sync compatible string with Linux 4.17-rc4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Evan Wang For pinctrl driver of mvebu, the compatible strings supported are defined differently from Linux version. The patch aligned the compatible string with Linux 4.17-rc4. Signed-off-by: Evan Wang Reviewed-by: Stefan Roese --- Changes in v2: - Add commit text. arch/arm/dts/armada-ap806.dtsi | 2 +- arch/arm/dts/armada-cp110-master.dtsi | 4 ++-- arch/arm/dts/armada-cp110-slave.dtsi | 2 +- .../pinctrl/marvell,mvebu-pinctrl.txt | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 8 ++++---- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi index e0d3016..ebdee51 100644 --- a/arch/arm/dts/armada-ap806.dtsi +++ b/arch/arm/dts/armada-ap806.dtsi @@ -141,7 +141,7 @@ }; ap_pinctl: ap-pinctl@6F4000 { - compatible = "marvell,armada-ap806-pinctrl"; + compatible = "marvell,ap806-pinctrl"; bank-name ="apn-806"; reg = <0x6F4000 0x10>; pin-count = <20>; diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 8c336f2..551d00d 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -120,8 +120,8 @@ cpm_pinctl: cpm-pinctl@440000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a70x0-pinctrl", - "marvell,a80x0-cp0-pinctrl"; + "marvell,armada-7k-pinctrl", + "marvell,armada-8k-cpm-pinctrl"; bank-name ="cp0-110"; reg = <0x440000 0x20>; pin-count = <63>; diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index 0cdb3d3..2ea9004 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -120,7 +120,7 @@ cps_pinctl: cps-pinctl@440000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a80x0-cp1-pinctrl"; + "marvell,armada-8k-cps-pinctrl"; bank-name ="cp1-110"; reg = <0x440000 0x20>; pin-count = <63>; diff --git a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt index 5f86c0a..1fc1bc6 100644 --- a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt @@ -6,10 +6,10 @@ mpp pins or group of pins and a mpp function common to all pins. Required properties for the pinctrl driver: - compatible: "marvell,mvebu-pinctrl", - "marvell,armada-ap806-pinctrl", - "marvell,a70x0-pinctrl", - "marvell,a80x0-cp0-pinctrl", - "marvell,a80x0-cp1-pinctrl" + "marvell,ap806-pinctrl", + "marvell,armada-7k-pinctrl", + "marvell,armada-8k-cpm-pinctrl", + "marvell,armada-8k-cps-pinctrl" - bank-name: A string defining the pinc controller bank name - reg: A pair of values defining the pin controller base address and the address space @@ -31,7 +31,7 @@ Example: config-space { pinctl: pinctl@6F4000 { compatible = "marvell,mvebu-pinctrl", - "marvell,armada-ap806-pinctrl"; + "marvell,ap806-pinctrl"; bank-name ="apn-806"; reg = <0x6F4000 0x10>; pin-count = <20>; @@ -52,8 +52,8 @@ Example: config-space { cpm_pinctl: pinctl@44000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a70x0-pinctrl", - "marvell,a80x0-cp0-pinctrl"; + "marvell,armada-7k-pinctrl", + "marvell,armada-8k-cpm-pinctrl"; bank-name ="cp0-110"; reg = <0x440000 0x20>; pin-count = <63>; @@ -89,7 +89,7 @@ Example: config-space { cps_pinctl: pinctl@44000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a80x0-cp1-pinctrl"; + "marvell,armada-8k-cps-pinctrl"; bank-name ="cp1-110"; reg = <0x440000 0x20>; pin-count = <63>; diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index ec19583..556bf78 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -162,10 +162,10 @@ static struct pinctrl_ops mvebu_pinctrl_ops = { static const struct udevice_id mvebu_pinctrl_ids[] = { { .compatible = "marvell,mvebu-pinctrl" }, - { .compatible = "marvell,armada-ap806-pinctrl" }, - { .compatible = "marvell,a70x0-pinctrl" }, - { .compatible = "marvell,a80x0-cp0-pinctrl" }, - { .compatible = "marvell,a80x0-cp1-pinctrl" }, + { .compatible = "marvell,ap806-pinctrl" }, + { .compatible = "marvell,armada-7k-pinctrl" }, + { .compatible = "marvell,armada-8k-cpm-pinctrl" }, + { .compatible = "marvell,armada-8k-cps-pinctrl" }, { } }; From patchwork Fri May 25 06:20:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: xswang@marvell.com X-Patchwork-Id: 920260 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40sbv60dXkz9s08 for ; Fri, 25 May 2018 16:29:22 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B05A5C21DF3; Fri, 25 May 2018 06:29:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B1EC0C21C27; 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Thu, 24 May 2018 23:28:56 -0700 Received: from mshsrv05.marvell.com (unknown [10.38.120.46]) by maili.marvell.com (Postfix) with ESMTP id 7CAA23F7040; Thu, 24 May 2018 23:28:55 -0700 (PDT) From: To: Date: Fri, 25 May 2018 14:20:52 +0800 Message-ID: <1527229253-5912-2-git-send-email-xswang@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527229253-5912-1-git-send-email-xswang@marvell.com> References: <1527229253-5912-1-git-send-email-xswang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-05-25_02:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1805250079 Cc: Stefan Roese , Evan Wang Subject: [U-Boot] [PATCH v2 2/3] mvebu: pinctrl: Add SD/eMMC PHY selector to the driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Konstantin Porotchkin When the pin control driver selects SD/eMMC function for a pin group, there is additional configuration to be done for this case - switch the PHY to work with SDHCI interface. This patch adds the missing functionality into the pin control driver. Signed-off-by: Konstantin Porotchkin Reviewed-by: Stefan Roese Signed-off-by: Evan Wang --- Changes in v2: None drivers/pinctrl/mvebu/pinctrl-mvebu.c | 59 +++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 556bf78..7d8a0b0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -17,8 +17,48 @@ #include #include "pinctrl-mvebu.h" +#define AP_EMMC_PHY_CTRL_REG 0x100 +#define CP_EMMC_PHY_CTRL_REG 0x424 +#define EMMC_PHY_CTRL_SDPHY_EN BIT(0) + +#define AP806_EMMC_CLK_PIN_ID 0 +#define AP806_EMMC_CLK_FUNC 0x1 +#define CP110_EMMC_CLK_PIN_ID 56 +#define CP110_EMMC_CLK_FUNC 0xe + DECLARE_GLOBAL_DATA_PTR; +/* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux + * To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux. + * eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC + * controller: + * - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer, + * - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller + * If pin function is set to eMMC/SD, then configure the eMMC/SD PHY + * muxltiplexer register to be on SDIO/eMMC controller + */ +void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func) +{ + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + struct mvebu_pinctrl_priv *priv = dev_get_priv(dev); + + if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) { + if ((pin == AP806_EMMC_CLK_PIN_ID) && + (func == AP806_EMMC_CLK_FUNC)) { + clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG, + EMMC_PHY_CTRL_SDPHY_EN); + } + } else if (!fdt_node_check_compatible(blob, node, + "marvell,armada-8k-cpm-pinctrl")) { + if ((pin == CP110_EMMC_CLK_PIN_ID) && + (func == CP110_EMMC_CLK_FUNC)) { + clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG, + EMMC_PHY_CTRL_SDPHY_EN); + } + } +} + /* * mvebu_pinctrl_set_state: configure pin functions. * @dev: the pinctrl device to be configured. @@ -48,9 +88,16 @@ int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config) function = fdtdec_get_int(blob, node, "marvell,function", 0xff); + /* + * Check if setup of PHY mux is needed for this pins group. + * Only the first pin id in array is tested, all the rest use the same + * pin function. + */ + mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function); + for (i = 0; i < pin_count; i++) { - int reg_offset; - int field_offset; + int reg_offset; + int field_offset; int pin = pin_arr[i]; if (function > priv->max_func) { @@ -97,6 +144,14 @@ static int mvebu_pinctrl_set_state_all(struct udevice *dev, return -EINVAL; } + /* Check if setup of PHY mux is needed for this pins group. */ + if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID) + mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID, + func_arr[AP806_EMMC_CLK_PIN_ID]); + else + mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID, + func_arr[CP110_EMMC_CLK_PIN_ID]); + for (pin = 0; pin < priv->pin_cnt; pin++) { int reg_offset; int field_offset; From patchwork Fri May 25 06:20:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: xswang@marvell.com X-Patchwork-Id: 920262 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40sbwS3jLvz9s19 for ; Fri, 25 May 2018 16:30:32 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2482BC21DD4; Fri, 25 May 2018 06:29:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 71BA5C21DE8; Fri, 25 May 2018 06:29:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CDD03C21C27; Fri, 25 May 2018 06:29:06 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lists.denx.de (Postfix) with ESMTPS id 46A8BC21C27 for ; Fri, 25 May 2018 06:29:06 +0000 (UTC) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w4P6OSSn025665; Thu, 24 May 2018 23:29:00 -0700 Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2j2kegvn06-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 May 2018 23:29:00 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 24 May 2018 23:28:58 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 24 May 2018 23:28:58 -0700 Received: from mshsrv05.marvell.com (unknown [10.38.120.46]) by maili.marvell.com (Postfix) with ESMTP id 2293F3F703F; Thu, 24 May 2018 23:28:56 -0700 (PDT) From: To: Date: Fri, 25 May 2018 14:20:53 +0800 Message-ID: <1527229253-5912-3-git-send-email-xswang@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527229253-5912-1-git-send-email-xswang@marvell.com> References: <1527229253-5912-1-git-send-email-xswang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-05-25_02:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=610 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1805250078 Cc: Stefan Roese , Evan Wang Subject: [U-Boot] [PATCH v2 3/3] dts: mvebu: a80x0: Enable SD/eMMC interfaces X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Konstantin Porotchkin Enable SDHCI interface on AP and CP0 in A80x0 DTS files Signed-off-by: Konstantin Porotchkin Reviewed-by: Stefan Roese Signed-off-by: Evan Wang --- Changes in v2: None arch/arm/dts/armada-8040-db.dts | 14 ++++++++++++++ arch/arm/dts/armada-8040-mcbin.dts | 8 ++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index fa58995..65b30bb 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -81,6 +81,13 @@ 1 3 0 0 0 0 0 0 0 3 >; }; +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + &cpm_pinctl { /* MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins @@ -182,6 +189,13 @@ status = "okay"; }; +&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + &cps_pinctl { /* MPP Bus: * [0-11] RGMII0 diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 991ddc0..46b32f2 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -156,6 +156,14 @@ status = "okay"; }; +/* uSD slot */ +&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + &cpm_comphy { /* * CP0 Serdes Configuration: