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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc82bfa11sm78362135ad.254.2025.05.13.04.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 04:02:32 -0700 (PDT) From: Aswin Murugan To: trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, lukma@denx.de, seanga2@gmail.com, aswin.murugan@oss.qualcomm.com, ilias.apalodimas@linaro.org, me@samcday.com, sjg@chromium.org, quic_varada@quicinc.com, sughosh.ganu@linaro.org, lehmanju@devpi.de, bhupesh.linux@gmail.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 1/5] dts: qcs615-ride-u-boot.dtsi: Add memory entry to bootup Date: Tue, 13 May 2025 16:32:09 +0530 Message-Id: <20250513110213.330495-2-aswin.murugan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> References: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTEzMDEwNSBTYWx0ZWRfX25wNgzFVKFBr HEUXt4UkB2uzmoakHXx0cIqfTGPtJKnz+2p23l1W6aAmdLISE06X2c0Zp0ItXHZ45dwAB4DZ9l6 MCscGXvBAMfHQyirKDGn1FfGmpY7vtg+Vuwg1XquFiMxKZQ7ULfsxECo7cIDzs4XpOJTWtrNCnZ ukscHAXSYkLCCmpvO4T/ZywOE65U2XLOo41xCGc3qG0vOG0gmlcYEfyDdX1mqeWSy75XzuPJnb3 mhtDd2ANdOLFTinZ6ydb3F0Qe7KkZKsouglR+MUE+gScDwr3xhDuhzPi3PynMp6gOIjwsVwGxaw lCHpUl0V8JywF9PcmTMqeXLTJA0oehCdodT/wWZlP4TkAB/k0e6TW09cg5ZmmkAkrGft2VLNANM Q2Z8UBfYZhjCblc3BQ3VrMiqmfoZRggUlvHL72pxfNb0yEiy7sFenYOT7UL0TrlDewD4aRdF X-Proofpoint-GUID: 1u6q0zp0ZcnxIQcsX6Ths8Q29j9NbNfW X-Authority-Analysis: v=2.4 cv=WMV/XmsR c=1 sm=1 tr=0 ts=682326cb cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=75hTQqtBxdwJIasrO-oA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: 1u6q0zp0ZcnxIQcsX6Ths8Q29j9NbNfW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-12_07,2025-05-09_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=965 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505130105 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Added the memory entry to bootup. Signed-off-by: Aswin Murugan --- arch/arm/dts/qcs615-ride-u-boot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm/dts/qcs615-ride-u-boot.dtsi diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi new file mode 100644 index 00000000000..68fffc70fcb --- /dev/null +++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x7a00000>, + <0x0 0x89600000 0x0 0x30100000>, + <0x0 0xc0000000 0x0 0xc0000000>, + <0x1 0x80000000 0x1 0x00000000>; + }; +}; From patchwork Tue May 13 11:02:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswin Murugan X-Patchwork-Id: 2085068 X-Patchwork-Delegate: casey.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=Uy6U6X9Z; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc82bfa11sm78362135ad.254.2025.05.13.04.02.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 04:02:37 -0700 (PDT) From: Aswin Murugan To: trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, lukma@denx.de, seanga2@gmail.com, aswin.murugan@oss.qualcomm.com, ilias.apalodimas@linaro.org, me@samcday.com, sjg@chromium.org, quic_varada@quicinc.com, sughosh.ganu@linaro.org, lehmanju@devpi.de, bhupesh.linux@gmail.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 2/5] phy: qcom: Enable QMP UFS PHY driver for QCS615 Date: Tue, 13 May 2025 16:32:10 +0530 Message-Id: <20250513110213.330495-3-aswin.murugan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> References: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=DqtW+H/+ c=1 sm=1 tr=0 ts=682326d1 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=-KtapgylDENPCd9WzicA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: nxKJN-rxvQjTv_5BS6ewM79VYFA6mzOV X-Proofpoint-GUID: nxKJN-rxvQjTv_5BS6ewM79VYFA6mzOV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTEzMDEwNSBTYWx0ZWRfX2Yl/wyABp9se K1CDWeHW9mT6tOW27YYoLT42vOHnAz/0/src7sP1xuVKfp+Ru2sGbpXatVGvkgsZJmjMZ6P4dIq pojf/bXdQZBjThuPYw8Q+4h5dSjV+BhYREvmbzQjH5Y+wFo06QFX14f3Zn1j8k01rjnapnZ+3mL loRfDTZie0dLqqLgA4DvSUy0R/JSMAP4gI7A5sinSwRMafxHleXZNZ8izxbMdtZKlJ6fzewCRyS VhIW9+43RbhTB5pL7+tzMlzwB9mfdBUCj+Z8mdQlo7OKO8Tku6povw5roWp29fCI5TSA9v0xark YesLTZJWJLzJoVvnyVQZvJ0OKIbiNy4wqYeMQZMY9nyvp1RmTGLkP6IiFxVDzeFO8V/zZDW4tR1 Tq6txCra24/X4rQcPjv2lmO5g8MvxGkSkIMmV6gqIgjx/f3e/BGqyKiU1yvUDltmomWa+FzD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-12_07,2025-05-09_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 phishscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505130105 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enable QMP phy for QCS615, referenced from Linux. Signed-off-by: Aswin Murugan Reviewed-by: Neil Armstrong --- drivers/phy/qcom/phy-qcom-qmp-ufs.c | 127 ++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 449b9767778..175f55e8113 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -86,6 +86,12 @@ enum qphy_reg_layout { QPHY_LAYOUT_SIZE }; +static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, @@ -715,6 +721,98 @@ static const struct qmp_ufs_init_tbl sc7280_ufsphy_hs_g4_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), }; +static const struct qmp_ufs_init_tbl sm6115_ufsphy_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +}; + +static const struct qmp_ufs_init_tbl sm6115_ufsphy_hs_b_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), +}; + +static const struct qmp_ufs_init_tbl sm6115_ufsphy_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +}; + +static const struct qmp_ufs_init_tbl sm6115_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b), +}; + +static const struct qmp_ufs_init_tbl sm6115_ufsphy_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -1079,6 +1177,34 @@ static const struct qmp_ufs_cfg sa8775p_ufsphy_cfg = { .regs = ufsphy_v5_regs_layout, }; +static const struct qmp_ufs_cfg sm6115_ufsphy_cfg = { + .lanes = 1, + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm6115_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx = sm6115_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), + .rx = sm6115_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs = sm6115_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm6115_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), + }, + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_ufs_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), + .regs = ufsphy_v2_regs_layout, + + .no_pcs_sw_reset = true, +}; + static void qmp_ufs_configure_lane(void __iomem *base, const struct qmp_ufs_init_tbl tbl[], int num, @@ -1472,6 +1598,7 @@ static const struct udevice_id qmp_ufs_ids[] = { { .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg }, { .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg }, { .compatible = "qcom,sc7280-qmp-ufs-phy", .data = (ulong)&sc7280_ufsphy_cfg, }, + { .compatible = "qcom,qcs615-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, }, { } }; From patchwork Tue May 13 11:02:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswin Murugan X-Patchwork-Id: 2085069 X-Patchwork-Delegate: casey.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=RoBMQpVh; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc82bfa11sm78362135ad.254.2025.05.13.04.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 04:02:43 -0700 (PDT) From: Aswin Murugan To: trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, lukma@denx.de, seanga2@gmail.com, aswin.murugan@oss.qualcomm.com, ilias.apalodimas@linaro.org, me@samcday.com, sjg@chromium.org, quic_varada@quicinc.com, sughosh.ganu@linaro.org, lehmanju@devpi.de, bhupesh.linux@gmail.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 3/5] clk/qcom: qcs615: Add GCC clock driver for QCS615 Date: Tue, 13 May 2025 16:32:11 +0530 Message-Id: <20250513110213.330495-4-aswin.murugan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> References: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 11UreuaavNjTSvcyxxSHyqH4c4TU4Mfv X-Proofpoint-GUID: 11UreuaavNjTSvcyxxSHyqH4c4TU4Mfv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTEzMDEwNSBTYWx0ZWRfX7ViVZLo6ctRX XpYM2WKx9mgPrfYMewYnXGmeyw7x/uQlpkCF9PCLlOrp7j3xUnONBVmpHSEPVEyIzvnyk4NQHtH C/OD6Lb8Ko0A2haNozgXt4Tt5CFebPSiizJMg/hnJ3omTNIL4LeBtd2M649QAqpIl4zWR9Ko/qy S2+n2qkW7md/bPgqHmeXXxhS6D0pVJyY6GlLPtG1qABHRJkYmDoWNUYMxflVm+JBDKiK5rtolcX 5DkieHjg3xjuWLCuXuri06UZ1YSy3elnJiAIDK9KErkJeVeD7nl3DH2vOxf/AefrWOjt/6Bc3jv SjafHMVMDm3BcOUypBOI6171h5K96CZTSjrlRrn9t8Ec7yVEasOGBP9YRKgfRyw8KnG+kD9Bwkt f8ExQ+68A8bOW612HLALgEDNHtGEBdOvrfcucrvGcVlxXXnHv/bMVvW9yqT4+7cv5931Kf+p X-Authority-Analysis: v=2.4 cv=afhhnQot c=1 sm=1 tr=0 ts=682326d5 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=240JKWVrdINMfe09_TgA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-12_07,2025-05-09_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505130105 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Port Linux's gcc-qcs615.c driver to U-Boot for basic bring-up. Signed-off-by: Aswin Murugan Reviewed-by: Neil Armstrong --- drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-qcs615.c | 163 ++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/clk/qcom/clock-qcs615.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 3ea01f3c969..eaac4a97376 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,6 +55,14 @@ config CLK_QCOM_QCS404 on the Snapdragon QCS404 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_QCS615 + bool "Qualcomm QCS615 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon QCS615 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_SA8775P bool "Qualcomm SA8775 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e13fc8c1071..8f749487246 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c new file mode 100644 index 00000000000..161db0eeef5 --- /dev/null +++ b/drivers/clk/qcom/clock-qcs615.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for Qualcomm qcs615 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "clock-qcom.h" + +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf034 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf060 + +#define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) +#define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) +#define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) +#define GCC_QUPV3_WRAP0_S3_CLK_ENA_BIT BIT(13) +#define GCC_QUPV3_WRAP0_S4_CLK_ENA_BIT BIT(14) +#define GCC_QUPV3_WRAP0_S5_CLK_ENA_BIT BIT(15) + +#define GCC_QUPV3_WRAP1_S0_CLK_ENA_BIT BIT(22) +#define GCC_QUPV3_WRAP1_S1_CLK_ENA_BIT BIT(23) +#define GCC_QUPV3_WRAP1_S2_CLK_ENA_BIT BIT(24) +#define GCC_QUPV3_WRAP1_S3_CLK_ENA_BIT BIT(25) +#define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26) +#define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27) + +static ulong qcs615_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, + priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate); + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return rate; + case GCC_USB30_PRIM_MASTER_CLK: + WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); + clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); + return rate; + default: + return 0; + } +} + +static const struct gate_clk qcs615_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf078, 1), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf07c, 1), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf014, 1), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf018, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, 1), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, GCC_QUPV3_WRAP0_S3_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, GCC_QUPV3_WRAP0_S4_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, GCC_QUPV3_WRAP0_S5_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, GCC_QUPV3_WRAP1_S0_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, GCC_QUPV3_WRAP1_S1_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x5200c, GCC_QUPV3_WRAP1_S2_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, GCC_QUPV3_WRAP1_S3_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT), + GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT), + GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, 1), + GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, 1) +}; + +static int qcs615_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, qcs615_clks[clk->id].name); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map qcs615_gcc_resets[] = { + [GCC_EMAC_BCR] = { 0x6000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0xd000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0xd004 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB2_PHY_SEC_BCR] = { 0x50018 }, + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c }, + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB20_SEC_BCR] = { 0xa6000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x50008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 }, + [GCC_SDCC1_BCR] = { 0x12000 }, + [GCC_SDCC2_BCR] = { 0x14000 } +}; + +static const struct qcom_power_map qcs615_gdscs[] = { + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, +}; + +static struct msm_clk_data sa8775_gcc_data = { + .resets = qcs615_gcc_resets, + .num_resets = ARRAY_SIZE(qcs615_gcc_resets), + .clks = qcs615_clks, + .num_clks = ARRAY_SIZE(qcs615_clks), + + .power_domains = qcs615_gdscs, + .num_power_domains = ARRAY_SIZE(qcs615_gdscs), + + .enable = qcs615_enable, + .set_rate = qcs615_set_rate, +}; + +static const struct udevice_id gcc_qcs615_of_match[] = { + { + .compatible = "qcom,qcs615-gcc", + .data = (ulong)&sa8775_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_qcs615) = { + .name = "gcc_qcs615", + .id = UCLASS_NOP, + .of_match = gcc_qcs615_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; From patchwork Tue May 13 11:02:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswin Murugan X-Patchwork-Id: 2085071 X-Patchwork-Delegate: casey.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Signed-off-by: Aswin Murugan --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index b8399701da0..8510828824f 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -51,6 +51,7 @@ CONFIG_CLK_QCOM_APQ8016=y CONFIG_CLK_QCOM_APQ8096=y CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y +CONFIG_CLK_QCOM_QCS615=y CONFIG_CLK_QCOM_SA8775P=y CONFIG_CLK_QCOM_SDM845=y CONFIG_CLK_QCOM_SM6115=y From patchwork Tue May 13 11:02:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswin Murugan X-Patchwork-Id: 2085070 X-Patchwork-Delegate: casey.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=kZSaoTWB; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc82bfa11sm78362135ad.254.2025.05.13.04.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 04:02:53 -0700 (PDT) From: Aswin Murugan To: trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, lukma@denx.de, seanga2@gmail.com, aswin.murugan@oss.qualcomm.com, ilias.apalodimas@linaro.org, me@samcday.com, sjg@chromium.org, quic_varada@quicinc.com, sughosh.ganu@linaro.org, lehmanju@devpi.de, bhupesh.linux@gmail.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 5/5] configs: add qcs615_defconfig Date: Tue, 13 May 2025 16:32:13 +0530 Message-Id: <20250513110213.330495-6-aswin.murugan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> References: <20250513110213.330495-1-aswin.murugan@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTEzMDEwNSBTYWx0ZWRfX2tTJFrg8L+cV 5NAjuIhHGne4ZhZ0jZ1/9TV00HWhv8a+SpD9wvKwI3O0WAuvEb9ZCvm5LxPqv1qwXf2iYDFtf0a e5yKh9p9jF7jCXS1OyhauuUzgm2JGulDwqXkFiGCl1Uj2v1EAaE/jDRJ0brZEu51kjL3mwUKBVw 58r/48bMwgjiD8ZGDIJ4o3O0Dx3J182E/LZ3r6foiViofMEFeRl2QysEvJlEHT00PVGbJTG5p/g y59YGcVac+qZQEE7EqzPa37oPaEane21aqAimpxTGiR1W4/J7HiWE4t/HhI2Ck7Lelx5FPxO0CK zxvs+cMHqLtMApsz60g0MFm1JiutSzBILk1DYntqGXiNonAK9kgGQZL7W5EYqtHddHUbcJ+uHEv Q44FJZSPVJXd9HLmLCMEWfG1obwgjzdXCrkP30P5FC5BKGGN3k4HY+myIiELmRr8K0dz0fzJ X-Proofpoint-GUID: BZO4TgHGFggu52Rak3MFlHIJbOJcn4fz X-Authority-Analysis: v=2.4 cv=WMV/XmsR c=1 sm=1 tr=0 ts=682326df cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=R2VVY1Wf7TWBXLlSVHsA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: BZO4TgHGFggu52Rak3MFlHIJbOJcn4fz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-12_07,2025-05-09_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=841 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505130105 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Introduce a defconfig for QCS615 based boards. Signed-off-by: Aswin Murugan --- configs/qcom_qcs615_defconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 configs/qcom_qcs615_defconfig diff --git a/configs/qcom_qcs615_defconfig b/configs/qcom_qcs615_defconfig new file mode 100644 index 00000000000..c3822d392ef --- /dev/null +++ b/configs/qcom_qcs615_defconfig @@ -0,0 +1,22 @@ +# Configuration for building U-Boot to be flashed +# to the uefi partition of QCS615 dev boards with +# the "Linux Embedded" partition layout (which have +# a dedicated "uefi" partition for edk2/U-Boot) + +#include "qcom_defconfig" + +# Otherwise buildman thinks this isn't an ARM platform +CONFIG_ARM=y + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x880000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 + +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs615-ride" + +CONFIG_REMAKE_ELF=y + +# Address where U-Boot will be loaded +CONFIG_TEXT_BASE=0x9fc00000