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Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/Kconfig | 7 +++++-- arch/arm/mach-stm32mp/Kconfig.13x | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 58250901101..3a0ca50e9d6 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -40,16 +40,19 @@ choice config STM32MP13X bool "Support STMicroelectronics STM32MP13x Soc" select ARCH_EARLY_INIT_R - select ARM_SMCCC + select ARM_SMCCC if TFABOOT + select ARCH_SUPPORT_PSCI if !TFABOOT + select BINMAN if !TFABOOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT - select OF_BOARD + select OF_BOARD if TFABOOT select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC select STM32_RESET select STM32_SERIAL + select SUPPORT_SPL if !TFABOOT select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO imply OF_UPSTREAM diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x index bc8b3f8cf77..cecf9e3b8c7 100644 --- a/arch/arm/mach-stm32mp/Kconfig.13x +++ b/arch/arm/mach-stm32mp/Kconfig.13x @@ -20,7 +20,8 @@ config TARGET_ST_STM32MP13X endchoice config TEXT_BASE - default 0xC0000000 + default 0xC0000000 if TFABOOT + default 0xC0100000 if !TFABOOT config PRE_CON_BUF_ADDR default 0xC0800000 From patchwork Mon May 12 17:21:29 2025 Content-Type: text/plain; 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This is similar to STM32MP15xx except the code has to enable MCE to bring DRAM controller up later. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/include/mach/stm32.h | 2 + arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c | 204 ++++++++++++++++++++ 2 files changed, 206 insertions(+) diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index dfba57e7dc4..37f3e8595b2 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -156,6 +156,8 @@ enum forced_boot_mode { #endif #ifdef CONFIG_STM32MP13X +#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) +#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 4a811065fc3..79b2f2d0bba 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -6,11 +6,59 @@ #define LOG_CATEGORY LOGC_ARCH #include +#include #include #include #include +#include +#include #include #include +#include +#include +#include +#include + +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x400) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x468) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x740) +#define RCC_MP_AHB6ENSETR (STM32_RCC_BASE + 0x780) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* DBGMCU register */ +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2c) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +/* Security register */ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_ACTION (STM32_TZC_BASE + 0x004) +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_BASE(n) (STM32_TZC_BASE + 0x100 + (0x20 * (n))) +#define TZC_REGION_TOP(n) (STM32_TZC_BASE + 0x108 + (0x20 * (n))) +#define TZC_REGION_ATTRIBUTE(n) (STM32_TZC_BASE + 0x110 + (0x20 * (n))) +#define TZC_REGION_ID_ACCESS(n) (STM32_TZC_BASE + 0x114 + (0x20 * (n))) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_CR1_DBP BIT(8) + +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 /* SYSCFG register */ #define SYSCFG_IDC_OFFSET 0x380 @@ -23,6 +71,162 @@ #define RPN_SHIFT 0 #define RPN_MASK GENMASK(11, 0) +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(0, ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable MCE clock */ + writel(BIT(1), RCC_MP_AHB6ENSETR); + + /* enable TZC clock */ + writel(BIT(11), RCC_MP_APB5ENSETR); + + /* Disable Filter 0 */ + writel(0, TZC_GATE_KEEPER); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(0)); + + /* bit 30 / 31 => Secure Global Enable : write/read */ + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(0)); + + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(1)); + writel(0xC0000000, TZC_REGION_BASE(1)); + writel(0xDDFFFFFF, TZC_REGION_TOP(1)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(1)); + + writel(0x00000000, TZC_REGION_ID_ACCESS(2)); + writel(0xDE000000, TZC_REGION_BASE(2)); + writel(0xDFFFFFFF, TZC_REGION_TOP(2)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(2)); + + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(3)); + writel(0x00000000, TZC_REGION_BASE(3)); + writel(0xBFFFFFFF, TZC_REGION_TOP(3)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(3)); + + /* Set Action */ + writel(BIT(0), TZC_ACTION); + + /* Enable Filter 0 */ + writel(BIT(0), TZC_GATE_KEEPER); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); +} + +/* + * Debug init + */ +void dbgmcu_init(void) +{ + /* + * Freeze IWDG2 if Cortex-A7 is in debug mode + * done in TF-A for TRUSTED boot and + * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE + */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + u8 *tlb; + int ret; + + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); + + /* Enable Dcache here, now that DRAM is available */ + if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_STM32MP13X)) { + tlb = memalign(0x4000, PGTABLE_SIZE); + if (!tlb) + return; + + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)tlb; + dcache_enable(); + } +} + +/* get bootmode from ROM code boot context: saved in TAMP register */ +static void update_bootmode(void) +{ + u32 boot_mode; + u32 bootrom_itf = readl(get_stm32mp_rom_api_table()); + u32 bootrom_device, bootrom_instance; + + /* enable TAMP clock = RTCAPBEN */ + writel(BIT(8), RCC_MP_APB5ENSETR); + + /* read bootrom context */ + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +} + +/* weak function: STM32MP15x mach init for boot without TFA */ +void stm32mp_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_XPL_BUILD)) { + security_init(); + update_bootmode(); + } +} + static u32 read_idc(void) { void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); From patchwork Mon May 12 17:21:30 2025 Content-Type: text/plain; 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The dcache will be enabled later, once DRAM is available and TLB can be placed in DRAM. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 9 ++++++--- arch/arm/mach-stm32mp/stm32mp1/spl.c | 3 ++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 9ab5a3ede52..1ae82489a4b 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -28,7 +28,9 @@ * early TLB into the .data section so that it not get cleared * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) */ +#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X)) u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); +#endif u32 get_bootmode(void) { @@ -95,18 +97,19 @@ void dram_bank_mmu_setup(int bank) */ static void early_enable_caches(void) { +#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X)) /* I-cache is already enabled in start.S: cpu_init_cp15 */ - if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) return; #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - gd->arch.tlb_size = PGTABLE_SIZE; - gd->arch.tlb_addr = (unsigned long)&early_tlb; + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; #endif /* enable MMU (default configuration) */ dcache_enable(); +#endif } /* diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 9c4fafbf478..e63bdaaf42f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -220,10 +220,11 @@ void board_init_f(ulong dummy) * activate cache on DDR only when DDR is fully initialized * to avoid speculative access and issue in get_ram_size() */ - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !IS_ENABLED(CONFIG_STM32MP13X)) { mmu_set_region_dcache_behaviour(STM32_DDR_BASE, CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); + } } void spl_board_prepare_for_boot(void) From patchwork Mon May 12 17:21:31 2025 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747070540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wlQeXKprmnnpWWXsbmVTnZIw+/Hde1MGFbCAtnDBLh8=; b=QOEsUC9prl9igi3lWua7lUBxjFUP6nf8lYDW2kgaNlQ99kVFrgn8DvbktV4woGDwhjduGX za694O4YGa3CQMbm0t/Aw/frOgN/IYkRzM+oqXAT1BrGV6BqB9+60erjpi7mQKRRsSxhKP xhbjXgMz+kJYw4Do17+4ts2LQLNttuY919e9dflzk4jUsnMCiS7IPQMSrLWXTzLdIxWhZu wu+XDxvhzZ1h5r4cC1zoqJtSzUfygOGS82MrnLRgjvjnv58nJw92kUIioT3B35Qo8AAXg/ CdPFO4xZkyQuuczqfDV32+p5Ob/twwGxhHqz54qJoUneZjDPUmWOgPjKw85H/Q== To: u-boot@lists.denx.de Cc: Marek Vasut , Cheick Traore , Fabrice Gasnier , Gatien Chevallier , Lionel Debieve , Pascal Zimmermann , Patrice Chotard , Patrick Delaunay , Simon Glass , Sughosh Ganu , Tom Rini , u-boot@dh-electronics.com, uboot-stm32@st-md-mailman.stormreply.com Subject: [PATCH 04/10] ARM: stm32: Add STM32MP13xx PMIC initialization for DDR3 DRAM type Date: Mon, 12 May 2025 19:21:31 +0200 Message-ID: <20250512172149.150214-5-marek.vasut@mailbox.org> In-Reply-To: <20250512172149.150214-1-marek.vasut@mailbox.org> References: <20250512172149.150214-1-marek.vasut@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: ee551b5348d262a5161 X-MBO-RS-META: swqn8niaunyarxayx3iotuteoggjj6jm X-Rspamd-Queue-Id: 4Zx5yP6h1Hz9smH X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar to the STM32MP15xx PMIC initialization, except the VTT rail is not enabled. Fill in the STM32MP13xx support. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- board/st/common/stpmic1.c | 51 ++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 17 deletions(-) diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index 45c2bb5bcea..b46f89dacb9 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -14,8 +14,19 @@ #include #include +static bool is_stm32mp13xx(void) +{ + if (!IS_ENABLED(CONFIG_STM32MP13X)) + return false; + + return of_machine_is_compatible("st,stm32mp131") || + of_machine_is_compatible("st,stm32mp133") || + of_machine_is_compatible("st,stm32mp135"); +} + int board_ddr_power_init(enum ddr_type ddr_type) { + bool is_mp13 = is_stm32mp13xx(); struct udevice *dev; bool buck3_at_1800000v = false; int ret; @@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type) switch (ddr_type) { case STM32MP_DDR3: /* VTT = Set LDO3 to sync mode */ - ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); - if (ret < 0) - return ret; - - ret &= ~STPMIC1_LDO3_MODE; - ret &= ~STPMIC1_LDO12356_VOUT_MASK; - ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); - - ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - ret); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); + if (ret < 0) + return ret; + + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); + + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + ret); + if (ret < 0) + return ret; + } /* VDD_DDR = Set BUCK2 to 1.35V */ ret = pmic_clrsetbits(dev, @@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type) mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); /* Enable VTT = LDO3 */ - ret = pmic_clrsetbits(dev, - STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_clrsetbits(dev, + STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); + if (ret < 0) + return ret; + } mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); From patchwork Mon May 12 17:21:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 2084559 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=JfJRZKGA; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=qelaxidN; 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This is similar to STM32MP15xx debug UART initialization, except the RCC registers are at different offsets and the UART pinmux pins are different. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- board/st/stm32mp1/debug_uart.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/board/st/stm32mp1/debug_uart.c b/board/st/stm32mp1/debug_uart.c index 24e3f9f2201..4c2149e0480 100644 --- a/board/st/stm32mp1/debug_uart.c +++ b/board/st/stm32mp1/debug_uart.c @@ -9,17 +9,32 @@ #include #include +#if IS_ENABLED(CONFIG_STM32MP13X) +#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0700) +#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0768) +#elif IS_ENABLED(CONFIG_STM32MP15X) #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) +#endif +#define GPIOA_BASE 0x50002000 #define GPIOG_BASE 0x50008000 void board_debug_uart_init(void) { - if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) { - /* UART4 clock enable */ - setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + if (CONFIG_DEBUG_UART_BASE != STM32_UART4_BASE) + return; + /* UART4 clock enable */ + setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + + if (IS_ENABLED(CONFIG_STM32MP13X)) { + /* GPIOA clock enable */ + writel(BIT(0), RCC_MP_AHB4ENSETR); + /* GPIO configuration for DH boards: Uart4 TX = A9 */ + writel(0xfffbffff, GPIOA_BASE + 0x00); + writel(0x00000080, GPIOA_BASE + 0x24); + } else if (IS_ENABLED(CONFIG_STM32MP15X)) { /* GPIOG clock enable */ writel(BIT(6), RCC_MP_AHB4ENSETR); /* GPIO configuration for ST boards: Uart4 TX = G11 */ From patchwork Mon May 12 17:21:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 2084560 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=Glh6mxRR; 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747070543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oEBCnKWMya6FW2bsjfAnOy7t/hQr8bDilgKI0CVR4nw=; b=BeYWxh/NXVAqC9rM+1jj2MuyFIuGi1g5RnVuYN1vSrXhoqgDIi76tTXOXKVgXL+1J1knEA v5Y13OkCTw+OpnYesibVmcNbh9wvjjE8TsH52rkJHkTE3qYUrGRNG3CDYLrHsa+fvc/IoQ S4lvnlIpBEwgsB1Tf25fk+skVXl+UJgOMsKIrWVEoYE69ZBVoeNy+lNLSQiNby1kTfN/z6 TgRgUlyY+3CcV0eX7HhTaR7Ly1rPlfDbcWd/FLiCXo813yKuzzNqfYKmPzayPEkovTA2h6 KwDx+t1JJ5mXIfqaWD1aRiY5R6FriXEwAq6A4pvbcA1PjwhZd9HFoMlP/qwRoQ== To: u-boot@lists.denx.de Cc: Marek Vasut , Cheick Traore , Fabrice Gasnier , Gatien Chevallier , Lionel Debieve , Pascal Zimmermann , Patrice Chotard , Patrick Delaunay , Simon Glass , Sughosh Ganu , Tom Rini , u-boot@dh-electronics.com, uboot-stm32@st-md-mailman.stormreply.com Subject: [PATCH 06/10] ARM: dts: stm32: Add stm32mp13-ddr.dtsi template Date: Mon, 12 May 2025 19:21:33 +0200 Message-ID: <20250512172149.150214-7-marek.vasut@mailbox.org> In-Reply-To: <20250512172149.150214-1-marek.vasut@mailbox.org> References: <20250512172149.150214-1-marek.vasut@mailbox.org> MIME-Version: 1.0 X-MBO-RS-META: 4ab3mwacn6pyewi839qsayg3piyuwjkd X-MBO-RS-ID: 29c7be93e5c737a09cb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Factor out common parts of STM32MP15xx DRAM controller configuration DT description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which describes STM32MP13xx DRAM controller configuration in DT. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- arch/arm/dts/stm32mp1-ddr.dtsi | 187 ++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp13-ddr.dtsi | 49 +++++++++ arch/arm/dts/stm32mp15-ddr.dtsi | 170 +---------------------------- 3 files changed, 237 insertions(+), 169 deletions(-) create mode 100644 arch/arm/dts/stm32mp1-ddr.dtsi create mode 100644 arch/arm/dts/stm32mp13-ddr.dtsi diff --git a/arch/arm/dts/stm32mp1-ddr.dtsi b/arch/arm/dts/stm32mp1-ddr.dtsi new file mode 100644 index 00000000000..da9f9fac4b8 --- /dev/null +++ b/arch/arm/dts/stm32mp1-ddr.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2018 + */ +#include + +#ifdef CONFIG_SPL +&ddr { + config-DDR_MEM_COMPATIBLE { + bootph-all; + + compatible = __stringify(st,DDR_MEM_COMPATIBLE); + + st,mem-name = DDR_MEM_NAME; + st,mem-speed = ; + st,mem-size = ; + + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; + + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; + + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; + + + /* + * Both st,ctl-perf and st,phy-reg differ + * between STM32MP13xx and STM32MP15xx due + * to 16bit and 32bit DRAM bus respectively + * on these SoCs. + */ + + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; + + status = "okay"; + }; +}; +#endif + +#undef DDR_MEM_COMPATIBLE +#undef DDR_MEM_NAME +#undef DDR_MEM_SPEED +#undef DDR_MEM_SIZE + +#undef DDR_MSTR +#undef DDR_MRCTRL0 +#undef DDR_MRCTRL1 +#undef DDR_DERATEEN +#undef DDR_DERATEINT +#undef DDR_PWRCTL +#undef DDR_PWRTMG +#undef DDR_HWLPCTL +#undef DDR_RFSHCTL0 +#undef DDR_RFSHCTL3 +#undef DDR_RFSHTMG +#undef DDR_CRCPARCTL0 +#undef DDR_DRAMTMG0 +#undef DDR_DRAMTMG1 +#undef DDR_DRAMTMG2 +#undef DDR_DRAMTMG3 +#undef DDR_DRAMTMG4 +#undef DDR_DRAMTMG5 +#undef DDR_DRAMTMG6 +#undef DDR_DRAMTMG7 +#undef DDR_DRAMTMG8 +#undef DDR_DRAMTMG14 +#undef DDR_ZQCTL0 +#undef DDR_DFITMG0 +#undef DDR_DFITMG1 +#undef DDR_DFILPCFG0 +#undef DDR_DFIUPD0 +#undef DDR_DFIUPD1 +#undef DDR_DFIUPD2 +#undef DDR_DFIPHYMSTR +#undef DDR_ADDRMAP1 +#undef DDR_ADDRMAP2 +#undef DDR_ADDRMAP3 +#undef DDR_ADDRMAP4 +#undef DDR_ADDRMAP5 +#undef DDR_ADDRMAP6 +#undef DDR_ADDRMAP9 +#undef DDR_ADDRMAP10 +#undef DDR_ADDRMAP11 +#undef DDR_ODTCFG +#undef DDR_ODTMAP +#undef DDR_SCHED +#undef DDR_SCHED1 +#undef DDR_PERFHPR1 +#undef DDR_PERFLPR1 +#undef DDR_PERFWR1 +#undef DDR_DBG0 +#undef DDR_DBG1 +#undef DDR_DBGCMD +#undef DDR_POISONCFG +#undef DDR_PCCFG +#undef DDR_PCFGR_0 +#undef DDR_PCFGW_0 +#undef DDR_PCFGQOS0_0 +#undef DDR_PCFGQOS1_0 +#undef DDR_PCFGWQOS0_0 +#undef DDR_PCFGWQOS1_0 +#undef DDR_PCFGR_1 +#undef DDR_PCFGW_1 +#undef DDR_PCFGQOS0_1 +#undef DDR_PCFGQOS1_1 +#undef DDR_PCFGWQOS0_1 +#undef DDR_PCFGWQOS1_1 +#undef DDR_PGCR +#undef DDR_PTR0 +#undef DDR_PTR1 +#undef DDR_PTR2 +#undef DDR_ACIOCR +#undef DDR_DXCCR +#undef DDR_DSGCR +#undef DDR_DCR +#undef DDR_DTPR0 +#undef DDR_DTPR1 +#undef DDR_DTPR2 +#undef DDR_MR0 +#undef DDR_MR1 +#undef DDR_MR2 +#undef DDR_MR3 +#undef DDR_ODTCR +#undef DDR_ZQ0CR1 +#undef DDR_DX0GCR +#undef DDR_DX1GCR +#undef DDR_DX2GCR +#undef DDR_DX3GCR diff --git a/arch/arm/dts/stm32mp13-ddr.dtsi b/arch/arm/dts/stm32mp13-ddr.dtsi new file mode 100644 index 00000000000..30d8c5014e0 --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2018 + */ +#ifdef CONFIG_SPL +&ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + + config-DDR_MEM_COMPATIBLE { + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + >; + + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + >; + }; +}; +#endif + +#include "stm32mp1-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 48b0828828f..f18fdaeab68 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -2,8 +2,6 @@ /* * Copyright : STMicroelectronics 2018 */ -#include - #ifdef CONFIG_SPL &ddr { clocks = <&rcc AXIDCG>, @@ -21,69 +19,6 @@ "ddrphycapb"; config-DDR_MEM_COMPATIBLE { - bootph-all; - - compatible = __stringify(st,DDR_MEM_COMPATIBLE); - - st,mem-name = DDR_MEM_NAME; - st,mem-speed = ; - st,mem-size = ; - - st,ctl-reg = < - DDR_MSTR - DDR_MRCTRL0 - DDR_MRCTRL1 - DDR_DERATEEN - DDR_DERATEINT - DDR_PWRCTL - DDR_PWRTMG - DDR_HWLPCTL - DDR_RFSHCTL0 - DDR_RFSHCTL3 - DDR_CRCPARCTL0 - DDR_ZQCTL0 - DDR_DFITMG0 - DDR_DFITMG1 - DDR_DFILPCFG0 - DDR_DFIUPD0 - DDR_DFIUPD1 - DDR_DFIUPD2 - DDR_DFIPHYMSTR - DDR_ODTMAP - DDR_DBG0 - DDR_DBG1 - DDR_DBGCMD - DDR_POISONCFG - DDR_PCCFG - >; - - st,ctl-timing = < - DDR_RFSHTMG - DDR_DRAMTMG0 - DDR_DRAMTMG1 - DDR_DRAMTMG2 - DDR_DRAMTMG3 - DDR_DRAMTMG4 - DDR_DRAMTMG5 - DDR_DRAMTMG6 - DDR_DRAMTMG7 - DDR_DRAMTMG8 - DDR_DRAMTMG14 - DDR_ODTCFG - >; - - st,ctl-map = < - DDR_ADDRMAP1 - DDR_ADDRMAP2 - DDR_ADDRMAP3 - DDR_ADDRMAP4 - DDR_ADDRMAP5 - DDR_ADDRMAP6 - DDR_ADDRMAP9 - DDR_ADDRMAP10 - DDR_ADDRMAP11 - >; - st,ctl-perf = < DDR_SCHED DDR_SCHED1 @@ -117,111 +52,8 @@ DDR_DX2GCR DDR_DX3GCR >; - - st,phy-timing = < - DDR_PTR0 - DDR_PTR1 - DDR_PTR2 - DDR_DTPR0 - DDR_DTPR1 - DDR_DTPR2 - DDR_MR0 - DDR_MR1 - DDR_MR2 - DDR_MR3 - >; - - status = "okay"; }; }; #endif -#undef DDR_MEM_COMPATIBLE -#undef DDR_MEM_NAME -#undef DDR_MEM_SPEED -#undef DDR_MEM_SIZE - -#undef DDR_MSTR -#undef DDR_MRCTRL0 -#undef DDR_MRCTRL1 -#undef DDR_DERATEEN -#undef DDR_DERATEINT -#undef DDR_PWRCTL -#undef DDR_PWRTMG -#undef DDR_HWLPCTL -#undef DDR_RFSHCTL0 -#undef DDR_RFSHCTL3 -#undef DDR_RFSHTMG -#undef DDR_CRCPARCTL0 -#undef DDR_DRAMTMG0 -#undef DDR_DRAMTMG1 -#undef DDR_DRAMTMG2 -#undef DDR_DRAMTMG3 -#undef DDR_DRAMTMG4 -#undef DDR_DRAMTMG5 -#undef DDR_DRAMTMG6 -#undef DDR_DRAMTMG7 -#undef DDR_DRAMTMG8 -#undef DDR_DRAMTMG14 -#undef DDR_ZQCTL0 -#undef DDR_DFITMG0 -#undef DDR_DFITMG1 -#undef DDR_DFILPCFG0 -#undef DDR_DFIUPD0 -#undef DDR_DFIUPD1 -#undef DDR_DFIUPD2 -#undef DDR_DFIPHYMSTR -#undef DDR_ADDRMAP1 -#undef DDR_ADDRMAP2 -#undef DDR_ADDRMAP3 -#undef DDR_ADDRMAP4 -#undef DDR_ADDRMAP5 -#undef DDR_ADDRMAP6 -#undef DDR_ADDRMAP9 -#undef DDR_ADDRMAP10 -#undef DDR_ADDRMAP11 -#undef DDR_ODTCFG -#undef DDR_ODTMAP -#undef DDR_SCHED -#undef DDR_SCHED1 -#undef DDR_PERFHPR1 -#undef DDR_PERFLPR1 -#undef DDR_PERFWR1 -#undef DDR_DBG0 -#undef DDR_DBG1 -#undef DDR_DBGCMD -#undef DDR_POISONCFG -#undef DDR_PCCFG -#undef DDR_PCFGR_0 -#undef DDR_PCFGW_0 -#undef DDR_PCFGQOS0_0 -#undef DDR_PCFGQOS1_0 -#undef DDR_PCFGWQOS0_0 -#undef DDR_PCFGWQOS1_0 -#undef DDR_PCFGR_1 -#undef DDR_PCFGW_1 -#undef DDR_PCFGQOS0_1 -#undef DDR_PCFGQOS1_1 -#undef DDR_PCFGWQOS0_1 -#undef DDR_PCFGWQOS1_1 -#undef DDR_PGCR -#undef DDR_PTR0 -#undef DDR_PTR1 -#undef DDR_PTR2 -#undef DDR_ACIOCR -#undef DDR_DXCCR -#undef DDR_DSGCR -#undef DDR_DCR -#undef DDR_DTPR0 -#undef DDR_DTPR1 -#undef DDR_DTPR2 -#undef DDR_MR0 -#undef DDR_MR1 -#undef DDR_MR2 -#undef DDR_MR3 -#undef DDR_ODTCR -#undef DDR_ZQ0CR1 -#undef DDR_DX0GCR -#undef DDR_DX1GCR -#undef DDR_DX2GCR -#undef DDR_DX3GCR +#include "stm32mp1-ddr.dtsi" From patchwork Mon May 12 17:21:34 2025 Content-Type: text/plain; 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Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- .../stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi | 100 ++++++++++++++++++ arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi | 1 + 2 files changed, 101 insertions(+) create mode 100644 arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi new file mode 100644 index 00000000000..7b344541c3e --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, DH electronics - All Rights Reserved + * + * STM32MP13xx DHSOM configuration + * 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W631GU6MB15I from Winbond + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 0 = W631GU6MB15I / DDR3-1333 + * DDR density 2 + * timing mode optimized + * address mapping : RBC + * Tc > + 85C : J + */ +#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-1x2gb-533mhz +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index 9ff42ab8248..6117da10bbf 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "stm32mp13-u-boot.dtsi" +#include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi" / { aliases { From patchwork Mon May 12 17:21:35 2025 Content-Type: text/plain; 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This includes binman node to generate STM32 Image v2.0 which can be booted by the BootROM, clock entries used by the SPL clock driver during clock tree initialization, and syscon-reboot node so U-Boot can reset the system without having to rely on PSCI call. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- arch/arm/dts/stm32mp13-u-boot.dtsi | 89 ++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 1fe6966781c..ad63d5027b2 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -17,6 +17,7 @@ pinctrl0 = &pinctrl; }; +#if defined(CONFIG_TFABOOT) firmware { optee { bootph-all; @@ -27,6 +28,86 @@ psci { bootph-some-ram; }; +#else + binman: binman { + multiple-images; + + spl-stm32 { + filename = "u-boot-spl.stm32"; + mkimage { + args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000"; + u-boot-spl { + no-write-symbols; + }; + }; + }; + }; + + clocks { + bootph-all; + + clk_hse: ck_hse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: ck_hsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: ck_lse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: ck_lsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: ck_csi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + bootph-pre-ram; + opp-650000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; + opp-1000000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; + }; + }; + + reboot { + bootph-all; + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x114>; + mask = <0x1>; + }; +#endif soc { bootph-all; @@ -52,6 +133,14 @@ bootph-all; }; +#if !defined(CONFIG_TFABOOT) +&cpu0 { + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + operating-points-v2 = <&cpu0_opp_table>; +}; +#endif + &gpioa { bootph-all; }; From patchwork Mon May 12 17:21:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 2084563 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=MkkRcYma; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=fk6A24bc; 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spf=pass smtp.mailfrom=marek.vasut@mailbox.org Received: from smtp1.mailbox.org (smtp1.mailbox.org [10.196.197.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4Zx5yZ71zBz9smH; Mon, 12 May 2025 19:22:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747070551; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FeXd+WlBnri4ZTOv82UditI3xm6q0kQ4rGwC4nDMjW0=; b=MkkRcYmaaqWaLWGmZbavADpP/HfJi2/eguKhJnJBet/XaW0rXkbbUZth0z5g8Y6eyPxCLG N2BLykns9u2kNW0XA6Kgn36RLiQUzelSPecBG2c+V89sO3HQ+RTztCfgJi+uYpOpN+huCp Gtq5sHGglUKhf3v+QqRppheEPPBc0sfWKh3kWpUHzAOJzCt3xiEXmLSU04ynGc2UyIuG/1 gdMb/UpLW8+hum8A2iuLFCsCYIWiF8TUpWIyeFRZbDjYdzCdCquNtYJUe4LUwDm9lqQuiX NeODl+eXNgNs1VJW+CxZhiuo77nkK9ITAQ90APDAZ2M3KgwNnfTXkFJeL2aAaA== From: Marek Vasut DKIM-Signature: v=1; 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These include I2C3 configuration which is required to access the PMIC, PMIC regulator and QSPI NOR bootph-all properties to allow SPL to configure PMIC buck regulators and load from QSPI NOR respectively, etzpc bus switch to simple-bus to prevent interference from TFABOOT specific configuration, and RCC configuration to define clock tree configuration used by this platform. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi | 155 ++++++++++++++++++++- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index 6117da10bbf..b5952637442 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2024 Marek Vasut */ +#include #include "stm32mp13-u-boot.dtsi" #include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi" @@ -19,8 +20,12 @@ }; }; +&etzpc { + compatible = "simple-bus"; +}; + &flash0 { - bootph-pre-ram; + bootph-all; partitions { compatible = "fixed-partitions"; @@ -49,6 +54,134 @@ }; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; +}; + +&qspi { + bootph-all; +}; + +&qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&pinctrl { + bootph-all; + i2c3_pins_a: i2c3-0 { + bootph-all; + pins { + bootph-all; + pinmux = , /* I2C3_SCL */ + ; /* I2C3_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; +}; + +&rcc { + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; + + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_CKPER_HSE + CLK_RTC_LSE + CLK_MCO1_LSI + CLK_MCO2_HSI + >; + + st,clkdiv = < + 0 /*AXI*/ + 0 /*MLHAB*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 1 /*APB6*/ + 0 /*RTC*/ + >; + + st,pkcs = < + CLK_I2C12_HSI + CLK_I2C3_HSI + CLK_QSPI_PLL3R + CLK_SAES_AXI + CLK_SDMMC1_PLL3R + CLK_SDMMC2_PLL3R + CLK_STGEN_HSE + CLK_UART2_HSI + CLK_UART4_HSI + CLK_USBO_USBPHY + CLK_USBPHY_HSE + >; + + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 1 0 PQR(1,1,1) >; + frac = < 0x1400 >; + bootph-all; + }; + + /* VCO = 600 MHz => P = 200, Q = 150, R = 200 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 2 74 2 3 2 PQR(1,1,1) >; + bootph-all; + }; + + /* VCO = 750.0 MHz => P = 125, Q = 83, R = 75 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 124 5 8 9 PQR(1,1,1) >; + bootph-all; + }; +}; + &sdmmc1 { status = "disabled"; }; @@ -56,3 +189,23 @@ &usbotg_hs { u-boot,force-b-session-valid; }; + +&vddcpu { + bootph-all; +}; + +&vdd_ddr { + bootph-all; +}; + +&vdd { + bootph-all; +}; + +&vddcore { + bootph-all; +}; + +&vref_ddr { + bootph-all; +}; From patchwork Mon May 12 17:21:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 2084564 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=BD9Iwdve; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=FxnmwQK6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Mon, 12 May 2025 19:22:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747070552; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CoezvAeJd1KGre7JYI98rybiGH8qNmV6pfabsBy5K9k=; b=BD9IwdveGhUibhc11K8BX9ZUP0bcg4zwKCLWs/52I30jbTLFgUHQdtBXtBUVAEg0rECxkR YWPulF9gA28Kk6BsgXdADLwUwNH3YK/BvG4Cx+AIezsJs2WY/JwmkwV7bKOl6W/fx0FDCK mcFld5UivhurFfFI79TjXhhn1SqPXznQAGWWrdh6QFOHzBsgBlmV5XnJUW0zByjmlYljBj fJehn/W/YPGfFQt57v4ImXr8Izinf9mD9MtSTUuxZlFq6qv13/BUeDeJ1J7xwNawjN/dGP Lm6RiShF/kOF/6mwpcG8sYbngRpSrNT4UrVBC1EOs8fVszy1lcXDOQQV3ibudg== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747070550; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CoezvAeJd1KGre7JYI98rybiGH8qNmV6pfabsBy5K9k=; b=FxnmwQK6cLC22g+nmq/rX4hl/iXuMEl+v+QUQI7mmyZ3dmYjC8rgrmCnBBplPxJE6x/mtp BeqqqmKHbE/+C8b8Y1Izrk/2+/GORck2Y5cCwa14yp5UJ29NFq4WM8cmDZxjeiBXiu6AQB OZSJJN8JB05fcqblH1mp2TwqQM/qiO/qRp+wxA2YKWN0crnlAZ5Fqbhz0KkqAeNW9VVMtA hVQv03jIssRfwjyaIMIg/Ak6tQPlZ4H2pbYsKHsW8mQEknbVhhyUMtdETe2uVnp1knEbnb DoJvIp69ETTh++bWj6O9zUNQivVEj6WCfPgX0NnQbtfjJpf6LcNZ39WYVzN+lw== To: u-boot@lists.denx.de Cc: Marek Vasut , Cheick Traore , Fabrice Gasnier , Gatien Chevallier , Lionel Debieve , Pascal Zimmermann , Patrice Chotard , Patrick Delaunay , Simon Glass , Sughosh Ganu , Tom Rini , u-boot@dh-electronics.com, uboot-stm32@st-md-mailman.stormreply.com Subject: [PATCH 10/10] ARM: dts: stm32: Switch defconfig to SPL for DH STM32MP13xx DHCOR DHSBC Date: Mon, 12 May 2025 19:21:37 +0200 Message-ID: <20250512172149.150214-11-marek.vasut@mailbox.org> In-Reply-To: <20250512172149.150214-1-marek.vasut@mailbox.org> References: <20250512172149.150214-1-marek.vasut@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: 625241e21a5b107c39f X-MBO-RS-META: ozg7at9qwbwcmo1p4f7xre6pg9wkiukn X-Rspamd-Queue-Id: 4Zx5yc5Gz5z9tST X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update defconfig to make use of U-Boot SPL to initialize DH STM32MP13xx DHCOM DHSBC SoM and board. This is largely a move of SPL enablement from DH STM32MP15xx DHSOM defconfigs into generic DH STM32MP1xx defconfig . Support for SPI NOR chips which are not used on STM32MP13xx DHCOR are moved into STM32MP15xx DHSOM defconfigs. Changes to STM32MP13xx DHCOR defconfig then enable SPL support, CCF in SPL to configure clock, pin configuration support in SPL, and OpTee OS start support in U-Boot. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- configs/stm32mp13_dhcor_defconfig | 30 +++++++++++++------ configs/stm32mp15_dhsom.config | 48 +++++-------------------------- configs/stm32mp_dhsom.config | 35 ++++++++++++++++++++-- 3 files changed, 60 insertions(+), 53 deletions(-) diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig index 2da9287ea7b..0d70aab5e8f 100644 --- a/configs/stm32mp13_dhcor_defconfig +++ b/configs/stm32mp13_dhcor_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y -CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x1c0000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000 CONFIG_ENV_OFFSET=0x3E0000 @@ -12,11 +11,16 @@ CONFIG_DDR_CACHEABLE_SIZE=0x8000000 CONFIG_TARGET_ST_STM32MP13X=y CONFIG_ENV_OFFSET_REDUND=0x3F0000 CONFIG_STM32MP15_PWR=y -# CONFIG_ARMV7_NONSEC is not set +CONFIG_ARMV7_NONSEC=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_ARMV7_PSCI_NR_CPUS=2 +# CONFIG_ARMV7_LPAE is not set CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_SYS_MEM_TOP_HIDE=0x2000000 CONFIG_BOOTSTAGE_RECORD_COUNT=100 CONFIG_BOOTDELAY=3 +CONFIG_BOOTM_OPTEE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_CMD_ASKENV=y CONFIG_CMD_ERASEENV=y @@ -31,20 +35,28 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_MMC_USE_DT=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SYS_MMC_ENV_DEV=0 CONFIG_SYS_MMC_ENV_PART=1 CONFIG_PHY_REALTEK=y -CONFIG_DM_REGULATOR_SCMI=y -CONFIG_RESET_SCMI=y CONFIG_DM_RNG=y CONFIG_RNG_STM32=y -CONFIG_SYSRESET_PSCI=y -CONFIG_TEE=y -CONFIG_OPTEE=y -# CONFIG_OPTEE_TA_AVB is not set CONFIG_USB_ONBOARD_HUB=y CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000 CONFIG_ERRNO_STR=y +CONFIG_OPTEE_LIB=y +CONFIG_OPTEE_IMAGE=y +CONFIG_OPTEE_TZDRAM_SIZE=0x02000000 +CONFIG_SPL_TEXT_BASE=0x2FFE0000 +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +# CONFIG_SPL_SHA1 is not set +# CONFIG_SPL_SHA256 is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_PINCTRL_GENERIC=y +CONFIG_SPL_PINMUX=y +CONFIG_SPL_PINCONF=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index c84116482f6..f7ff5db5943 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -2,10 +2,6 @@ # CONFIG_ARMV7_VIRT is not set # CONFIG_BINMAN_FDT is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_PARTITION_UUIDS is not set -# CONFIG_SPL_PINCTRL_FULL is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_SIZE_LIMIT=1441792 CONFIG_BOOTCOUNT_BOOTLIMIT=3 @@ -20,9 +16,7 @@ CONFIG_CMD_STM32PROG_OTP=y CONFIG_CONSOLE_MUX=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_DM_HWSPINLOCK=y -CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_HAS_BOARD_SIZE_LIMIT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HWSPINLOCK_STM32=y CONFIG_KS8851_MLL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" @@ -31,42 +25,7 @@ CONFIG_PINCTRL_STMFX=y CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_SERVERIP="192.168.1.1" CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_SPL=y -CONFIG_SPL_BLOCK_CACHE=y -CONFIG_SPL_BOOTCOUNT_LIMIT=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 -CONFIG_SPL_DFU=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR_STPMIC1=y -CONFIG_SPL_DM_SPI=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_DM_USB_GADGET=y -CONFIG_SPL_ENV_IS_NOWHERE=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FOOTPRINT_LIMIT=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_I2C=y -CONFIG_SPL_LEGACY_IMAGE_FORMAT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 -CONFIG_SPL_MAX_FOOTPRINT=0x3db00 -CONFIG_SPL_MMC=y -CONFIG_SPL_MTD=y -CONFIG_SPL_PHY=y -CONFIG_SPL_POWER=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_SPI=y -CONFIG_SPL_SPI_FLASH_MTD=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_HAVE_INIT_STACK=y -CONFIG_SPL_STACK=0x30000000 -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_USB_GADGET=y CONFIG_STM32_ADC=y -CONFIG_SYSRESET_SYSCON=y CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y @@ -76,3 +35,10 @@ CONFIG_PREBOOT="run dh_preboot" CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_TARGET_DH_STM32MP1_PDK2=y CONFIG_USE_SERVERIP=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +CONFIG_SPL_TEXT_BASE=0x2FFC2500 +CONFIG_SPL_BLOCK_CACHE=y +CONFIG_SPL_MMC=y diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config index 01d65cfd893..13f9186b1cf 100644 --- a/configs/stm32mp_dhsom.config +++ b/configs/stm32mp_dhsom.config @@ -2,6 +2,10 @@ # CONFIG_CMD_EXPORTENV is not set # CONFIG_EFI_LOADER is not set # CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +# CONFIG_SPL_PINCTRL_FULL is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CMD_BOOTCOUNT=y @@ -38,6 +42,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_RTC=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y @@ -49,6 +54,7 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_FAT_WRITE=y CONFIG_FIT=y CONFIG_GPIO_HOG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_I2C_EEPROM=y CONFIG_IPV6=y CONFIG_IP_DEFRAG=y @@ -58,6 +64,7 @@ CONFIG_MTD=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y CONFIG_PINCONF=y @@ -66,17 +73,39 @@ CONFIG_PROT_TCP_SACK=y CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SPI=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_MTD=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPL=y +CONFIG_SPL_BOOTCOUNT_LIMIT=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 +CONFIG_SPL_DFU=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_I2C=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +CONFIG_SPL_MTD=y +CONFIG_SPL_PHY=y +CONFIG_SPL_POWER=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_STACK=0x30000000 +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_STM32_FMC2_EBI=y CONFIG_STM32_QSPI=y CONFIG_STM32_SDMMC2=y CONFIG_STM32_SPI=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SYSRESET_SYSCON=y CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_DISABLE_AUTOLOAD=y