From patchwork Mon May 21 10:18:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 917514 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-478039-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ll731XD2"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40qFBj66nJz9s16 for ; Mon, 21 May 2018 20:19:40 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=hIgtYIWqdmAQ Caf7XwxayMCWJ+umoMs3yjJl3d6TzmmoIm4zvfSGCLqFqI8WNks5q87vwDcKz5CY CDlIC5EPGNiOiKUQGA7oJ6g8ZROCCKx4MaHY5ZqxjmnwksbVIc10ku9hlsXcJQg5 nO+y4w3Sf4uqwj0TZacfTa3kUi3waek= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=jHXnU2yeHgEuYW8rHu 7Wjv1+oec=; b=ll731XD2L/n2jnvF8cMKZxzG9sEYYQQfYOKbM1e6cQs/lCD3uT 1LOAQohhbrIS3YcovuAP56R6KMtP79HfCn4zHODcvKi0u69X9pPBtETesxws30o0 6NA80dVN/orKMLDChkX7RwgXKcNCDK0zteSocF+SxIQS+5oDhylub1Qlk= Received: (qmail 25369 invoked by alias); 21 May 2018 10:19:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25345 invoked by uid 89); 21 May 2018 10:19:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Advanced, *12, modes X-HELO: mail-wr0-f173.google.com Received: from mail-wr0-f173.google.com (HELO mail-wr0-f173.google.com) (209.85.128.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 May 2018 10:19:30 +0000 Received: by mail-wr0-f173.google.com with SMTP id r13-v6so3089800wrj.10 for ; Mon, 21 May 2018 03:19:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lrq1+yJ86eMdso+l86z9ZVwJ9qyRdyB0BUr2ZMv3I4g=; b=WJryLEOuf2tiobV3fcLb9XWTbevXEcqeg19qfvcZjn0sA7qfxztwW/9MrYAL/FBnid nolOW6n6fAHk4QACYqjtiuNtYbWZB1Xx9RNi3UqE0uurxIxtaIV38HsoEgg2zLn6jhcC 0HCGeyU+yNKt8YXBKe4SQQJbVnN9WeiPezdEMF3xaj7MWQQMIXI/U1M5+nzChWAHWLBF BbPeH9lfM0YlvtdaP7+2z8eMkO3FALKAx+HO+igf1VgWgfnySDSzEdHJsYFXO9b4Jxig O8PsCStuuW23wLDMmoWEBS8YNkZXTggn/KwvVNKkSCc0WQ7Wr2XxyxZ3SHoEQMRbEfDO UZQg== X-Gm-Message-State: ALKqPwdWaSngl4cEIfK+Iv/sqK5FCPELv2LD5Dpp/kBN1FFQm6y5N6qI zJBclpMsQRoM1VwsH/NqXLRdXQ== X-Google-Smtp-Source: AB8JxZpDVgnnH7hSrFDn5gAcSgEPBLJD6RWbhpWGoMhaxZUqMm/cWtZ8oVAlLlPvyQ/IasuteIdlzA== X-Received: by 2002:adf:b353:: with SMTP id k19-v6mr11851460wrd.207.1526897968122; Mon, 21 May 2018 03:19:28 -0700 (PDT) Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id k23-v6sm17109788wrc.59.2018.05.21.03.19.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 03:19:27 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, claziss@synopsys.comq, Claudiu Zissulescu Subject: [PATCH 1/6] [ARC] Add modes scheduler HS Date: Mon, 21 May 2018 13:18:34 +0300 Message-Id: <20180521101839.13288-1-claziss@gmail.com> X-IsSubscribed: yes From: Claudiu Zissulescu An update on how the instructions are scheduled for HS processor. Ok to apply? Claudiu --- gcc/config/arc/arcHS.md | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/gcc/config/arc/arcHS.md b/gcc/config/arc/arcHS.md index d49b90c4970..5c1ab5413ab 100644 --- a/gcc/config/arc/arcHS.md +++ b/gcc/config/arc/arcHS.md @@ -35,12 +35,14 @@ (eq_attr "type" "store")) "hs_issue+hs_ld_st") -(define_insn_reservation "hs_alu0" 2 +;; Advanced ALU +(define_insn_reservation "hs_alu0" 4 (and (match_test "TARGET_HS") (eq_attr "tune" "none") (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr")) - "hs_issue+x1,x2") + "hs_issue+x1,x2, nothing*2") +;; Basic ALU (define_insn_reservation "hs_alu1" 4 (and (match_test "TARGET_HS") (eq_attr "tune" "none") @@ -54,19 +56,26 @@ (eq_attr "type" "div_rem")) "hs_issue+divrem_hs, (divrem_hs)*12") -(define_insn_reservation "hs_mul" 3 +(define_insn_reservation "hs_mul" 4 (and (match_test "TARGET_HS") (eq_attr "tune" "none") (eq_attr "type" "mul16_em, multi, umulti")) "hs_issue+mul_hs, nothing*3") -;; BYPASS EALU -> +;; BYPASS Advanced ALU -> (define_bypass 1 "hs_alu0" "hs_divrem") (define_bypass 1 "hs_alu0" "hs_mul") +(define_bypass 2 "hs_alu0" "hs_alu0") +(define_bypass 1 "hs_alu0" "hs_alu1") +(define_bypass 1 "hs_alu0" "hs_data_load") +(define_bypass 1 "hs_alu0" "hs_data_store" "store_data_bypass_p") +(define_bypass 2 "hs_alu0" "hs_data_store") -;; BYPASS BALU -> +;; BYPASS Basic ALU -> (define_bypass 1 "hs_alu1" "hs_alu1") (define_bypass 1 "hs_alu1" "hs_data_store" "store_data_bypass_p") +(define_bypass 3 "hs_alu1" "hs_mul") +(define_bypass 3 "hs_alu1" "hs_divrem") ;; BYPASS LD -> (define_bypass 1 "hs_data_load" "hs_alu1") @@ -76,7 +85,7 @@ (define_bypass 1 "hs_data_load" "hs_data_store" "store_data_bypass_p") ;; BYPASS MPY -> -;;(define_bypass 3 "hs_mul" "hs_mul") +(define_bypass 3 "hs_mul" "hs_mul") (define_bypass 1 "hs_mul" "hs_alu1") (define_bypass 3 "hs_mul" "hs_divrem") (define_bypass 1 "hs_mul" "hs_data_store" "store_data_bypass_p") From patchwork Mon May 21 10:18:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 917515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-478040-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="QdXTA49m"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40qFBv6rw3z9s19 for ; Mon, 21 May 2018 20:19:51 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; 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Mon, 21 May 2018 03:19:29 -0700 (PDT) Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id k23-v6sm17109788wrc.59.2018.05.21.03.19.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 03:19:28 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, claziss@synopsys.comq, claziss Subject: [PATCH 2/6] [ARC] Allow EX instruction for ARC700 and ARCv2. Date: Mon, 21 May 2018 13:18:35 +0300 Message-Id: <20180521101839.13288-2-claziss@gmail.com> In-Reply-To: <20180521101839.13288-1-claziss@gmail.com> References: <20180521101839.13288-1-claziss@gmail.com> X-IsSubscribed: yes From: claziss The EX instruction is base line for both architectures. Reflect this in the compiler. OK to apply? Claudiu gcc/ 2017-05-02 Claudiu Zissulescu * config/arc/arc.c (atomic_exchangesi): EX instruction is default for ARC700 and ARCv2. --- gcc/config/arc/atomic.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/atomic.md b/gcc/config/arc/atomic.md index 13a2e34549c..4a56ca229cc 100644 --- a/gcc/config/arc/atomic.md +++ b/gcc/config/arc/atomic.md @@ -120,7 +120,7 @@ (match_operand:SI 1 "mem_noofs_operand" "") (match_operand:SI 2 "register_operand" "") (match_operand:SI 3 "const_int_operand" "")] - "TARGET_ATOMIC" + "TARGET_ARC700 || TARGET_V2" { enum memmodel model = (enum memmodel) INTVAL (operands[3]); From patchwork Mon May 21 10:18:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 917516 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-478041-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="DCxNysc3"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40qFC755qtz9s16 for ; Mon, 21 May 2018 20:20:03 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=v6lzf5DvSXxFFwHcu4w10EYFkadieHBhojTdV4hV4a6uvqc7umDWV NjoCHcLdOU+z+BkUdIp1Ktx8JEH/8B+ogphYEXnH/mb9L9rcdMtZl873VuwZosyP GPTC4AdS2MEzpxdKF5VZcieQiUW49aZFItsMSqUltfq/9WEQNYPiuM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=xLYXfMD6KKFdlR1YEbiV9d8hPmI=; b=DCxNysc3Eufds5yhFZIv bzAsluTWgsIo8010vvRdiB2ystzLl+pLxr/JEGirWdPp1C92+jmRErVL/uXIHvGE r/3mleBqEJ4m17WREmLJDFALPcuSNGSMsj3x0WaFxJyatJvJneliXDB2Ltwjm61n qqxFnIyfyiQMkAMzHL/1348= Received: (qmail 25588 invoked by alias); 21 May 2018 10:19:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25466 invoked by uid 89); 21 May 2018 10:19:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=cores X-HELO: mail-wr0-f180.google.com Received: from mail-wr0-f180.google.com (HELO mail-wr0-f180.google.com) (209.85.128.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 May 2018 10:19:32 +0000 Received: by mail-wr0-f180.google.com with SMTP id a15-v6so8157719wrm.0 for ; Mon, 21 May 2018 03:19:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pptkCNLUA7pi0A7/pYaZRAKdh1vyLB1WesYKENFAeBE=; b=OgSfjGHPpiX2Y6bUt7liM9gD5srA/69373+RbG41NTwqwKq/21o6AeUAo5pIkq/Ax/ BrAflTL8iV9ePlnvI1BQUR0s2+fv72J78Ud8KetU2uTfEZvVVRY/A/w72iW2Ugf2rstr +te5WNQZ/NILbgKbzcliL45oj/YqEz7Qu8+OgsyCY6H0qKIAPYQAdlZpR+V+plINEbef +dte54XD2/RCfVly5Krp0FX6BGn5acPkGQxug0plUVkeXFCy2wXpKFaYMTW/4+5tH2Hq a6y3FwhcBzoq2Q87vZSpTclt/EGTg/vQfpoxQeqJKyt+yHF/bayoKb0IAVY5Qq5G15aL gTbg== X-Gm-Message-State: ALKqPwdS2eRdasc4WUBm2Px833UdJz09Z+n6KMRSg1hxcYF1WywcrEpB v8g/vgMmCFfIdGgLcq6KXsYmcgaQ X-Google-Smtp-Source: AB8JxZpm8W3S55+V4XgQV+foVXlWuA5DGbxnaPKSY06o41c3a5/A8Wt28CqqwmZjIU7fPO0lk6bohA== X-Received: by 2002:a5d:408a:: with SMTP id o10-v6mr5438103wrp.133.1526897970097; Mon, 21 May 2018 03:19:30 -0700 (PDT) Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id k23-v6sm17109788wrc.59.2018.05.21.03.19.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 03:19:29 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, claziss@synopsys.comq, claziss Subject: [PATCH 3/6] [ARC] SYNC instruction is valid on all ARC cores. Date: Mon, 21 May 2018 13:18:36 +0300 Message-Id: <20180521101839.13288-3-claziss@gmail.com> In-Reply-To: <20180521101839.13288-1-claziss@gmail.com> References: <20180521101839.13288-1-claziss@gmail.com> X-IsSubscribed: yes From: claziss The sync instruction is part of all ARC architectures. Fix this in the compiler. Ok to apply? Claudiu gcc/ 2017-05-03 Claudiu Zissulescu * config/arc/builtins.def (SYNC): SYNC instruction is valid on all ARC cores. --- gcc/config/arc/builtins.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/builtins.def b/gcc/config/arc/builtins.def index 349f39fab23..5171ab40842 100644 --- a/gcc/config/arc/builtins.def +++ b/gcc/config/arc/builtins.def @@ -34,7 +34,7 @@ /* Special builtins. */ DEF_BUILTIN (NOP, 0, void_ftype_void, nothing, 1) DEF_BUILTIN (RTIE, 0, void_ftype_void, rtie, 1) -DEF_BUILTIN (SYNC, 0, void_ftype_void, sync, TARGET_ARC700) +DEF_BUILTIN (SYNC, 0, void_ftype_void, sync, 1) DEF_BUILTIN (BRK, 0, void_ftype_void, brk, 1) DEF_BUILTIN (SWI, 0, void_ftype_void, swi, 1) DEF_BUILTIN (UNIMP_S, 0, void_ftype_void, unimp_s, !TARGET_ARC600_FAMILY) From patchwork Mon May 21 10:18:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 917517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-478042-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="pNtIkrcU"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40qFCM46jRz9s16 for ; Mon, 21 May 2018 20:20:15 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=NbYOa80whPl1RQyWGzqE1tU/R4P3cn7l6JJeDnZPJEsOu9PLaY7EM UBkQ0wenkGhECEqW7pzUTWnwcreBLF3lONvUSF1eHo0Nm1QelLkbskCoAKYBZ+co 9n34CmDtaoVLJp47kMJCVj/CgZmjK7D8gDotKNgU9EIdpcze3UWnxk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=1k1Dt2ZuAkGyVxsgN/Q6qgxtcC0=; b=pNtIkrcUt4UxY4SF2OfG 2MVDSZqfdA7/7+A26sep7wj+jKr6tIULc/mkCauCAqQT7zhOw7oZfHpQNw1xDW0S rHaEyNx0Ll1PgbRTjiwpsK/GvMCwQrWmtI4Eminn9xRIfvEXY95sEAe4xXJ4FUQa LPGsM5mS6xl83Ylrw87bF/Y= Received: (qmail 25727 invoked by alias); 21 May 2018 10:19:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25643 invoked by uid 89); 21 May 2018 10:19:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr0-f176.google.com Received: from mail-wr0-f176.google.com (HELO mail-wr0-f176.google.com) (209.85.128.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 May 2018 10:19:33 +0000 Received: by mail-wr0-f176.google.com with SMTP id 94-v6so15435120wrf.5 for ; Mon, 21 May 2018 03:19:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OXl1BJf6KLB0DyECE6jquQji9SD7tqDePUtNKnNTk5g=; b=WqnTy2fv0+UE9xXTBm9jHSuBxaGcD43aJGetpr9oJVmPD7RUQ2eRhZSuxpAjTVYwzr XvQd5oFoNieGUusle8IeR0cERfwXoG7ZMC+zUj/YFkv7pkkgraLGc80s+shrH/LpW0bz 7VQI1ApLvz0WsZBNwQYjsunnh2SQsEa78cSv4a6A4t0z1Wy1FlupwxW/Hw61g0AJw5FU qsbBEI+eFM7XOlaFtCZER3UaKaJXiWSvgpFdLOjjM6k3vgnfAm8xdPCVhc8wYVdLRgSp CY7H3kKXIzsqrEU+d9BLHluN+1J6kIy1vkmzcrQX0ISbxCJwsoyWzauo3Z64+OYnRKfv Yq6g== X-Gm-Message-State: ALKqPwcbr6kuS/ISk14vUUKPSztW5ET6xZooOlNMPWegEh7HjeGQPCWi hxlvQyUoYJe0OyNPA3fFwA9ilY3h X-Google-Smtp-Source: AB8JxZo/sxTMq6QEXppIBR1c+7TTzwMcQJ2Mzg0UwDIm9dDSEO2kkaonz5oNJU/dGm9qodpdTwwqZg== X-Received: by 2002:adf:a075:: with SMTP id l50-v6mr16304149wrl.227.1526897971053; Mon, 21 May 2018 03:19:31 -0700 (PDT) Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id k23-v6sm17109788wrc.59.2018.05.21.03.19.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 03:19:30 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, claziss@synopsys.comq, claziss Subject: [PATCH 4/6] [ARC] Define LINK_GCC_C_SEQUENCE_SPEC. Date: Mon, 21 May 2018 13:18:37 +0300 Message-Id: <20180521101839.13288-4-claziss@gmail.com> In-Reply-To: <20180521101839.13288-1-claziss@gmail.com> References: <20180521101839.13288-1-claziss@gmail.com> X-IsSubscribed: yes From: claziss If no specs file is provided, default to nosys library. Ok to apply? Claudiu gcc/ 2017-05-03 Claudiu Zissulescu * config/arc/elf.h (LINK_GCC_C_SEQUENCE_SPEC): Define. --- gcc/config/arc/elf.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h index 43ced3b720f..66ee5b698ea 100644 --- a/gcc/config/arc/elf.h +++ b/gcc/config/arc/elf.h @@ -73,3 +73,8 @@ along with GCC; see the file COPYING3. If not see #undef TARGET_ASM_FILE_END #define TARGET_ASM_FILE_END arc_file_end + +/* If no specs file is enforced, default to nosys libarary. */ +#undef LINK_GCC_C_SEQUENCE_SPEC +#define LINK_GCC_C_SEQUENCE_SPEC \ + "--start-group %G %{!specs=*:-lc -lnosys} --end-group" From patchwork Mon May 21 10:18:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 917518 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-478043-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Hz3ydygM"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40qFCc1gMjz9s37 for ; Mon, 21 May 2018 20:20:28 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=JpNUJkd2KWZ70E5ofomsV5cIlhyKB6qlwSZOTbxxgSJU8eiv8Z96E khMjUyIFKpzYhbkraoMXqh2V5xKuVeQV8ewrhaFNgoAGx2LQTbCwm6oMZZEvE08V DU4ct2VlI3fh1EieaJ7Tv7EMaVLpR6bdVlCyKlLoRaRkp3mpfbGZYI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=a/jdRd66jPnShMkRlD1kfckuW7E=; b=Hz3ydygMzdsUY7fjuIWL mDtgy4FjymPqBe1cWKOnu7ofQyPprgCLuOqoxYxDveS2E3F/vDN9cpQE9Ypy/g8h X44RlJd5+162jhEAelN5dnAR882M3uOQusuGTzdym2q8H1d2j3j4+Q+meYK1061d OYFPajvPVved8dyEwBBQ0SI= Received: (qmail 25958 invoked by alias); 21 May 2018 10:19:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25842 invoked by uid 89); 21 May 2018 10:19:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Force X-HELO: mail-wm0-f41.google.com Received: from mail-wm0-f41.google.com (HELO mail-wm0-f41.google.com) (74.125.82.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 May 2018 10:19:34 +0000 Received: by mail-wm0-f41.google.com with SMTP id a137-v6so11486546wme.1 for ; Mon, 21 May 2018 03:19:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y5ohrAAMKEs3pNUc9etyKLQWQObhBNnuon7XuaLZZAc=; b=d4obJ9go+YwJCyyU7l7V8IqQOlE5UOX21UQPoHALvVZ1EnGFAPJ2mZ+ls76uicdY60 vqYzWMCiTpHqLU2SLuig/6BAb9InCzQIrpk/33IMXebgS9Y5+6lwKQnog+a7VhGKYXXC 3IL7ripKGAicfEwBjTrPVDyls3lQHONQYECvpKuBIACBXbZolj01GGUdkmkNj/+ihy/1 NhDxJwQMD21LOqWerwLiqZ1P3TtjhS16dUrev2PH8cizj1PSuUlpga8kr1tYZh5sbG1B GC9Sywre1ssTQRy7VJpCw4YWWHu12qGxlvfEwqZk8WDpijrTRF2zc0z0nNslte+7BURH XOdw== X-Gm-Message-State: ALKqPwdK6DcsHkqoflBk94uP30dp+qVy3cnW2V1Ux3YRzg6e/PiPiKys OEipe2sU/20ihnYTr9O4ShbBVw== X-Google-Smtp-Source: AB8JxZqVuNPT4e35ZQ29MovVB3nVvseEGMNrf8PZtKJFgbn4mH3OPuUA7tCmRVqW1v2kbn1MN0L5JA== X-Received: by 2002:a1c:ec4b:: with SMTP id k72-v6mr11221328wmh.27.1526897971917; Mon, 21 May 2018 03:19:31 -0700 (PDT) Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id k23-v6sm17109788wrc.59.2018.05.21.03.19.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 03:19:31 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, claziss@synopsys.comq Subject: [PATCH 5/6] [ARC] Update fma expansions. Date: Mon, 21 May 2018 13:18:38 +0300 Message-Id: <20180521101839.13288-5-claziss@gmail.com> In-Reply-To: <20180521101839.13288-1-claziss@gmail.com> References: <20180521101839.13288-1-claziss@gmail.com> X-IsSubscribed: yes Make sure only one operand has an immediate. OK to apply? Claudiu gcc/ 2018-03-21 Claudiu Zissulescu * config/arc/fpu.md (fmasf4): Force operand to register. (fnmasf4): Likewise. gcc/testsuite 2018-03-21 Claudiu Zissulescu * gcc.target/arc/fma-1.c: New test. --- gcc/config/arc/fpu.md | 6 ++++++ gcc/testsuite/gcc.target/arc/fma-1.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arc/fma-1.c diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md index de876cac0c1..9457922667e 100644 --- a/gcc/config/arc/fpu.md +++ b/gcc/config/arc/fpu.md @@ -64,6 +64,9 @@ tmp = gen_rtx_REG (SFmode, ACCL_REGNO); emit_move_insn (tmp, operands[3]); operands[3] = tmp; + if (!register_operand (operands[1], SFmode) + && !register_operand (operands[2], SFmode)) + operands[2] = force_reg (SFmode, operands[2]); }") (define_expand "fnmasf4" @@ -77,6 +80,9 @@ tmp = gen_rtx_REG (SFmode, ACCL_REGNO); emit_move_insn (tmp, operands[3]); operands[3] = tmp; + if (!register_operand (operands[1], SFmode) + && !register_operand (operands[2], SFmode)) + operands[2] = force_reg (SFmode, operands[2]); }") (define_insn "fmasf4_fpu" diff --git a/gcc/testsuite/gcc.target/arc/fma-1.c b/gcc/testsuite/gcc.target/arc/fma-1.c new file mode 100644 index 00000000000..c195ad98127 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/fma-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-skip-if "FPU not available" { arc700 || arc6xx } } */ +/* { dg-options "-s -std=gnu11 -O2 -frounding-math -mfpu=fpus_all" } */ + +const float a, b = 7.8539818525e01; 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Mon, 21 May 2018 03:19:32 -0700 (PDT) Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id k23-v6sm17109788wrc.59.2018.05.21.03.19.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 03:19:32 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, claziss@synopsys.comq, Claudiu Zissulescu Subject: [PATCH 6/6] [ARC] Reimplement return padding operation for ARC700. Date: Mon, 21 May 2018 13:18:39 +0300 Message-Id: <20180521101839.13288-6-claziss@gmail.com> In-Reply-To: <20180521101839.13288-1-claziss@gmail.com> References: <20180521101839.13288-1-claziss@gmail.com> X-IsSubscribed: yes From: Claudiu Zissulescu For ARC700, adding padding if necessary to avoid a mispredict. A return could happen immediately after the function start. A call/return and return/return must be 6 bytes apart to avoid mispredict. The old implementation was doing this operation very late in the compilation process, and the additional nop instructions and/or forcing some other instruction to take their long form was not taken into account when generating brcc instructions. Thus, wrong code could be generated. Ok to apply? Claudiu gcc/ 2017-03-24 Claudiu Zissulescu * config/arc/arc-protos.h (arc_pad_return): Remove. * config/arc/arc.c (machine_function): Remove force_short_suffix and size_reason. (arc_print_operand): Adjust printing of '&'. (arc_verify_short): Remove conditional printing of short suffix. (arc_final_prescan_insn): Remove reference to size_reason. (pad_return): New function. (arc_reorg): Call pad_return. (arc_pad_return): Remove. (arc_init_machine_status): Remove reference to force_short_suffix. * config/arc/arc.md (vunspec): Add VUNSPEC_ARC_BLOCKAGE. (attr length): When attribute iscompact is true force to 2 regardless; in the case of maybe check if we want to force the instruction to have 4 bytes length. (nopv): Change it to generate 4 byte long nop as well. (blockage): New pattern. (simple_return): Remove call to arc_pad_return. (p_return_i): Likewise. gcc/testsuite/ 2017-03-24 Claudiu Zissulescu * gcc.target/arc/pr9001107555.c: New file. --- gcc/config/arc/arc-protos.h | 1 - gcc/config/arc/arc.c | 156 +++++++++++++--------------- gcc/config/arc/arc.md | 26 +++-- gcc/testsuite/gcc.target/arc/pr9001107555.c | 38 +++++++ 4 files changed, 128 insertions(+), 93 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/pr9001107555.c diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index 67f3b4e3226..ce4b6f84749 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -89,7 +89,6 @@ extern void arc_clear_unalign (void); extern void arc_toggle_unalign (void); extern void split_addsi (rtx *); extern void split_subsi (rtx *); -extern void arc_pad_return (void); extern void arc_split_move (rtx *); extern const char *arc_short_long (rtx_insn *insn, const char *, const char *); extern rtx arc_regno_use_in (unsigned int, rtx); diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index b1a09d82b72..22f1442a027 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -2648,8 +2648,6 @@ typedef struct GTY (()) machine_function struct arc_frame_info frame_info; /* To keep track of unalignment caused by short insns. */ int unalign; - int force_short_suffix; /* Used when disgorging return delay slot insns. */ - const char *size_reason; struct arc_ccfsm ccfsm_current; /* Map from uid to ccfsm state during branch shortening. */ rtx ccfsm_current_insn; @@ -4307,7 +4305,7 @@ arc_print_operand (FILE *file, rtx x, int code) } break; case '&': - if (TARGET_ANNOTATE_ALIGN && cfun->machine->size_reason) + if (TARGET_ANNOTATE_ALIGN) fprintf (file, "; unalign: %d", cfun->machine->unalign); return; case '+': @@ -4980,7 +4978,6 @@ static int arc_verify_short (rtx_insn *insn, int, int check_attr) { enum attr_iscompact iscompact; - struct machine_function *machine; if (check_attr > 0) { @@ -4988,10 +4985,6 @@ arc_verify_short (rtx_insn *insn, int, int check_attr) if (iscompact == ISCOMPACT_FALSE) return 0; } - machine = cfun->machine; - - if (machine->force_short_suffix >= 0) - return machine->force_short_suffix; return (get_attr_length (insn) & 2) != 0; } @@ -5030,8 +5023,6 @@ arc_final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED, cfun->machine->prescan_initialized = 1; } arc_ccfsm_advance (insn, &arc_ccfsm_current); - - cfun->machine->size_reason = 0; } /* Given FROM and TO register numbers, say whether this elimination is allowed. @@ -7673,6 +7664,76 @@ jli_call_scan (void) } } +/* Add padding if necessary to avoid a mispredict. A return could + happen immediately after the function start. A call/return and + return/return must be 6 bytes apart to avoid mispredict. */ + +static void +pad_return (void) +{ + rtx_insn *insn; + long offset; + + if (!TARGET_PAD_RETURN) + return; + + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + rtx_insn *prev0 = prev_active_insn (insn); + bool wantlong = false; + + if (!INSN_P (insn) || GET_CODE (PATTERN (insn)) != SIMPLE_RETURN) + continue; + + if (!prev0) + { + prev0 = emit_insn_before (gen_nopv (), insn); + /* REG_SAVE_NOTE is used by Haifa scheduler, we are in reorg + so it is safe to reuse it for forcing a particular length + for an instruction. */ + add_reg_note (prev0, REG_SAVE_NOTE, GEN_INT (1)); + emit_insn_before (gen_nopv (), insn); + continue; + } + offset = get_attr_length (prev0); + + if (get_attr_length (prev0) == 2 + && get_attr_iscompact (prev0) != ISCOMPACT_TRUE) + { + /* Force long version of the insn. */ + wantlong = true; + offset += 2; + } + + rtx_insn *prev = prev_active_insn (prev0); + if (prev) + offset += get_attr_length (prev); + + prev = prev_active_insn (prev); + if (prev) + offset += get_attr_length (prev); + + switch (offset) + { + case 2: + prev = emit_insn_before (gen_nopv (), insn); + add_reg_note (prev, REG_SAVE_NOTE, GEN_INT (1)); + break; + case 4: + emit_insn_before (gen_nopv (), insn); + break; + default: + continue; + } + + if (wantlong) + add_reg_note (prev0, REG_SAVE_NOTE, GEN_INT (1)); + + /* Emit a blockage to avoid delay slot scheduling. */ + emit_insn_before (gen_blockage(), insn); + } +} + static int arc_reorg_in_progress = 0; /* ARC's machince specific reorg function. */ @@ -7698,6 +7759,7 @@ arc_reorg (void) workaround_arc_anomaly (); jli_call_scan (); + pad_return (); /* FIXME: should anticipate ccfsm action, generate special patterns for to-be-deleted branches that have no delay slot and have at least the @@ -9256,79 +9318,6 @@ arc_branch_size_unknown_p (void) return !optimize_size && arc_reorg_in_progress; } -/* We are about to output a return insn. Add padding if necessary to avoid - a mispredict. A return could happen immediately after the function - start, but after a call we know that there will be at least a blink - restore. */ - -void -arc_pad_return (void) -{ - rtx_insn *insn = current_output_insn; - rtx_insn *prev = prev_active_insn (insn); - int want_long; - - if (!prev) - { - fputs ("\tnop_s\n", asm_out_file); - cfun->machine->unalign ^= 2; - want_long = 1; - } - /* If PREV is a sequence, we know it must be a branch / jump or a tailcall, - because after a call, we'd have to restore blink first. */ - else if (GET_CODE (PATTERN (prev)) == SEQUENCE) - return; - else - { - want_long = (get_attr_length (prev) == 2); - prev = prev_active_insn (prev); - } - if (!prev - || ((NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) - ? CALL_ATTR (as_a (PATTERN (prev))->insn (0), - NON_SIBCALL) - : CALL_ATTR (prev, NON_SIBCALL))) - { - if (want_long) - cfun->machine->size_reason - = "call/return and return/return must be 6 bytes apart to avoid mispredict"; - else if (TARGET_UNALIGN_BRANCH && cfun->machine->unalign) - { - cfun->machine->size_reason - = "Long unaligned jump avoids non-delay slot penalty"; - want_long = 1; - } - /* Disgorge delay insn, if there is any, and it may be moved. */ - if (final_sequence - /* ??? Annulled would be OK if we can and do conditionalize - the delay slot insn accordingly. */ - && !INSN_ANNULLED_BRANCH_P (insn) - && (get_attr_cond (insn) != COND_USE - || !reg_set_p (gen_rtx_REG (CCmode, CC_REG), - XVECEXP (final_sequence, 0, 1)))) - { - prev = as_a (XVECEXP (final_sequence, 0, 1)); - gcc_assert (!prev_real_insn (insn) - || !arc_hazard (prev_real_insn (insn), prev)); - cfun->machine->force_short_suffix = !want_long; - rtx save_pred = current_insn_predicate; - final_scan_insn (prev, asm_out_file, optimize, 1, NULL); - cfun->machine->force_short_suffix = -1; - prev->set_deleted (); - current_output_insn = insn; - current_insn_predicate = save_pred; - } - else if (want_long) - fputs ("\tnop\n", asm_out_file); - else - { - fputs ("\tnop_s\n", asm_out_file); - cfun->machine->unalign ^= 2; - } - } - return; -} - /* The usual; we set up our machine_function data. */ static struct machine_function * @@ -9337,7 +9326,6 @@ arc_init_machine_status (void) struct machine_function *machine; machine = ggc_cleared_alloc (); machine->fn_type = ARC_FUNCTION_UNKNOWN; - machine->force_short_suffix = -1; return machine; } diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 5610bab694c..2401926f08d 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -162,6 +162,7 @@ VUNSPEC_ARC_CAS VUNSPEC_ARC_SC VUNSPEC_ARC_LL + VUNSPEC_ARC_BLOCKAGE ]) (define_constants @@ -385,13 +386,18 @@ ;; and insn lengths: insns with shimm values cannot be conditionally executed. (define_attr "length" "" (cond - [(eq_attr "iscompact" "true,maybe") + [(eq_attr "iscompact" "true") + (const_int 2) + + (eq_attr "iscompact" "maybe") (cond [(eq_attr "type" "sfunc") (cond [(match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 12)] (const_int 10)) - (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4)] + (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4) + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (1))") + (const_int 4)] (const_int 2)) (eq_attr "iscompact" "true_limm") @@ -4447,8 +4453,16 @@ archs4x, archs4xd, archs4xd_slow" "" "nop%?" [(set_attr "type" "misc") - (set_attr "iscompact" "true") - (set_attr "length" "2")]) + (set_attr "iscompact" "maybe") + (set_attr "length" "*")]) + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] VUNSPEC_ARC_BLOCKAGE)] + "" + "" + [(set_attr "length" "0") + (set_attr "type" "block")] +) ;; Split up troublesome insns for better scheduling. @@ -4993,8 +5007,6 @@ archs4x, archs4xd, archs4xd_slow" { return \"rtie\"; } - if (TARGET_PAD_RETURN) - arc_pad_return (); output_asm_insn (\"j%!%* [%0]%&\", ®); return \"\"; } @@ -5038,8 +5050,6 @@ archs4x, archs4xd, archs4xd_slow" arc_return_address_register (arc_compute_function_type (cfun))); - if (TARGET_PAD_RETURN) - arc_pad_return (); output_asm_insn (\"j%d0%!%# [%1]%&\", xop); /* record the condition in case there is a delay insn. */ arc_ccfsm_record_condition (xop[0], false, insn, 0); diff --git a/gcc/testsuite/gcc.target/arc/pr9001107555.c b/gcc/testsuite/gcc.target/arc/pr9001107555.c new file mode 100644 index 00000000000..134426d33d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/pr9001107555.c @@ -0,0 +1,38 @@ +/* { dg-do assemble } * +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-O3 -w -funroll-loops -mno-sdata -mcpu=arc700" } */ + +typedef a __attribute__((__mode__(__DI__))); +typedef struct c c; +struct b { + int d; + c *e +}; +enum { f }; +typedef struct { + a g; + a h; + int i +} j; +struct c { + int count; + int current +}; +k; +l(struct b *demux, __builtin_va_list args) { + c m = *demux->e; + j *n; + switch (k) + case f: { + a o = __builtin_va_arg(args, a); + m.current = 0; + while (m.current < m.count) { + if (n[m.current].h > o) { + p(demux->d, 4 + 128LL * n[m.current].i); + break; + } + m.current++; + } + return 0; + } +}