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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5ec02c2c157sm52730eaf.44.2024.10.23.13.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 13:59:26 -0700 (PDT) From: David Lechner Date: Wed, 23 Oct 2024 15:59:11 -0500 Subject: [PATCH RFC v4 04/15] spi: dt-bindings: add trigger-source.yaml Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241023-dlech-mainline-spi-engine-offload-2-v4-4-f8125b99f5a1@baylibre.com> References: <20241023-dlech-mainline-spi-engine-offload-2-v4-0-f8125b99f5a1@baylibre.com> In-Reply-To: <20241023-dlech-mainline-spi-engine-offload-2-v4-0-f8125b99f5a1@baylibre.com> To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= , =?utf-8?q?Uwe_Kleine-K=C3=B6?= =?utf-8?q?nig?= Cc: Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, David Lechner X-Mailer: b4 0.14.1 Add a new binding for SPI offload trigger sources. Signed-off-by: David Lechner --- v4 changes: new patch in v4. FWIW, this is essentially identical to the leds trigger-source binding. --- .../devicetree/bindings/spi/trigger-source.yaml | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/trigger-source.yaml b/Documentation/devicetree/bindings/spi/trigger-source.yaml new file mode 100644 index 000000000000..d64367726af2 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/trigger-source.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/trigger-source.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trigger source providers for SPI offloads + +maintainers: + - David Lechner + +description: + Each trigger source provider should be represented by a device tree node. It + may be e.g. a SPI peripheral chip or a clock source. + +properties: + '#trigger-source-cells': + description: + Number of cells in a source trigger. Typically 0 for nodes of simple + trigger sources. For nodes with more than one output signal, the first + cell be used to specify which output signal to use. If the same signal is + available on more than one pin, the second cell can be used to specify + which pin to use. + enum: [ 0, 1, 2 ] + +additionalProperties: true + +... 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Signed-off-by: David Lechner --- v4 changes: new patch in v4 --- .../devicetree/bindings/spi/trigger-pwm.yaml | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/trigger-pwm.yaml b/Documentation/devicetree/bindings/spi/trigger-pwm.yaml new file mode 100644 index 000000000000..987638aa4732 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/trigger-pwm.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/trigger-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic SPI offload trigger using PWM + +description: Remaps a PWM channel as a trigger source. + +maintainers: + - David Lechner + +$ref: /schemas/spi/trigger-source.yaml# + +properties: + compatible: + const: trigger-pwm + + '#trigger-source-cells': + const: 0 + + pwms: + maxItems: 1 + +required: + - compatible + - '#trigger-source-cells' + - pwms + +additionalProperties: false + +examples: + - | + trigger { + compatible = "trigger-pwm"; + #trigger-source-cells = <0>; + pwms = <&pwm 0 1000000 0>; + }; From patchwork Wed Oct 23 20:59:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 2001293 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=FDB43yQ4; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-114913-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XYhKp71KCz1xw0 for ; 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This includes a connection to a DMA controller for streaming RX data and a trigger input for starting execution of the SPI message programmed in the offload. Signed-off-by: David Lechner --- v4 changes: * Dropped #spi-offload-cells property. * Changed subject line. v3 changes: * Added #spi-offload-cells property. * Added properties for triggers and RX data stream connected to DMA. v2 changes: This is basically a new patch. It partially replaces "dt-bindings: iio: offload: add binding for PWM/DMA triggered buffer". The controller no longer has an offloads object node and the spi-offloads property is now a standard SPI peripheral property. --- .../bindings/spi/adi,axi-spi-engine.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index d48faa42d025..5281b4871209 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -41,6 +41,24 @@ properties: - const: s_axi_aclk - const: spi_clk + trigger-sources: + description: + An array of trigger source phandles for offload instances. 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5ec02c2c157sm52730eaf.44.2024.10.23.13.59.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 13:59:54 -0700 (PDT) From: David Lechner Date: Wed, 23 Oct 2024 15:59:21 -0500 Subject: [PATCH RFC v4 14/15] dt-bindings: iio: adc: adi,ad4695: add SPI offload properties Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241023-dlech-mainline-spi-engine-offload-2-v4-14-f8125b99f5a1@baylibre.com> References: <20241023-dlech-mainline-spi-engine-offload-2-v4-0-f8125b99f5a1@baylibre.com> In-Reply-To: <20241023-dlech-mainline-spi-engine-offload-2-v4-0-f8125b99f5a1@baylibre.com> To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= , =?utf-8?q?Uwe_Kleine-K=C3=B6?= =?utf-8?q?nig?= Cc: Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, David Lechner X-Mailer: b4 0.14.1 Add a pwms property to the adi,ad4695 binding to specify an optional PWM output connected to the CNV pin on the ADC. Also add #trigger-source-cells property to allow the BUSY output to be used as a SPI offload trigger source to indicate when a sample is ready to be read. The $ref for spi-peripheral-props.yaml is moved to keep similar $refs grouped together. Signed-off-by: David Lechner --- v4 changes: new patch in v4 For offload support, this doesn't actually tell the whole story. For some use cases, it would be perfectly reasonable to have a PWM directly connected to the CNV pin, which is why I have made the bindings like this. However, in order to work with the the AXI SPI Engine SPI offload and allow for non-cyclic DMA transfers, the actual signal that is being connected to the CNV pin is: CNV = (PWM_OUT && !DMA_FULL) || CNV_GPIO_OUT RFC: Is this binding sufficient for this use case? Or should we consider something that describes it more accurately? The gory details (mostly of interest for those reviewing the driver patch that uses this binding): * The PWM output has to be disabled in hardware by connecting it to an AND gate where the 2nd input comes from the DMA controller. This is necessary to ensure that we can only trigger conversions as long as there is room in the DMA buffer to receive them. If we continue to trigger conversions when the DMA is full, then the advanced sequencer in the ADC chip keeps advancing and we will end up starting the next batch of conversions with a random channel when DMA is no longer full. * To get out of conversion mode, we also have to toggle the CNV pin manually one time. If it wasn't for the DMA mask on the PWM output, we could just use 0% and 100% duty cycle to toggle the CNV pin, but since the PWM output is masked by the DMA, we have to use a GPIO to toggle the CNV pin. The GPIO signal is connected to an input of an OR gate along with the output of the AND gate mentioned above. --- Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml index 310f046e139f..0d767d8b867a 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml @@ -18,8 +18,6 @@ description: | * https://www.analog.com/en/products/ad4697.html * https://www.analog.com/en/products/ad4698.html -$ref: /schemas/spi/spi-peripheral-props.yaml# - properties: compatible: enum: @@ -84,6 +82,9 @@ properties: description: The Reset Input (RESET). Should be configured GPIO_ACTIVE_LOW. maxItems: 1 + pwms: + description: PWM signal connected to the CNV pin. + interrupts: minItems: 1 items: @@ -106,6 +107,12 @@ properties: The first cell is the GPn number: 0 to 3. The second cell takes standard GPIO flags. + '#trigger-source-cells': + description: | + First cell indicates the output signal: 0 = BUSY, 1 = ALERT. + Second cell indicates which GPn pin is used: 0 to 3. + const: 2 + "#address-cells": const: 1 @@ -165,6 +172,8 @@ required: - vio-supply allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - $ref: /schemas/spi/trigger-source.yaml# - oneOf: - required: - ldo-in-supply