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Violators will be prosecuted; Thu, 3 May 2018 11:17:09 -0600 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w43HH6DQ11075964; Thu, 3 May 2018 10:17:08 -0700 Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D1FA0BE040; Thu, 3 May 2018 11:17:08 -0600 (MDT) Received: from ibm-toto.the-meissners.org (unknown [9.32.77.218]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS id 52147BE03A; Thu, 3 May 2018 11:17:08 -0600 (MDT) Date: Thu, 3 May 2018 13:17:03 -0400 From: Michael Meissner To: GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH] PowerPC address support clean, patch 1 of 4 Mail-Followup-To: Michael Meissner , GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 18050317-0016-0000-0000-000008A65392 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008963; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000258; SDB=6.01026980; UDB=6.00524556; IPR=6.00806113; MB=3.00020910; MTD=3.00000008; XFM=3.00000015; UTC=2018-05-03 17:17:10 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18050317-0017-0000-0000-00003E8914F7 Message-Id: <20180503171703.GA4233@ibm-toto.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-05-03_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1805030149 These patches were previously posted in March as a RFC, and I would like to check them into the trunk. These patches make the mode_supports* functions use similar names for the functions that return if a mode supports D-FORM, DS-FORM, and/or DQ-FORM instructions, and add the ability to ask whether a particular reload register class supports a particular D*-form instruction. This is patch #1 of 4 and it renames the mode_supports_vsx_dform_quad function to be mode_supports_dq_form. I have done a bootstrap and make check comparison on a little endian power8 system, and there were no regressions. Can I check it in? 2018-05-03 Michael Meissner * config/rs6000/rs6000.c (mode_supports_dq_form): Rename mode_supports_vsx_dform_quad to mode_supports_dq_form. (mode_supports_vsx_dform_quad): Likewise. (quad_address_p): Likewise. (reg_offset_addressing_ok_p): Likewise. (offsettable_ok_by_alignment): Likewise. (rs6000_legitimate_offset_address_p): Likewise. (legitimate_lo_sum_address_p): Likewise. (rs6000_legitimize_address): Likewise. (rs6000_legitimize_reload_address): Likewise. (rs6000_secondary_reload_inner): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_output_move_128bit): Likewise. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 259864) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -649,7 +649,7 @@ mode_supports_vmx_dform (machine_mode mo is more limited than normal d-form addressing in that the offset must be aligned on a 16-byte boundary. */ static inline bool -mode_supports_vsx_dform_quad (machine_mode mode) +mode_supports_dq_form (machine_mode mode) { return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET) != 0); @@ -7922,7 +7922,7 @@ quad_address_p (rtx addr, machine_mode m if (legitimate_indirect_address_p (addr, strict)) return true; - if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode)) + if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode)) return false; if (GET_CODE (addr) != PLUS) @@ -8104,7 +8104,7 @@ reg_offset_addressing_ok_p (machine_mode IEEE 128-bit floating point that is passed in a single vector register. */ if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) - return mode_supports_vsx_dform_quad (mode); + return mode_supports_dq_form (mode); break; case E_SDmode: @@ -8164,7 +8164,7 @@ offsettable_ok_by_alignment (rtx op, HOS /* ISA 3.0 vector d-form addressing is restricted, don't allow SYMBOL_REF. */ - if (mode_supports_vsx_dform_quad (mode)) + if (mode_supports_dq_form (mode)) return false; dsize = GET_MODE_SIZE (mode); @@ -8335,7 +8335,7 @@ rs6000_legitimate_offset_address_p (mach return false; if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) return false; - if (mode_supports_vsx_dform_quad (mode)) + if (mode_supports_dq_form (mode)) return quad_address_p (x, mode, strict); if (!reg_offset_addressing_ok_p (mode)) return virtual_stack_registers_memory_p (x); @@ -8448,7 +8448,7 @@ legitimate_lo_sum_address_p (machine_mod if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) return false; /* quad word addresses are restricted, and we can't use LO_SUM. */ - if (mode_supports_vsx_dform_quad (mode)) + if (mode_supports_dq_form (mode)) return false; x = XEXP (x, 1); @@ -8513,7 +8513,7 @@ rs6000_legitimize_address (rtx x, rtx ol unsigned int extra; if (!reg_offset_addressing_ok_p (mode) - || mode_supports_vsx_dform_quad (mode)) + || mode_supports_dq_form (mode)) { if (virtual_stack_registers_memory_p (x)) return x; @@ -9229,7 +9229,7 @@ rs6000_legitimize_reload_address (rtx x, int ind_levels ATTRIBUTE_UNUSED, int *win) { bool reg_offset_p = reg_offset_addressing_ok_p (mode); - bool quad_offset_p = mode_supports_vsx_dform_quad (mode); + bool quad_offset_p = mode_supports_dq_form (mode); /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */ @@ -9515,7 +9515,7 @@ static bool rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) { bool reg_offset_p = reg_offset_addressing_ok_p (mode); - bool quad_offset_p = mode_supports_vsx_dform_quad (mode); + bool quad_offset_p = mode_supports_dq_form (mode); /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ if (VECTOR_MEM_ALTIVEC_P (mode) @@ -19743,7 +19743,7 @@ rs6000_secondary_reload_inner (rtx reg, } } - else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1)) + else if (mode_supports_dq_form (mode) && CONST_INT_P (op1)) { if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0) || !quad_address_p (addr, mode, false)) @@ -19784,7 +19784,7 @@ rs6000_secondary_reload_inner (rtx reg, } /* Quad offsets are restricted and can't handle normal addresses. */ - else if (mode_supports_vsx_dform_quad (mode)) + else if (mode_supports_dq_form (mode)) { emit_insn (gen_rtx_SET (scratch, addr)); new_addr = scratch; @@ -19979,7 +19979,7 @@ rs6000_preferred_reload_class (rtx x, en /* D-form addressing can easily reload the value. */ if (mode_supports_vmx_dform (mode) - || mode_supports_vsx_dform_quad (mode)) + || mode_supports_dq_form (mode)) return rclass; /* If this is a scalar floating point value and we don't have D-form @@ -20382,7 +20382,7 @@ rs6000_output_move_128bit (rtx operands[ else if (TARGET_VSX && dest_vsx_p) { - if (mode_supports_vsx_dform_quad (mode) + if (mode_supports_dq_form (mode) && quad_address_p (XEXP (src, 0), mode, true)) return "lxv %x0,%1"; @@ -20420,7 +20420,7 @@ rs6000_output_move_128bit (rtx operands[ else if (TARGET_VSX && src_vsx_p) { - if (mode_supports_vsx_dform_quad (mode) + if (mode_supports_dq_form (mode) && quad_address_p (XEXP (dest, 0), mode, true)) return "stxv %x1,%0";