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Thu, 18 Jul 2024 13:50:02 -0700 (PDT) MIME-Version: 1.0 References: <20240718072305.3609-1-MayShao-oc@zhaoxin.com> In-Reply-To: <20240718072305.3609-1-MayShao-oc@zhaoxin.com> From: Uros Bizjak Date: Thu, 18 Jul 2024 22:49:50 +0200 Message-ID: Subject: [committed] libatomic: Handle AVX+CX16 ZHAOXIN like intel for 16b atomic [PR104688] To: MayShao-oc Cc: "gcc-patches@gcc.gnu.org" , Jakub Jelinek , "Louis Qi(BJ-RD)" , "Hawk Wang(BJ-RD)" , "Tim Hu(WH-RD)" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: mayshao PR target/104688 libatomic/ChangeLog: * config/x86/init.c (__libat_feat1_init): Don't clear bit_AVX on ZHAOXIN CPUs. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/libatomic/config/x86/init.c b/libatomic/config/x86/init.c index 26168d46832..c6ce997a5af 100644 --- a/libatomic/config/x86/init.c +++ b/libatomic/config/x86/init.c @@ -41,11 +41,15 @@ __libat_feat1_init (void) { /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address is atomic, and AMD is going to do something similar soon. - We don't have a guarantee from vendors of other CPUs with AVX, - like Zhaoxin and VIA. */ + Zhaoxin also guarantees this. We don't have a guarantee + from vendors of other CPUs with AVX, like VIA. */ + unsigned int family = (eax >> 8) & 0x0f; unsigned int ecx2; __cpuid (0, eax, ebx, ecx2, edx); - if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx) + if (ecx2 != signature_INTEL_ecx + && ecx2 != signature_AMD_ecx + && !(ecx2 == signature_CENTAUR_ecx && family > 6) + && ecx2 != signature_SHANGHAI_ecx) FEAT1_REGISTER &= ~bit_AVX; } #endif