From patchwork Fri Apr 27 22:59:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Terpstra X-Patchwork-Id: 905986 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="fpS0hvmC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XqDw0gMLz9s0w for ; Sat, 28 Apr 2018 09:01:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932453AbeD0XBf (ORCPT ); Fri, 27 Apr 2018 19:01:35 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:42222 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932977AbeD0XA2 (ORCPT ); Fri, 27 Apr 2018 19:00:28 -0400 Received: by mail-pf0-f196.google.com with SMTP id a11so2485042pfn.9 for ; Fri, 27 Apr 2018 16:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lgR2ZSJVVEYIepwhL6PwbmSjFII7BXtaK3acK/tsZtQ=; b=fpS0hvmCwXHJgeyJPvCIk63BfV5SOiRFuqpXfpBqo1LCFROuNx60FmB4RNI6xiREKP ZPoqXGqwzywsmHanSPJudhEKfRnKxHYqVLK2G5od8+zsAeFbPcyXJ6CK2RfMqU3bH4Of P/IZVOLb+Xby0K91Z5gDmulOZC9HfQlV6/3J+z5v+GwAL7s+H13aNvR4M310hgnVYm3K EPI8qxIjQ1tMB8tpYWUQu9QNFiCs+HTySy7oVDpnEdov7V0Z27LP9o5rX9oqbnohKA8O bKkzdubCV+6oXuhTBj1814zTx9ADu64dKOuKinyLMH+HKAQ+PAdstxnwBxBMNsd7FnVd Drhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lgR2ZSJVVEYIepwhL6PwbmSjFII7BXtaK3acK/tsZtQ=; b=c5xtsoEc+eZxaxlSE3M4H6AnNfUXBbdFcwBsghmfUaccI5ox/HSVmdoBY2oz97+bXu QbTkhbkgoXOApB9HPbk0eSiUYn2PDQxQ1o6hf4sKo7JuZ9Cg+ke9SmmFq0PaRFv3ZzVs V/PKDOvI6skaq0fsyWoAIAhQ7AFme0aXjoi+VgSPZbWS4kkej++LywMBSnm94TW7pMeT 6UUpX6DL5LHXymnQbPSTzeN7t4366fGqdIJ4StG/Mz1sxZPc1ET0cA32H9lr8qWlf/HB dlHOq9JnJoe6EDZTDYNV/omUcw80ttS4Wd963nFJvBg736OFvPpnWCXlqJMMbR2+3/Vx grlA== X-Gm-Message-State: ALQs6tDjQMl5zVhTuTyxGzp1KrvXPrRFY8V7w4f9TVXfQIBk6OLkp9op iEr/V7rbHW1xcgQkS8VMfEWrCw== X-Google-Smtp-Source: AB8JxZoIbxtLXKpYK8DXKLzUtUR1E35berOvXOi/G/3BPWS/rkFQFCU/vLz2YKsPpnhXmHyzpJL4Tw== X-Received: by 10.98.211.82 with SMTP id q79mr3806515pfg.45.1524870028376; Fri, 27 Apr 2018 16:00:28 -0700 (PDT) Received: from gamma03.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id s9sm2462410pfa.141.2018.04.27.16.00.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Apr 2018 16:00:27 -0700 (PDT) From: "Wesley W. Terpstra" To: Thierry Reding , Rob Herring , Mark Rutland , =?utf-8?q?Andreas_F=C3=A4?= =?utf-8?q?rber?= , =?utf-8?q?Noralf_Tr=C3=B8nnes?= , David Lechner , Alexandre Belloni , SZ Lin , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "Wesley W. Terpstra" Subject: [PATCH 1/3] dt-bindings: added new pwm-sifive driver documentation Date: Fri, 27 Apr 2018 15:59:56 -0700 Message-Id: <1524869998-2805-2-git-send-email-wesley@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524869998-2805-1-git-send-email-wesley@sifive.com> References: <1524869998-2805-1-git-send-email-wesley@sifive.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Document new PWM device tree bindings for SiFive SoCs. Signed-off-by: Wesley W. Terpstra --- .../devicetree/bindings/pwm/pwm-sifive.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt new file mode 100644 index 0000000..7cea20d --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt @@ -0,0 +1,28 @@ +SiFive PWM controller + +Unlike most other PWM controllers, the SiFive PWM controller currently only +supports one period for all channels in the PWM. This is set globally in DTS. +The period also has significant restrictions on the values it can achieve, +which the driver rounds to the nearest achievable frequency. + +Required properties: +- compatible: should be "sifive,pwm0" +- reg: physical base address and length of the controller's registers +- clocks: The frequency the controller runs at +- #pwm-cells: Should be 2. + The first cell is the PWM channel number + The second cell is the PWM polarity +- sifive,approx-period: the driver will get as close to this period as it can +- interrupts: one interrupt per PWM channel (currently unused in the driver) + +Examples: + +pwm: pwm@10020000 { + compatible = "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + clocks = <&tlclk>; + interrupt-parent = <&plic>; + interrupts = <42 43 44 45>; + #pwm-cells = <2>; + sifive,approx-period = <1000000>; +}; From patchwork Fri Apr 27 22:59:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wesley Terpstra X-Patchwork-Id: 905981 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="cuxImgdK"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XqDK4G6Kz9s0p for ; Sat, 28 Apr 2018 09:01:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933048AbeD0XAc (ORCPT ); Fri, 27 Apr 2018 19:00:32 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:36464 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933010AbeD0XAa (ORCPT ); Fri, 27 Apr 2018 19:00:30 -0400 Received: by mail-pg0-f66.google.com with SMTP id i6-v6so2555322pgv.3 for ; Fri, 27 Apr 2018 16:00:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GsImA2yJHYRLzy4e/goy9KjS5rIddULgBKSO8aaaFbE=; b=cuxImgdKcbAlj+6OL3VlytYbEB+rxdqmaTWiAQWjersbhtv3uuq6D0dRIyP7j5Rkwo fUSMb4ogGdQ/NTpC3kdL7/me105/GtBH32TxVwQsaGSomews8kYIdVKFg22rwQrD3/Qe L4lWvHXTYka7yM3Bao6+8Pk8GTxQJKMln9ksBrMaVc2dWosCyZwifzRx1fcgBrBCzEeg jTo67p3l3VT/fKLbPAaRD1jzjIqI/Z+QTIPJQbmOrnteMypw3XWUNzxL8ogwm1KrRILo W7NOLAy86gQ1DO4H+d1LHL9lzQ+fZsmzPXpyowhGUhY0l7RzrYpAgfGx7ccs7BAgRGG5 jeYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GsImA2yJHYRLzy4e/goy9KjS5rIddULgBKSO8aaaFbE=; b=CYAJh5DQ50Brr+FCYwQkiKNaiw56vYgkSY11YCn686wCL4FNnKk1TKKbTxJ87ItsTW 9tKSO+qTmeE3AR5vQzzocYm9Elvrq9W+YBCjMlGnjclLNLV9gFS9h3dRlOSPynShuI17 FX7LtvJwEZJNZGAi05iud3CcWuGtITxNCGaSfNigyhO93tM4GOBLBMXH2AiJlg+FNrEa boRNMoaLo4eLpAtW2pFIln7W6bDKneKaviGU9gshGxc2NiZF6NotM1nI4u2vGV7CSarX GiCjvWRKXLe9KszFBucR0AgzT3CpvHUi3pz7aKXSySMW0YIERI26hJWfnVbKNfN1pvEP xbCQ== X-Gm-Message-State: ALQs6tDOy++4cZ+lTgP+ysFjFSUgmXbxLb/dC6ybwvm5uq3l78Qq8ZBR joUtd4Yb9/PM4d4ZM4/d+2Z+vA== X-Google-Smtp-Source: AB8JxZrG13kaz9IBtTBejq+opoCNdmb69M+Vg/Ve0od5S1xuERR1X/p79CMKQScw4ZjaSP3WsQipmw== X-Received: by 2002:a17:902:7d92:: with SMTP id a18-v6mr3941499plm.331.1524870029398; Fri, 27 Apr 2018 16:00:29 -0700 (PDT) Received: from gamma03.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id s9sm2462410pfa.141.2018.04.27.16.00.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Apr 2018 16:00:28 -0700 (PDT) From: "Wesley W. Terpstra" To: Thierry Reding , Rob Herring , Mark Rutland , =?utf-8?q?Andreas_F=C3=A4?= =?utf-8?q?rber?= , =?utf-8?q?Noralf_Tr=C3=B8nnes?= , David Lechner , Alexandre Belloni , SZ Lin , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "Wesley W. Terpstra" Subject: [PATCH 2/3] dt-bindings: Add "sifive" vendor prefix Date: Fri, 27 Apr 2018 15:59:57 -0700 Message-Id: <1524869998-2805-3-git-send-email-wesley@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524869998-2805-1-git-send-email-wesley@sifive.com> References: <1524869998-2805-1-git-send-email-wesley@sifive.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This adds a vendor prefix "sifive" for SiFive, Inc. We make chips. Signed-off-by: Wesley W. Terpstra Reviewed-by: Andreas Färber --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index ae850d6..c98faf7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -315,6 +315,7 @@ sgx SGX Sensortech sharp Sharp Corporation shimafuji Shimafuji Electric, Inc. si-en Si-En Technology Ltd. +sifive SiFive, Inc. sigma Sigma Designs, Inc. sii Seiko Instruments, Inc. sil Silicon Image From patchwork Fri Apr 27 22:59:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Terpstra X-Patchwork-Id: 905983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="NuvxM62x"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XqDk6bmvz9s0t for ; Sat, 28 Apr 2018 09:01:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932891AbeD0XBL (ORCPT ); Fri, 27 Apr 2018 19:01:11 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:37620 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933031AbeD0XAb (ORCPT ); Fri, 27 Apr 2018 19:00:31 -0400 Received: by mail-pf0-f195.google.com with SMTP id p6so2489605pfn.4 for ; Fri, 27 Apr 2018 16:00:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FE9uIAui6rD4DKYbH5vzfEyTJjg/wH6gcuE/FmW/Lfw=; b=NuvxM62xQHaUfMm8WWdG6dvj0uFvUB6q3YmbtL+U1gAFa+2mLNLcv4L12WQZhCjjhh Dak5qyV+KxSVYkC7MHqt/fcwhJPvGp61VI5Fgw4k+0N+wUsvShHAB1nQapv5TxhRhvz5 IFKp9g7pJfW0ZV09qNwD/4FZe2M6SXnLHUgte1TpsFJXwy3G/o0Uz0C2s/+GL+r6YgPx P+MBAh562KnCRV1ByGYsKmMhV9vLZyjzaQ8Z26UhNTVQYipwiR/k9aXcSzUFu8vogWL5 tyfdLE8zNd/Rc/2Uhcev1JMoWapbwujgfdnA+AyV87tdDDBBFdd8L+rS/gbsxNgwXt61 EfmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FE9uIAui6rD4DKYbH5vzfEyTJjg/wH6gcuE/FmW/Lfw=; b=MtVaILT+w0bzYWi7IIkYNbLec4J6PsHFX9U/+PjXLeZSJKS2fyupu1+70tLRshNrlr J+VmME3RqH27mlhbj3T9FLR3PTQH3L2CGStvT/5HVemEzM5sTJqxePZdXBUIO0feXMdw DGsBIParMCqlou7G4lpBIhHTGkPR+Wto7YaXGrTfsctSnhqpb+pPYWnOqpkJ0ZujabTs dNhoNuPxMNsrk4M8ye7l2Y5+ubLR3msNAdMfgsSkt38VINMYBSgQdmE+BX7o4jZzRmyj QO/OxsVudafAJl7l/+U8d1FaLz4U/BLDRoKncUpT0MgsK+a2ocmrbEqUgEMLBj4zLx8a e5Lg== X-Gm-Message-State: ALQs6tBeIx8mC2sxv4oo0aOZTaJQAxSuueauCukLyOo0MaMG1gBLR8s1 ahzrksrMm37OCidbuLcWm/tcNg== X-Google-Smtp-Source: AB8JxZomq6P6BclZGlz/gExY6lzhCiJdBlF60nvUmRlRtQDF0V0TluQKoBmrj5MU/z3BVUwJ4mELzg== X-Received: by 2002:a17:902:206:: with SMTP id 6-v6mr3918909plc.376.1524870030499; Fri, 27 Apr 2018 16:00:30 -0700 (PDT) Received: from gamma03.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id s9sm2462410pfa.141.2018.04.27.16.00.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Apr 2018 16:00:30 -0700 (PDT) From: "Wesley W. Terpstra" To: Thierry Reding , Rob Herring , Mark Rutland , =?utf-8?q?Andreas_F=C3=A4?= =?utf-8?q?rber?= , =?utf-8?q?Noralf_Tr=C3=B8nnes?= , David Lechner , Alexandre Belloni , SZ Lin , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "Wesley W. Terpstra" , "Wesley W . Terpstra" Subject: [PATCH 3/3] pwm-sifive: add a driver for SiFive SoC PWM Date: Fri, 27 Apr 2018 15:59:58 -0700 Message-Id: <1524869998-2805-4-git-send-email-wesley@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524869998-2805-1-git-send-email-wesley@sifive.com> References: <1524869998-2805-1-git-send-email-wesley@sifive.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org SiFive SoCs can contain one or more PWM IP blocks. This adds a driver for them. Tested on the HiFive Unleashed. Signed-off-by: Wesley W. Terpstra --- drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sifive.c | 259 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 271 insertions(+) create mode 100644 drivers/pwm/pwm-sifive.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 763ee50..49e9824 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -387,6 +387,17 @@ config PWM_SAMSUNG To compile this driver as a module, choose M here: the module will be called pwm-samsung. +config PWM_SIFIVE + tristate "SiFive PWM support" + depends on OF + depends on COMMON_CLK + help + Generic PWM framework driver for SiFive SoCs, such as those + found on the HiFive Unleashed series boards. + + To compile this driver as a module, choose M here: the module + will be called pwm-sifive. + config PWM_SPEAR tristate "STMicroelectronics SPEAr PWM support" depends on PLAT_SPEAR diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0258a74..17c5eb9 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o +obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_STI) += pwm-sti.o obj-$(CONFIG_PWM_STM32) += pwm-stm32.o diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c new file mode 100644 index 0000000..587d4d4 --- /dev/null +++ b/drivers/pwm/pwm-sifive.c @@ -0,0 +1,259 @@ +/* + * SiFive PWM driver + * + * Copyright (C) 2018 SiFive, Inc + * + * Author: Wesley W. Terpstra + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2, as published by + * the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_PWM 4 + +/* Register offsets */ +#define REG_PWMCFG 0x0 +#define REG_PWMCOUNT 0x8 +#define REG_PWMS 0x10 +#define REG_PWMCMP0 0x20 + +/* PWMCFG fields */ +#define BIT_PWM_SCALE 0 +#define BIT_PWM_STICKY 8 +#define BIT_PWM_ZERO_ZMP 9 +#define BIT_PWM_DEGLITCH 10 +#define BIT_PWM_EN_ALWAYS 12 +#define BIT_PWM_EN_ONCE 13 +#define BIT_PWM0_CENTER 16 +#define BIT_PWM0_GANG 24 +#define BIT_PWM0_IP 28 + +#define SIZE_PWMCMP 4 +#define MASK_PWM_SCALE 0xf + +struct sifive_pwm_device { + struct pwm_chip chip; + struct notifier_block notifier; + struct clk *clk; + void __iomem *regs; + int irq; + unsigned int approx_period; + unsigned int real_period; +}; + +static inline struct sifive_pwm_device *chip_to_sifive(struct pwm_chip *c) +{ + return container_of(c, struct sifive_pwm_device, chip); +} + +static inline struct sifive_pwm_device *notifier_to_sifive(struct notifier_block *nb) +{ + return container_of(nb, struct sifive_pwm_device, notifier); +} + +static int sifive_pwm_apply(struct pwm_chip *chip, + struct pwm_device *dev, + struct pwm_state *state) +{ + struct sifive_pwm_device *pwm = chip_to_sifive(chip); + unsigned int duty_cycle; + u32 frac; + + duty_cycle = state->duty_cycle; + if (!state->enabled) + duty_cycle = 0; + if (state->polarity == PWM_POLARITY_NORMAL) + duty_cycle = state->period - duty_cycle; + + frac = ((u64)duty_cycle << 16) / state->period; + frac = min(frac, 0xFFFFU); + + iowrite32(frac, pwm->regs + REG_PWMCMP0 + (dev->hwpwm * SIZE_PWMCMP)); + + if (state->enabled) { + state->period = pwm->real_period; + state->duty_cycle = ((u64)frac * pwm->real_period) >> 16; + if (state->polarity == PWM_POLARITY_NORMAL) + state->duty_cycle = state->period - state->duty_cycle; + } + + return 0; +} + +static void sifive_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *dev, + struct pwm_state *state) +{ + struct sifive_pwm_device *pwm = chip_to_sifive(chip); + unsigned long duty; + + duty = ioread32(pwm->regs + REG_PWMCMP0 + (dev->hwpwm * SIZE_PWMCMP)); + + state->period = pwm->real_period; + state->duty_cycle = ((u64)duty * pwm->real_period) >> 16; + state->polarity = PWM_POLARITY_INVERSED; + state->enabled = duty > 0; +} + +static const struct pwm_ops sifive_pwm_ops = { + .get_state = sifive_pwm_get_state, + .apply = sifive_pwm_apply, + .owner = THIS_MODULE, +}; + +static struct pwm_device *sifive_pwm_xlate(struct pwm_chip *chip, + const struct of_phandle_args *args) +{ + struct sifive_pwm_device *pwm = chip_to_sifive(chip); + struct pwm_device *dev; + + if (args->args[0] >= chip->npwm) + return ERR_PTR(-EINVAL); + + dev = pwm_request_from_chip(chip, args->args[0], NULL); + if (IS_ERR(dev)) + return dev; + + /* The period cannot be changed on a per-PWM basis */ + dev->args.period = pwm->real_period; + dev->args.polarity = PWM_POLARITY_NORMAL; + if (args->args[1] & PWM_POLARITY_INVERTED) + dev->args.polarity = PWM_POLARITY_INVERSED; + + return dev; +} + +static void sifive_pwm_update_clock(struct sifive_pwm_device *pwm, + unsigned long rate) +{ + /* (1 << (16+scale)) * 10^9/rate = real_period */ + unsigned long scalePow = (pwm->approx_period * (u64)rate) / 1000000000; + int scale = ilog2(scalePow) - 16; + + scale = clamp(scale, 0, 0xf); + iowrite32((1 << BIT_PWM_EN_ALWAYS) | (scale << BIT_PWM_SCALE), + pwm->regs + REG_PWMCFG); + + pwm->real_period = (1000000000ULL << (16 + scale)) / rate; +} + +static int sifive_pwm_clock_notifier(struct notifier_block *nb, + unsigned long event, + void *data) +{ + struct clk_notifier_data *ndata = data; + struct sifive_pwm_device *pwm = notifier_to_sifive(nb); + + if (event == POST_RATE_CHANGE) + sifive_pwm_update_clock(pwm, ndata->new_rate); + + return NOTIFY_OK; +} + +static int sifive_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct sifive_pwm_device *pwm; + struct pwm_chip *chip; + struct resource *res; + int ret; + + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + chip = &pwm->chip; + chip->dev = dev; + chip->ops = &sifive_pwm_ops; + chip->of_xlate = sifive_pwm_xlate; + chip->of_pwm_n_cells = 2; + chip->base = -1; + + ret = of_property_read_u32(node, "sifive,npwm", &chip->npwm); + if (ret < 0 || chip->npwm > MAX_PWM) + chip->npwm = MAX_PWM; + + ret = of_property_read_u32(node, "sifive,approx-period", + &pwm->approx_period); + if (ret < 0) { + dev_err(dev, "Unable to read sifive,approx-period from DTS\n"); + return -ENOENT; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pwm->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(pwm->regs)) { + dev_err(dev, "Unable to map IO resources\n"); + return PTR_ERR(pwm->regs); + } + + pwm->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pwm->clk)) { + dev_err(dev, "Unable to find controller clock\n"); + return PTR_ERR(pwm->clk); + } + + pwm->irq = platform_get_irq(pdev, 0); + if (pwm->irq < 0) { + dev_err(dev, "Unable to find interrupt\n"); + return pwm->irq; + } + + /* Watch for changes to underlying clock frequency */ + pwm->notifier.notifier_call = sifive_pwm_clock_notifier; + clk_notifier_register(pwm->clk, &pwm->notifier); + + /* Initialize PWM config */ + sifive_pwm_update_clock(pwm, clk_get_rate(pwm->clk)); + + ret = pwmchip_add(chip); + if (ret < 0) { + dev_err(dev, "cannot register PWM: %d\n", ret); + clk_notifier_unregister(pwm->clk, &pwm->notifier); + return ret; + } + + platform_set_drvdata(pdev, pwm); + dev_info(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm); + + return 0; +} + +static int sifive_pwm_remove(struct platform_device *dev) +{ + struct sifive_pwm_device *pwm = platform_get_drvdata(dev); + struct pwm_chip *chip = &pwm->chip; + + clk_notifier_unregister(pwm->clk, &pwm->notifier); + return pwmchip_remove(chip); +} + +static const struct of_device_id sifive_pwm_of_match[] = { + { .compatible = "sifive,pwm0" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sifive_pwm_of_match); + +static struct platform_driver sifive_pwm_driver = { + .probe = sifive_pwm_probe, + .remove = sifive_pwm_remove, + .driver = { + .name = "pwm-sifivem", + .of_match_table = of_match_ptr(sifive_pwm_of_match), + }, +}; +module_platform_driver(sifive_pwm_driver); + +MODULE_AUTHOR("Wesley W. Terpstra "); +MODULE_DESCRIPTION("SiFive PWM driver"); +MODULE_LICENSE("GPL v2");