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Tue, 11 Jun 2024 10:06:19 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f72d450697sm18363035ad.168.2024.06.11.10.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 10:06:19 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: Edwin Lu , Patrick O'Neill Subject: [Committed 1/3] RISC-V: Add basic Zaamo and Zalrsc support Date: Tue, 11 Jun 2024 10:06:03 -0700 Message-ID: <20240611170605.2376245-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Edwin Lu There is a proposal to split the A extension into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc. * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc. * config/riscv/riscv.opt: Add Zaamo and Zalrsc * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and TARGET_ZALRSC. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-15.c: Adjust expected arch string. * gcc.target/riscv/attribute-16.c: Ditto. * gcc.target/riscv/attribute-17.c: Ditto. * gcc.target/riscv/attribute-18.c: Ditto. * gcc.target/riscv/pr110696.c: Ditto. * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto. * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto. Signed-off-by: Edwin Lu Co-authored-by: Patrick O'Neill --- gcc/common/config/riscv/riscv-common.cc | 11 +++++-- gcc/config/riscv/arch-canonicalize | 1 + gcc/config/riscv/riscv.opt | 6 +++- gcc/config/riscv/sync.md | 30 +++++++++---------- gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- .../gcc.target/riscv/rvv/base/pr114352-1.c | 4 +-- .../gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++--- 11 files changed, 41 insertions(+), 29 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 88204393fde..78dfd6b1470 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] = {"f", "zicsr"}, {"d", "zicsr"}, + {"a", "zaamo"}, + {"a", "zalrsc"}, + {"zdinx", "zfinx"}, {"zfinx", "zicsr"}, {"zdinx", "zicsr"}, @@ -255,6 +258,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, - {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, + {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS}, - {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, + {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, + {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO}, + {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC}, {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index 8f7d040cdeb..6c10d1aa81b 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] # IMPLIED_EXT = { "d" : ["f", "zicsr"], + "a" : ["zaamo", "zalrsc"], "f" : ["zicsr"], "zdinx" : ["zfinx", "zicsr"], "zfinx" : ["zicsr"], diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 78cb1c37e69..b13e993c47a 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -256,7 +256,11 @@ Mask(ZICCRSE) Var(riscv_zi_subext) TargetVariable int riscv_za_subext -Mask(ZAWRS) Var(riscv_za_subext) +Mask(ZAWRS) Var(riscv_za_subext) + +Mask(ZAAMO) Var(riscv_za_subext) + +Mask(ZALRSC) Var(riscv_za_subext) Mask(ZA64RS) Var(riscv_za_subext) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 6f0b5aae08d..c9544176ead 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -93,7 +93,7 @@ (match_operand:GPR 1 "reg_or_0_operand" "rJ")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "TARGET_ATOMIC" + "TARGET_ZAAMO" "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) @@ -107,7 +107,7 @@ (match_operand:GPR 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "TARGET_ATOMIC" + "TARGET_ZAAMO" "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) @@ -125,7 +125,7 @@ (match_operand:SI 5 "register_operand" "rI") ;; not_mask (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I3\t%0, %1\;" @@ -144,7 +144,7 @@ (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op (match_operand:SI 3 "const_int_operand")] ;; model - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_nand to implement a LR/SC version of the @@ -192,7 +192,7 @@ (match_operand:SI 5 "register_operand" "rI") ;; not_mask (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I3\t%0, %1\;" @@ -212,7 +212,7 @@ (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op (match_operand:SI 3 "const_int_operand")] ;; model - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_ to implement a LR/SC version of the @@ -256,7 +256,7 @@ UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] - "TARGET_ATOMIC" + "TARGET_ZAAMO" "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) @@ -266,7 +266,7 @@ (match_operand:SHORT 1 "memory_operand") ;; mem location (match_operand:SHORT 2 "register_operand") ;; value (match_operand:SI 3 "const_int_operand")] ;; model - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -303,7 +303,7 @@ UNSPEC_SYNC_EXCHANGE_SUBWORD)) (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I3\t%0, %1\;" @@ -325,7 +325,7 @@ (match_operand:SI 5 "const_int_operand")] ;; mod_f UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] - "TARGET_ATOMIC" + "TARGET_ZALRSC" { enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); @@ -351,7 +351,7 @@ (match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand" "") ;; mod_s (match_operand:SI 7 "const_int_operand" "")] ;; mod_f - "TARGET_ATOMIC" + "TARGET_ZALRSC" { if (word_mode != mode && operands[3] != const0_rtx) { @@ -394,7 +394,7 @@ (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], operands[3], operands[4], @@ -439,7 +439,7 @@ (match_operand:SI 4 "const_int_operand") ;; mod_s (match_operand:SI 5 "const_int_operand") ;; mod_f (match_scratch:SHORT 6)] - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_cas_strong to implement a LR/SC version of the @@ -497,7 +497,7 @@ (match_operand:SI 5 "register_operand" "rI") ;; mask (match_operand:SI 6 "register_operand" "rI") ;; not_mask (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I4\t%0, %1\;" @@ -516,7 +516,7 @@ [(match_operand:QI 0 "register_operand" "") ;; bool output (match_operand:QI 1 "memory_operand" "+A") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "TARGET_ATOMIC" + "TARGET_ZALRSC" { /* We have no QImode atomics, so use the address LSBs to form a mask, then use an aligned SImode atomic. */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c index 59efeb6ea45..a2e394b6489 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c @@ -3,4 +3,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c index 26f961efb48..d2b18160cb5 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-16.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c @@ -3,4 +3,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c index 0abff3705d9..fc2f488a3ac 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-17.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c @@ -3,4 +3,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c index fddbf15fc3e..eefd602103d 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ int foo() {} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c index a630f04e74f..08682a047e0 100644 --- a/gcc/testsuite/gcc.target/riscv/pr110696.c +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c @@ -4,4 +4,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c index b3f1f20fb79..faeb406498d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) out[i] = a[i] + b[i]; } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c index e7af4223d6a..38815ef5bd0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) out[i] = a[i] + b[i]; } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */ From patchwork Tue Jun 11 17:06:04 2024 Content-Type: text/plain; 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Tue, 11 Jun 2024 10:06:21 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f72d450697sm18363035ad.168.2024.06.11.10.06.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 10:06:20 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: Patrick O'Neill Subject: [Committed 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support Date: Tue, 11 Jun 2024 10:06:04 -0700 Message-ID: <20240611170605.2376245-2-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240611170605.2376245-1-patrick@rivosinc.com> References: <20240611170605.2376245-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A. gcc/ChangeLog: * doc/sourcebuild.texi: Add docs for atomic extension testsuite infra. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A. * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather than A. * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather than A. * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc rather than A. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto. * lib/target-supports.exp: Add testsuite infrastructure support for Zaamo and Zalrsc. Signed-off-by: Patrick O'Neill --- gcc/doc/sourcebuild.texi | 16 ++++++- .../riscv/amo-table-a-6-amo-add-1.c | 2 +- .../riscv/amo-table-a-6-amo-add-2.c | 2 +- .../riscv/amo-table-a-6-amo-add-3.c | 2 +- .../riscv/amo-table-a-6-amo-add-4.c | 2 +- .../riscv/amo-table-a-6-amo-add-5.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-1.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-2.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-3.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-4.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-5.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-6.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-7.c | 2 +- .../riscv/amo-table-a-6-subword-amo-add-1.c | 2 +- .../riscv/amo-table-a-6-subword-amo-add-2.c | 2 +- .../riscv/amo-table-a-6-subword-amo-add-3.c | 2 +- .../riscv/amo-table-a-6-subword-amo-add-4.c | 2 +- .../riscv/amo-table-a-6-subword-amo-add-5.c | 2 +- .../riscv/amo-table-ztso-amo-add-1.c | 2 +- .../riscv/amo-table-ztso-amo-add-2.c | 2 +- .../riscv/amo-table-ztso-amo-add-3.c | 2 +- .../riscv/amo-table-ztso-amo-add-4.c | 2 +- .../riscv/amo-table-ztso-amo-add-5.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-1.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-2.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-3.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-4.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-5.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-6.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-7.c | 2 +- .../riscv/amo-table-ztso-subword-amo-add-1.c | 2 +- .../riscv/amo-table-ztso-subword-amo-add-2.c | 2 +- .../riscv/amo-table-ztso-subword-amo-add-3.c | 2 +- .../riscv/amo-table-ztso-subword-amo-add-4.c | 2 +- .../riscv/amo-table-ztso-subword-amo-add-5.c | 2 +- gcc/testsuite/lib/target-supports.exp | 48 ++++++++++++++++++- 36 files changed, 95 insertions(+), 37 deletions(-) diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index e997dbec333..e37fb85f3b3 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2513,8 +2513,17 @@ Test system has an integer register width of 32 bits. @item rv64 Test system has an integer register width of 64 bits. -@item cv_bi -Test system has support for the CORE-V BI extension. +@item riscv_a +Test target architecture has support for the A extension. + +@item riscv_zaamo +Test target architecture has support for the zaamo extension. + +@item riscv_zlrsc +Test target architecture has support for the zalrsc extension. + +@item riscv_ztso +Test target architecture has support for the ztso extension. @end table @@ -2534,6 +2543,9 @@ Test system has support for the CORE-V ELW extension. @item cv_simd Test system has support for the CORE-V SIMD extension. +@item cv_bi +Test system has support for the CORE-V BI extension. + @end table @subsubsection Other hardware attributes diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c index 8ab1a02b40c..9c2ba39789a 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match Table A.6's recommended mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c index a5a841abdcd..b7682a5bab4 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match Table A.6's recommended mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c index f523821b658..c8776872d91 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match Table A.6's recommended mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c index f1561b52c89..b37c4c3f242 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match Table A.6's recommended mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c index 81f876ee625..8d45ca7a347 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match Table A.6's recommended mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c index dc445f0316a..4917cd6bd2b 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c index 7e8ab7bb5ef..121936507e3 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c index 4cb6c422213..649c7d2b1fe 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c index da81c34b92c..5f7fdeb1b21 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c index bb16ccc754c..f4bd7d6d842 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c index 0f3f0b49d95..154764425ae 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* Mixed mappings need to be unioned. */ /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c index d51de56cc78..16712540919 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c index ca8aa715bed..4174fdee352 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c index e64759a54ae..4c06c90b558 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c index 9d3f69264fa..7e791c901b6 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c index ba32ed59c2f..76f3be27110 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c index f9be8c5e628..8dbfa9c4fc8 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c index a9edc33ff39..82169390925 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match the Ztso suggested mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-add-options riscv_ztso } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c index ad843402bcc..a238c6f4403 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings the Ztso suggested mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-add-options riscv_ztso } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c index bdae5bb83a6..c97bf467c63 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match the Ztso suggested mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-add-options riscv_ztso } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c index 815a72f1e56..14e632ba2f2 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match the Ztso suggested mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-add-options riscv_ztso } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c index eda6f01096e..74d8df99ddc 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Verify that atomic op mappings match the Ztso suggested mapping. */ /* { dg-options "-O3" } */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zaamo } */ /* { dg-add-options riscv_ztso } */ /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c index b6315c45e85..46a9f0c918a 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c index e487184f6cf..20e325f2e7c 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c index e9c925f0923..0a443b461f3 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c index 6b454559633..35e01cdc8be 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c index 02c9f0ada77..cd884931bdf 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c index 75abd5d3dfb..7da3b1dce48 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c index 33928c0eac4..53f6e6ace0b 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that compare exchange mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c index 2a40d6b1376..5c0a8b8f6e9 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c index c79380f2611..551078186ec 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c index d1a94eccfa8..5f0f7870721 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c index 3d65bc2f64a..24f4f02dcea 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c index 10354387a13..405e498fb40 100644 --- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ -/* { dg-add-options riscv_a } */ +/* { dg-add-options riscv_zalrsc } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 5c0a3dade22..e862a893244 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1889,6 +1889,28 @@ proc check_effective_target_riscv_a { } { }] } +# Return 1 if the target arch supports the atomic LRSC extension, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_zalrsc { } { + return [check_no_compiler_messages riscv_ext_zalrsc assembly { + #ifndef __riscv_zalrsc + #error "Not __riscv_zalrsc" + #endif + }] +} + +# Return 1 if the target arch supports the atomic AMO extension, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_zaamo { } { + return [check_no_compiler_messages riscv_ext_zaamo assembly { + #ifndef __riscv_zaamo + #error "Not __riscv_zaamo" + #endif + }] +} + # Return 1 if the target arch supports the double precision floating point # extension, 0 otherwise. Cache the result. @@ -2107,7 +2129,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { proc riscv_get_arch { } { set gcc_march "" # ??? do we neeed to add more extensions to the list below? - foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } { + foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc } { if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { #ifndef DEF #error "Not DEF" @@ -2166,6 +2188,30 @@ proc add_options_for_riscv_v { flags } { return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]" } +proc add_options_for_riscv_zaamo { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ] + return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ] + } + if { [check_effective_target_riscv_zaamo] } { + return "$flags" + } + return "$flags -march=[riscv_get_arch]_zaamo" +} + +proc add_options_for_riscv_zalrsc { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ] + return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ] + } + if { [check_effective_target_riscv_zalrsc] } { + return "$flags" + } + return "$flags -march=[riscv_get_arch]_zalrsc" +} + proc add_options_for_riscv_zfh { flags } { if { [lsearch $flags -march=*] >= 0 } { # If there are multiple -march flags, we have to adjust all of them. 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Tue, 11 Jun 2024 10:06:22 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f72d450697sm18363035ad.168.2024.06.11.10.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 10:06:22 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: Patrick O'Neill Subject: [Committed 3/3] RISC-V: Add Zalrsc amo-op patterns Date: Tue, 11 Jun 2024 10:06:05 -0700 Message-ID: <20240611170605.2376245-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240611170605.2376245-1-patrick@rivosinc.com> References: <20240611170605.2376245-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org All amo patterns can be represented with lrsc sequences. Add these patterns as a fallback when Zaamo is not enabled. gcc/ChangeLog: * config/riscv/sync.md (atomic_): New expand pattern. (amo_atomic_): Rename amo pattern. (atomic_fetch_): New lrsc sequence pattern. (lrsc_atomic_): New expand pattern. (amo_atomic_fetch_): Rename amo pattern. (lrsc_atomic_fetch_): New lrsc sequence pattern. (atomic_exchange): New expand pattern. (amo_atomic_exchange): Rename amo pattern. (lrsc_atomic_exchange): New lrsc sequence pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill --- Changes from v3: Added -mabi=lp64d to testcases. --- gcc/config/riscv/sync.md | 124 +++++++++++++++++- .../riscv/amo-zaamo-preferred-over-zalrsc.c | 17 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-1.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-2.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-3.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-4.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-5.c | 19 +++ 7 files changed, 231 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index c9544176ead..4df9d0b5a5f 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -86,7 +86,24 @@ DONE; }) -(define_insn "atomic_" +;; AMO ops + +(define_expand "atomic_" + [(any_atomic:GPR (match_operand:GPR 0 "memory_operand") ;; mem location + (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op + (match_operand:SI 2 "const_int_operand")] ;; model + "TARGET_ZAAMO || TARGET_ZALRSC" +{ + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_ (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_lrsc_atomic_ (operands[0], operands[1], + operands[2])); + DONE; +}) + +(define_insn "amo_atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR [(any_atomic:GPR (match_dup 0) @@ -98,7 +115,44 @@ [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) -(define_insn "atomic_fetch_" +(define_insn "lrsc_atomic_" + [(set (match_operand:GPR 0 "memory_operand" "+A") + (unspec_volatile:GPR + [(any_atomic:GPR (match_dup 0) + (match_operand:GPR 1 "reg_or_0_operand" "rJ")) + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP)) + (clobber (match_scratch:GPR 3 "=&r"))] ;; tmp_1 + "!TARGET_ZAAMO && TARGET_ZALRSC" + { + return "1:\;" + "lr.%I2\t%3, %0\;" + "\t%3, %3, %1\;" + "sc.%J2\t%3, %3, %0\;" + "bnez\t%3, 1b"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 16))]) + +;; AMO fetch ops + +(define_expand "atomic_fetch_" + [(match_operand:GPR 0 "register_operand") ;; old value at mem + (any_atomic:GPR (match_operand:GPR 1 "memory_operand") ;; mem location + (match_operand:GPR 2 "reg_or_0_operand")) ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model + "TARGET_ZAAMO || TARGET_ZALRSC" + { + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_fetch_ (operands[0], operands[1], + operands[2], operands[3])); + else + emit_insn (gen_lrsc_atomic_fetch_ (operands[0], operands[1], + operands[2], operands[3])); + DONE; + }) + +(define_insn "amo_atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") (match_operand:GPR 1 "memory_operand" "+A")) (set (match_dup 1) @@ -112,6 +166,27 @@ [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) +(define_insn "lrsc_atomic_fetch_" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (match_operand:GPR 1 "memory_operand" "+A")) + (set (match_dup 1) + (unspec_volatile:GPR + [(any_atomic:GPR (match_dup 1) + (match_operand:GPR 2 "reg_or_0_operand" "rJ")) + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP)) + (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 + "!TARGET_ZAAMO && TARGET_ZALRSC" + { + return "1:\;" + "lr.%I3\t%0, %1\;" + "\t%4, %0, %2\;" + "sc.%J3\t%4, %4, %1\;" + "bnez\t%4, 1b"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 20))]) + (define_insn "subword_atomic_fetch_strong_" [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem (match_operand:SI 1 "memory_operand" "+A")) ;; mem location @@ -248,7 +323,23 @@ DONE; }) -(define_insn "atomic_exchange" +(define_expand "atomic_exchange" + [(match_operand:GPR 0 "register_operand") ;; old value at mem + (match_operand:GPR 1 "memory_operand") ;; mem location + (match_operand:GPR 2 "register_operand") ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model + "TARGET_ZAAMO || TARGET_ZALRSC" + { + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_exchange (operands[0], operands[1], + operands[2], operands[3])); + else + emit_insn (gen_lrsc_atomic_exchange (operands[0], operands[1], + operands[2], operands[3])); + DONE; + }) + +(define_insn "amo_atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+A") @@ -261,6 +352,26 @@ [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) +(define_insn "lrsc_atomic_exchange" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "+A") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_EXCHANGE)) + (set (match_dup 1) + (match_operand:GPR 2 "register_operand" "0")) + (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 + "!TARGET_ZAAMO && TARGET_ZALRSC" + { + return "1:\;" + "lr.%I3\t%4, %1\;" + "sc.%J3\t%0, %0, %1\;" + "bnez\t%0, 1b\;" + "mv\t%0, %4"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 20))]) + (define_expand "atomic_exchange" [(match_operand:SHORT 0 "register_operand") ;; old value at mem (match_operand:SHORT 1 "memory_operand") ;; mem location @@ -516,7 +627,7 @@ [(match_operand:QI 0 "register_operand" "") ;; bool output (match_operand:QI 1 "memory_operand" "+A") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "TARGET_ZALRSC" + "TARGET_ZAAMO || TARGET_ZALRSC" { /* We have no QImode atomics, so use the address LSBs to form a mask, then use an aligned SImode atomic. */ @@ -537,7 +648,10 @@ rtx shifted_set = gen_reg_rtx (SImode); riscv_lshift_subword (QImode, set, shift, &shifted_set); - emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); + else if (TARGET_ZALRSC) + emit_insn (gen_lrsc_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c new file mode 100644 index 00000000000..1c124c2b8b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* Ensure that AMO ops are emitted when both zalrsc and zaamo are enabled. */ +/* { dg-options "-O3" } */ +/* { dg-add-options riscv_zalrsc } */ +/* { dg-add-options riscv_zaamo } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** amoadd\.w\tzero,a1,0\(a0\) +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c new file mode 100644 index 00000000000..3fa74332433 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c new file mode 100644 index 00000000000..af0a2d50d38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w.aq\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c new file mode 100644 index 00000000000..521869b2165 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c new file mode 100644 index 00000000000..8b6e7579f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w.aq\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c new file mode 100644 index 00000000000..0bdc47d5c46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +}