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Mon, 10 Jun 2024 16:05:20 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id DD3B540045; Mon, 10 Jun 2024 16:05:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4EC1821A224; Mon, 10 Jun 2024 16:04:56 +0200 (CEST) Received: from jkgcxl0004.jkg.st.com (10.74.22.255) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 16:04:55 +0200 From: =?utf-8?q?Torbj=C3=B6rn_SVENSSON?= To: CC: , , , , =?utf-8?q?Torbj?= =?utf-8?q?=C3=B6rn_SVENSSON?= Subject: [PATCH v3 1/2] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253] Date: Mon, 10 Jun 2024 16:04:36 +0200 Message-ID: <20240610140437.966245-2-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240610140437.966245-1-torbjorn.svensson@foss.st.com> References: <51e7905e-60da-27ae-19c1-286128899e93@arm.com> <20240610140437.966245-1-torbjorn.svensson@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.74.22.255] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-10_02,2024-06-10_01,2024-05-17_01 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Properly handle zero and sign extension for Armv8-M.baseline as Cortex-M23 can have the security extension active. Currently, there is an internal compiler error on Cortex-M23 for the epilog processing of sign extension. This patch addresses the following CVE-2024-0151 for Armv8-M.baseline. gcc/ChangeLog: PR target/115253 * config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear): Sign extend for Thumb1. (thumb1_expand_prologue): Add zero/sign extend. Signed-off-by: Torbjörn SVENSSON Co-authored-by: Yvan ROUX --- gcc/config/arm/arm.cc | 71 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 63 insertions(+), 8 deletions(-) diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index ea0c963a4d6..e7b4caf1083 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -19220,17 +19220,22 @@ cmse_nonsecure_call_inline_register_clear (void) || TREE_CODE (ret_type) == BOOLEAN_TYPE) && known_lt (GET_MODE_SIZE (TYPE_MODE (ret_type)), 4)) { - machine_mode ret_mode = TYPE_MODE (ret_type); + rtx ret_reg = gen_rtx_REG (TYPE_MODE (ret_type), R0_REGNUM); + rtx si_reg = gen_rtx_REG (SImode, R0_REGNUM); rtx extend; if (TYPE_UNSIGNED (ret_type)) - extend = gen_rtx_ZERO_EXTEND (SImode, - gen_rtx_REG (ret_mode, R0_REGNUM)); + extend = gen_rtx_SET (si_reg, gen_rtx_ZERO_EXTEND (SImode, + ret_reg)); else - extend = gen_rtx_SIGN_EXTEND (SImode, - gen_rtx_REG (ret_mode, R0_REGNUM)); - emit_insn_after (gen_rtx_SET (gen_rtx_REG (SImode, R0_REGNUM), - extend), insn); - + /* Signed-extension is a special case because of + thumb1_extendhisi2. */ + if (TARGET_THUMB1 + && known_ge (GET_MODE_SIZE (TYPE_MODE (ret_type)), 2)) + extend = gen_thumb1_extendhisi2 (si_reg, ret_reg); + else + extend = gen_rtx_SET (si_reg, gen_rtx_SIGN_EXTEND (SImode, + ret_reg)); + emit_insn_after (extend, insn); } @@ -27250,6 +27255,56 @@ thumb1_expand_prologue (void) live_regs_mask = offsets->saved_regs_mask; lr_needs_saving = live_regs_mask & (1 << LR_REGNUM); + /* The AAPCS requires the callee to widen integral types narrower + than 32 bits to the full width of the register; but when handling + calls to non-secure space, we cannot trust the callee to have + correctly done so. So forcibly re-widen the result here. */ + if (IS_CMSE_ENTRY (func_type)) + { + function_args_iterator args_iter; + CUMULATIVE_ARGS args_so_far_v; + cumulative_args_t args_so_far; + bool first_param = true; + tree arg_type; + tree fndecl = current_function_decl; + tree fntype = TREE_TYPE (fndecl); + arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl); + args_so_far = pack_cumulative_args (&args_so_far_v); + FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter) + { + rtx arg_rtx; + + if (VOID_TYPE_P (arg_type)) + break; + + function_arg_info arg (arg_type, /*named=*/true); + if (!first_param) + /* We should advance after processing the argument and pass + the argument we're advancing past. */ + arm_function_arg_advance (args_so_far, arg); + first_param = false; + arg_rtx = arm_function_arg (args_so_far, arg); + gcc_assert (REG_P (arg_rtx)); + if ((TREE_CODE (arg_type) == INTEGER_TYPE + || TREE_CODE (arg_type) == ENUMERAL_TYPE + || TREE_CODE (arg_type) == BOOLEAN_TYPE) + && known_lt (GET_MODE_SIZE (GET_MODE (arg_rtx)), 4)) + { + rtx res_reg = gen_rtx_REG (SImode, REGNO (arg_rtx)); + if (TYPE_UNSIGNED (arg_type)) + emit_set_insn (res_reg, gen_rtx_ZERO_EXTEND (SImode, arg_rtx)); + else + /* Signed-extension is a special case because of + thumb1_extendhisi2. */ + if (known_ge (GET_MODE_SIZE (GET_MODE (arg_rtx)), 2)) + emit_insn (gen_thumb1_extendhisi2 (res_reg, arg_rtx)); + else + emit_set_insn (res_reg, + gen_rtx_SIGN_EXTEND (SImode, arg_rtx)); + } + } + } + /* Extract a mask of the ones we can give to the Thumb's push instruction. */ l_mask = live_regs_mask & 0x40ff; /* Then count how many other high registers will need to be pushed. */ From patchwork Mon Jun 10 14:04:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Torbjorn SVENSSON X-Patchwork-Id: 1945890 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=foss.st.com header.i=@foss.st.com header.a=rsa-sha256 header.s=selector1 header.b=xevfUqZN; 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Mon, 10 Jun 2024 16:05:20 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id DD32F40044; Mon, 10 Jun 2024 16:05:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B8CD221A227; Mon, 10 Jun 2024 16:04:56 +0200 (CEST) Received: from jkgcxl0004.jkg.st.com (10.74.22.255) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 16:04:56 +0200 From: =?utf-8?q?Torbj=C3=B6rn_SVENSSON?= To: CC: , , , , =?utf-8?q?Torbj?= =?utf-8?q?=C3=B6rn_SVENSSON?= Subject: [PATCH v3 2/2] testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253] Date: Mon, 10 Jun 2024 16:04:37 +0200 Message-ID: <20240610140437.966245-3-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240610140437.966245-1-torbjorn.svensson@foss.st.com> References: <51e7905e-60da-27ae-19c1-286128899e93@arm.com> <20240610140437.966245-1-torbjorn.svensson@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.74.22.255] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-10_02,2024-06-10_01,2024-05-17_01 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org For Armv8.1-M, the clearing of the registers is handled differently than for Armv8-M, so update the test case accordingly. gcc/testsuite/ChangeLog: PR target/115253 * gcc.target/arm/cmse/extend-return.c: Update test case condition for Armv8.1-M. Signed-off-by: Torbjörn SVENSSON Co-authored-by: Yvan ROUX --- .../gcc.target/arm/cmse/extend-return.c | 62 +++++++++++++++++-- 1 file changed, 56 insertions(+), 6 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c index 081de0d699f..2288d166bd3 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c +++ b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mcmse -fshort-enums" } */ +/* ARMv8-M expectation with target { ! arm_cmse_clear_ok }. */ +/* ARMv8.1-M expectation with target arm_cmse_clear_ok. */ /* { dg-final { check-function-bodies "**" "" "" } } */ #include @@ -20,7 +22,15 @@ typedef enum offset __attribute__ ((cmse_nonsecure_call)) ns_enum_foo_t (void); typedef bool __attribute__ ((cmse_nonsecure_call)) ns_bool_foo_t (void); /* -**unsignNonsecure0: +**unsignNonsecure0: { target arm_cmse_clear_ok } +** ... +** blxns r[0-3] +** ... +** uxtb r0, r0 +** ... +*/ +/* +**unsignNonsecure0: { target { ! arm_cmse_clear_ok } } ** ... ** bl __gnu_cmse_nonsecure_call ** uxtb r0, r0 @@ -32,7 +42,15 @@ unsigned char unsignNonsecure0 (ns_unsign_foo_t * ns_foo_p) } /* -**signNonsecure0: +**signNonsecure0: { target arm_cmse_clear_ok } +** ... +** blxns r[0-3] +** ... +** sxtb r0, r0 +** ... +*/ +/* +**signNonsecure0: { target { ! arm_cmse_clear_ok } } ** ... ** bl __gnu_cmse_nonsecure_call ** sxtb r0, r0 @@ -44,7 +62,15 @@ signed char signNonsecure0 (ns_sign_foo_t * ns_foo_p) } /* -**shortUnsignNonsecure0: +**shortUnsignNonsecure0: { target arm_cmse_clear_ok } +** ... +** blxns r[0-3] +** ... +** uxth r0, r0 +** ... +*/ +/* +**shortUnsignNonsecure0: { target { ! arm_cmse_clear_ok } } ** ... ** bl __gnu_cmse_nonsecure_call ** uxth r0, r0 @@ -56,7 +82,15 @@ unsigned short shortUnsignNonsecure0 (ns_short_unsign_foo_t * ns_foo_p) } /* -**shortSignNonsecure0: +**shortSignNonsecure0: { target arm_cmse_clear_ok } +** ... +** blxns r[0-3] +** ... +** sxth r0, r0 +** ... +*/ +/* +**shortSignNonsecure0: { target { ! arm_cmse_clear_ok } } ** ... ** bl __gnu_cmse_nonsecure_call ** sxth r0, r0 @@ -68,7 +102,15 @@ signed short shortSignNonsecure0 (ns_short_sign_foo_t * ns_foo_p) } /* -**enumNonsecure0: +**enumNonsecure0: { target arm_cmse_clear_ok } +** ... +** blxns r[0-3] +** ... +** uxtb r0, r0 +** ... +*/ +/* +**enumNonsecure0: { target { ! arm_cmse_clear_ok } } ** ... ** bl __gnu_cmse_nonsecure_call ** uxtb r0, r0 @@ -80,7 +122,15 @@ unsigned char __attribute__((noipa)) enumNonsecure0 (ns_enum_foo_t * ns_foo_p) } /* -**boolNonsecure0: +**boolNonsecure0: { target arm_cmse_clear_ok } +** ... +** blxns r[0-3] +** ... +** uxtb r0, r0 +** ... +*/ +/* +**boolNonsecure0: { target { ! arm_cmse_clear_ok } } ** ... ** bl __gnu_cmse_nonsecure_call ** uxtb r0, r0