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X-CSE-ConnectionGUID: VNdOpzqJQgeqh5gU5EMi8A== X-CSE-MsgGUID: llQDF+xoSyyxFYrHE5l1FQ== X-IronPort-AV: E=McAfee;i="6600,9927,11072"; a="15342241" X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="15342241" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2024 07:54:34 -0700 X-CSE-ConnectionGUID: vJ1t4d7RSXOBRvuBa7gX0w== X-CSE-MsgGUID: 6TkWRLmRTa673wcY6sCVQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="34905607" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa004.fm.intel.com with ESMTP; 13 May 2024 07:54:31 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 40F901005664; Mon, 13 May 2024 22:54:30 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, Tamar.Christina@arm.com, richard.sandiford@arm.com, Pan Li Subject: [PATCH v1 1/3] Vect: Support loop len in vectorizable early exit Date: Mon, 13 May 2024 22:54:28 +0800 Message-Id: <20240513145428.148553-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch adds early break auto-vectorization support for target which use length on partial vectorization. Consider this following example: unsigned vect_a[802]; unsigned vect_b[802]; void test (unsigned x, int n) {  for (int i = 0; i < n; i++)  {    vect_b[i] = x + i;    if (vect_a[i] > x)      break;    vect_a[i] = x;  } } We use VCOND_MASK_LEN to simulate the generate (mask && i < len + bias). And then the IR of RVV looks like below:   ...   _87 = .SELECT_VL (ivtmp_85, POLY_INT_CST [32, 32]);   _55 = (int) _87;   ...   mask_patt_6.13_69 = vect_cst__62 < vect__3.12_67;   vec_len_mask_72 = .VCOND_MASK_LEN (mask_patt_6.13_69, { -1, ... }, \ {0, ... }, _87, 0);   if (vec_len_mask_72 != { 0, ... })     goto ; [5.50%]   else     goto ; [94.50%] The below tests are passed for this patch: 1. The riscv fully regression tests. 2. The aarch64 fully regression tests. 3. The x86 bootstrap tests. 4. The x86 fully regression tests. gcc/ChangeLog: * tree-vect-stmts.cc (vectorizable_early_exit): Add loop len handling for one or multiple stmt. Signed-off-by: Pan Li --- gcc/tree-vect-stmts.cc | 47 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index 21e8fe98e44..bfd9d66568f 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -12896,7 +12896,9 @@ vectorizable_early_exit (vec_info *vinfo, stmt_vec_info stmt_info, ncopies = vect_get_num_copies (loop_vinfo, vectype); vec_loop_masks *masks = &LOOP_VINFO_MASKS (loop_vinfo); + vec_loop_lens *lens = &LOOP_VINFO_LENS (loop_vinfo); bool masked_loop_p = LOOP_VINFO_FULLY_MASKED_P (loop_vinfo); + bool len_loop_p = LOOP_VINFO_FULLY_WITH_LENGTH_P (loop_vinfo); /* Now build the new conditional. Pattern gimple_conds get dropped during codegen so we must replace the original insn. */ @@ -12960,12 +12962,11 @@ vectorizable_early_exit (vec_info *vinfo, stmt_vec_info stmt_info, { if (direct_internal_fn_supported_p (IFN_VCOND_MASK_LEN, vectype, OPTIMIZE_FOR_SPEED)) - return false; + vect_record_loop_len (loop_vinfo, lens, ncopies, vectype, 1); else vect_record_loop_mask (loop_vinfo, masks, ncopies, vectype, NULL); } - return true; } @@ -13018,6 +13019,25 @@ vectorizable_early_exit (vec_info *vinfo, stmt_vec_info stmt_info, stmts[i], &cond_gsi); workset.quick_push (stmt_mask); } + else if (len_loop_p) + for (unsigned i = 0; i < stmts.length (); i++) + { + tree all_ones_mask = build_all_ones_cst (vectype); + tree all_zero_mask = build_zero_cst (vectype); + tree len = vect_get_loop_len (loop_vinfo, gsi, lens, ncopies, + vectype, i, 1); + signed char cst = LOOP_VINFO_PARTIAL_LOAD_STORE_BIAS (loop_vinfo); + tree bias = build_int_cst (intQI_type_node, cst); + tree len_mask + = make_temp_ssa_name (TREE_TYPE (stmts[i]), NULL, "vec_len_mask"); + gcall *call = gimple_build_call_internal (IFN_VCOND_MASK_LEN, 5, + stmts[i], all_ones_mask, + all_zero_mask, len, bias); + gimple_call_set_lhs (call, len_mask); + gsi_insert_before (&cond_gsi, call, GSI_SAME_STMT); + + workset.quick_push (len_mask); + } else workset.splice (stmts); @@ -13042,6 +13062,29 @@ vectorizable_early_exit (vec_info *vinfo, stmt_vec_info stmt_info, new_temp = prepare_vec_mask (loop_vinfo, TREE_TYPE (mask), mask, new_temp, &cond_gsi); } + else if (len_loop_p) + { + /* len_mask = VCOND_MASK_LEN (compare_mask, ones, zero, len, bias) + + which is equivalent to: + + len_mask = compare_mask mask && i < len ? 1 : 0 + */ + tree all_ones_mask = build_all_ones_cst (vectype); + tree all_zero_mask = build_zero_cst (vectype); + tree len + = vect_get_loop_len (loop_vinfo, gsi, lens, ncopies, vectype, 0, 1); + signed char biasval = LOOP_VINFO_PARTIAL_LOAD_STORE_BIAS (loop_vinfo); + tree bias = build_int_cst (intQI_type_node, biasval); + tree len_mask + = make_temp_ssa_name (TREE_TYPE (new_temp), NULL, "vec_len_mask"); + gcall *call = gimple_build_call_internal (IFN_VCOND_MASK_LEN, 5, + new_temp, all_ones_mask, + all_zero_mask, len, bias); + gimple_call_set_lhs (call, len_mask); + gsi_insert_before (&cond_gsi, call, GSI_SAME_STMT); + new_temp = len_mask; + } } gcc_assert (new_temp); From patchwork Mon May 13 14:55:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1934752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=lw2WdFoG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VdMxn5txTz1yfq for ; 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X-CSE-ConnectionGUID: rS5Y2bheR/Ccn9VFYjxYZg== X-CSE-MsgGUID: C5ERNNzbQfCn+A0wIUqpMg== X-IronPort-AV: E=McAfee;i="6600,9927,11072"; a="22949031" X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="22949031" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2024 07:55:49 -0700 X-CSE-ConnectionGUID: K++zRZzITma4xTimvPsQMw== X-CSE-MsgGUID: cYBe2YjlTgWfeC4QZQ2VgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="30763428" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa006.jf.intel.com with ESMTP; 13 May 2024 07:55:47 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 7880A1005664; Mon, 13 May 2024 22:55:46 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, Tamar.Christina@arm.com, richard.sandiford@arm.com, Pan Li Subject: [PATCH v1 2/3] RISC-V: Implement vectorizable early exit with vcond_mask_len Date: Mon, 13 May 2024 22:55:43 +0800 Message-Id: <20240513145543.149757-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch depends on below middle-end implementation. https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651459.html After we support the loop lens for the vectorizable, we would like to implement the feature for the RISC-V target. Given below example: unsigned vect_a[1923]; unsigned vect_b[1923]; unsigned test (unsigned limit, int n) { unsigned ret = 0; for (int i = 0; i < n; i++) { vect_b[i] = limit + i; if (vect_a[i] > limit) { ret = vect_b[i]; return ret; } vect_a[i] = limit; } return ret; } Before this patch: ... .L8: sw a3,0(a5) addiw a0,a0,1 addi a4,a4,4 addi a5,a5,4 beq a1,a0,.L2 .L4: sw a0,0(a4) lw a2,0(a5) bleu a2,a3,.L8 ret After this patch: ... .L5: vsetvli a5,a3,e8,mf4,ta,ma vmv1r.v v4,v2 vsetvli t4,zero,e32,m1,ta,ma vmv.v.x v1,a5 vadd.vv v2,v2,v1 vsetvli zero,a5,e32,m1,ta,ma vadd.vv v5,v4,v3 slli a6,a5,2 vle32.v v1,0(t1) vmsltu.vv v1,v3,v1 vcpop.m t4,v1 beq t4,zero,.L4 vmv.x.s a4,v4 .L3: ... The below tests are passed for this patch: 1. The riscv fully regression tests. gcc/ChangeLog: * config/riscv/autovec-opt.md (*vcond_mask_len_popcount_): New pattern of vcond_mask_len_popcount for vector bool mode. * config/riscv/autovec.md (vcond_mask_len_): New pattern of vcond_mask_len for vector bool mode. (cbranch4): New pattern for vector bool mode. * config/riscv/vector-iterators.md: Add new unspec UNSPEC_SELECT_MASK. * config/riscv/vector.md (@pred_popcount): Add VLS mode to popcount pattern. (@pred_popcount): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/early-break-1.c: New test. * gcc.target/riscv/rvv/autovec/early-break-2.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/autovec-opt.md | 33 ++++++++++ gcc/config/riscv/autovec.md | 60 +++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 1 + gcc/config/riscv/vector.md | 18 +++--- .../riscv/rvv/autovec/early-break-1.c | 34 +++++++++++ .../riscv/rvv/autovec/early-break-2.c | 37 ++++++++++++ 6 files changed, 174 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 645dc53d868..04f85d8e455 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1436,3 +1436,36 @@ (define_insn_and_split "*n" DONE; } [(set_attr "type" "vmalu")]) + +;; Optimization pattern for early break auto-vectorization +;; vcond_mask_len (mask, ones, zeros, len, bias) + vlmax popcount +;; -> non vlmax popcount (mask, len) +(define_insn_and_split "*vcond_mask_len_popcount_" + [(set (match_operand:P 0 "register_operand") + (popcount:P + (unspec:VB_VLS [ + (unspec:VB_VLS [ + (match_operand:VB_VLS 1 "register_operand") + (match_operand:VB_VLS 2 "const_1_operand") + (match_operand:VB_VLS 3 "const_0_operand") + (match_operand 4 "autovec_length_operand") + (match_operand 5 "const_0_operand")] UNSPEC_SELECT_MASK) + (match_operand 6 "autovec_length_operand") + (const_int 1) + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))] + "TARGET_VECTOR + && can_create_pseudo_p () + && riscv_vector::get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists ()" + "#" + "&& 1" + [(const_int 0)] + { + riscv_vector::emit_nonvlmax_insn ( + code_for_pred_popcount (mode, Pmode), + riscv_vector::CPOP_OP, + operands, operands[4]); + DONE; + } + [(set_attr "type" "vector")] +) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index aa1ae0fe075..dfa58b8af69 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2612,3 +2612,63 @@ (define_expand "rawmemchr" DONE; } ) + +;; ========================================================================= +;; == Early break auto-vectorization patterns +;; ========================================================================= + +;; vcond_mask_len +(define_insn_and_split "vcond_mask_len_" + [(set (match_operand:VB 0 "register_operand") + (unspec: VB [ + (match_operand:VB 1 "register_operand") + (match_operand:VB 2 "const_1_operand") + (match_operand:VB 3 "const_0_operand") + (match_operand 4 "autovec_length_operand") + (match_operand 5 "const_0_operand")] UNSPEC_SELECT_MASK))] + "TARGET_VECTOR + && can_create_pseudo_p () + && riscv_vector::get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists ()" + "#" + "&& 1" + [(const_int 0)] + { + machine_mode mode = riscv_vector::get_vector_mode (Pmode, + GET_MODE_NUNITS (mode)).require (); + rtx reg = gen_reg_rtx (mode); + riscv_vector::expand_vec_series (reg, const0_rtx, const1_rtx); + rtx dup_rtx = gen_rtx_VEC_DUPLICATE (mode, operands[4]); + insn_code icode = code_for_pred_cmp_scalar (mode); + rtx cmp = gen_rtx_fmt_ee (LTU, mode, reg, dup_rtx); + rtx ops[] = {operands[0], operands[1], operands[1], cmp, reg, operands[4]}; + emit_vlmax_insn (icode, riscv_vector::COMPARE_OP_MU, ops); + DONE; + } + [(set_attr "type" "vector")]) + +;; cbranch +(define_expand "cbranch4" + [(set (pc) + (if_then_else + (match_operator 0 "equality_operator" + [(match_operand:VB_VLS 1 "register_operand") + (match_operand:VB_VLS 2 "reg_or_0_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "TARGET_VECTOR" + { + rtx pred; + if (operands[2] == CONST0_RTX (mode)) + pred = operands[1]; + else + pred = expand_binop (mode, xor_optab, operands[1], + operands[2], NULL_RTX, 0, + OPTAB_DIRECT); + rtx reg = gen_reg_rtx (Pmode); + rtx cpop_ops[] = {reg, pred}; + emit_vlmax_insn (code_for_pred_popcount (mode, Pmode), + riscv_vector::CPOP_OP, cpop_ops); + operands[1] = reg; + operands[2] = const0_rtx; + } +) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a24e1bf078f..76c27035a73 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -102,6 +102,7 @@ (define_c_enum "unspec" [ UNSPEC_WREDUC_SUMU UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED + UNSPEC_SELECT_MASK ]) (define_c_enum "unspecv" [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 228d0f9a766..95451dc762b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6121,21 +6121,21 @@ (define_insn "@pred_not" (set_attr "vl_op_idx" "4") (set (attr "avl_type_idx") (const_int 5))]) -(define_insn "@pred_popcount" - [(set (match_operand:P 0 "register_operand" "=r") +(define_insn "@pred_popcount" + [(set (match_operand:P 0 "register_operand" "=r") (popcount:P - (unspec:VB - [(and:VB - (match_operand:VB 1 "vector_mask_operand" "vmWc1") - (match_operand:VB 2 "register_operand" " vr")) - (match_operand 3 "vector_length_operand" " rK") - (match_operand 4 "const_int_operand" " i") + (unspec:VB_VLS + [(and:VB_VLS + (match_operand:VB_VLS 1 "vector_mask_operand" "vmWc1") + (match_operand:VB_VLS 2 "register_operand" " vr")) + (match_operand 3 "vector_length_operand" " rK") + (match_operand 4 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))] "TARGET_VECTOR" "vcpop.m\t%0,%2%p1" [(set_attr "type" "vmpop") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_insn "@pred_ffs" [(set (match_operand:P 0 "register_operand" "=r") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c new file mode 100644 index 00000000000..f70979e81f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -fdump-tree-vect-details" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define N 803 + +unsigned vect_a[N]; +unsigned vect_b[N]; + +/* +** test: +** ... +** vmsltu\.vv\s+v[0-9]+\s*,v[0-9]+,\s*v[0-9]+ +** vcpop\.m\s+[atx][0-9]+\s*,v[0-9]+ +** ... +*/ +unsigned test (unsigned x, int n) +{ + unsigned ret = 0; + + for (int i = 0; i < n; i++) + { + vect_b[i] = x + i; + + if (vect_a[i] > x) + break; + + vect_a[i] = x; + } + + return ret; +} + +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c new file mode 100644 index 00000000000..d405783d2c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -fdump-tree-vect-details" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define N 1728 + +unsigned vect_a[N]; +unsigned vect_b[N]; + +/* +** test: +** ... +** vmsltu\.vv\s+v[0-9]+\s*,v[0-9]+,\s*v[0-9]+ +** vcpop\.m\s+[atx][0-9]+\s*,v[0-9]+ +** ... +*/ +unsigned test (unsigned limit, int n) +{ + unsigned ret = 0; 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X-CSE-ConnectionGUID: XOLPx6nKSRWfsVQBsLaDWg== X-CSE-MsgGUID: MPEt/HcQT++qsJh5NHnZmQ== X-IronPort-AV: E=McAfee;i="6600,9927,11072"; a="29068326" X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="29068326" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2024 07:56:52 -0700 X-CSE-ConnectionGUID: Fd/cPCLCQKmdAGygKCC6fg== X-CSE-MsgGUID: l5WLzLPZTw6hdtLAL/W0xA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="34905866" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa004.fm.intel.com with ESMTP; 13 May 2024 07:56:50 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id CA942100566B; Mon, 13 May 2024 22:56:48 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, Tamar.Christina@arm.com, richard.sandiford@arm.com, Pan Li Subject: [PATCH v1 3/3] RISC-V: Enable vectorizable early exit test Date: Mon, 13 May 2024 22:56:47 +0800 Message-Id: <20240513145647.150975-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch depends on below 2 patches. https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651459.html https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651460.html After we supported vectorizable early exit in RISC-V, we would like to enable the gcc vect test for vectorizable early test. The vect-early-break_124-pr114403.c failed to vectorize for now. Because that the __builtin_memcpy with 8 bytes failed to folded into int64 assignment during ccp1. We will improve that first and mark this as xfail for RISC-V. The below tests are passed for this patch: 1. The riscv fully regression tests. 2. The aarch64 fully regression tests. 3. The x86 bootstrap tests. 4. The x86 fully regression tests. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-mask-store-1.c: Add pragma novector as it will have 2 times LOOP VECTORIZED in RISC-V. * gcc.dg/vect/vect-early-break_124-pr114403.c: Xfail for the riscv backend. * lib/target-supports.exp: Add RISC-V backend. Signed-off-by: Pan Li --- gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c | 2 ++ gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c | 2 +- gcc/testsuite/lib/target-supports.exp | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c b/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c index fdd9032da98..2f80bf89e5e 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c +++ b/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c @@ -28,6 +28,8 @@ main () if (__builtin_memcmp (x, res, sizeof (x)) != 0) abort (); + +#pragma GCC novector for (int i = 0; i < 32; ++i) if (flag[i] != 0 && flag[i] != 1) abort (); diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c index 51abf245ccb..101ae1e0eaa 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c @@ -2,7 +2,7 @@ /* { dg-require-effective-target vect_early_break_hw } */ /* { dg-require-effective-target vect_long_long } */ -/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { xfail riscv*-*-* } } } */ #include "tree-vect.h" diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 6f5d477b128..adaa5912588 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4099,6 +4099,7 @@ proc check_effective_target_vect_early_break { } { || [check_effective_target_arm_v8_neon_ok] || [check_effective_target_sse4] || [istarget amdgcn-*-*] + || [check_effective_target_riscv_v] }}] } @@ -4114,6 +4115,7 @@ proc check_effective_target_vect_early_break_hw { } { || [check_effective_target_arm_v8_neon_hw] || [check_sse4_hw_available] || [istarget amdgcn-*-*] + || [check_effective_target_riscv_v] }}] }