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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3502bbbbf08sm2588185f8f.96.2024.05.09.13.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 13:48:04 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Date: Thu, 9 May 2024 22:47:46 +0200 Message-ID: <20240509204750.1538-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240509204750.1538-1-ansuelsmth@gmail.com> References: <20240509204750.1538-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where CBR(Core Base Register) address might badly/never inizialized by the Bootloader or reaching it from co-processor registers if the system boots from secondary CPU results in invalid address. The CBR address is always the same on the SoC. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by: Christian Marangi Acked-by: Conor Dooley --- .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..6b961b62aff2 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,16 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where CBR(Core Base Register) + address might badly/never inizialized by the Bootloader or + reaching it from co-processor registers if the system + boots from secondary CPU results in invalid address. + The CBR address is always the same on the SoC hence it + can be provided in DT to handle these broken case. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +74,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: