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Thu, 09 May 2024 07:06:57 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baad058sm1793311f8f.66.2024.05.09.07.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 07:06:56 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee , Conor Dooley Subject: [PATCH v3 1/7] dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3128 DSI Date: Thu, 9 May 2024 16:06:47 +0200 Message-ID: <20240509140653.168591-2-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509140653.168591-1-knaerzche@gmail.com> References: <20240509140653.168591-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the MIPI DSI controller for Rockchip RK3128. The integration is similar to PX30 so it's bindings-constraints can be re-used. Signed-off-by: Alex Bee Acked-by: Conor Dooley --- changes since v1: - added ahb clock changes since v2: - revert added ahb clock .../rockchip/rockchip,dw-mipi-dsi.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index ccf79e738fa1..ccd71c5324af 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -15,6 +15,7 @@ properties: items: - enum: - rockchip,px30-mipi-dsi + - rockchip,rk3128-mipi-dsi - rockchip,rk3288-mipi-dsi - rockchip,rk3399-mipi-dsi - rockchip,rk3568-mipi-dsi @@ -77,6 +78,7 @@ allOf: contains: enum: - rockchip,px30-mipi-dsi + - rockchip,rk3128-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi From patchwork Thu May 9 14:06:48 2024 Content-Type: text/plain; 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Thu, 09 May 2024 07:06:59 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baad058sm1793311f8f.66.2024.05.09.07.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 07:06:58 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee , Conor Dooley Subject: [PATCH v3 2/7] dt-bindings: clock: rk3128: Add PCLK_MIPIPHY Date: Thu, 9 May 2024 16:06:48 +0200 Message-ID: <20240509140653.168591-3-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509140653.168591-1-knaerzche@gmail.com> References: <20240509140653.168591-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The DPHY's APB clock is required to be exposed in order to be able to enable it and access the phy's registers. Signed-off-by: Alex Bee Acked-by: Conor Dooley --- changes since v1: - none include/dt-bindings/clock/rk3128-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index 6a47825dac5d..1be455ba4985 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -116,6 +116,7 @@ #define PCLK_GMAC 367 #define PCLK_PMU_PRE 368 #define PCLK_SIM_CARD 369 +#define PCLK_MIPIPHY 370 /* hclk gates */ #define HCLK_SPDIF 440