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Signed-off-by: Alex Soo --- .../pinctrl/starfive,jh8100-aon-pinctrl.yaml | 260 ++++++++++++++++++ .../starfive,jh8100-sys-east-pinctrl.yaml | 222 +++++++++++++++ .../starfive,jh8100-sys-gmac-pinctrl.yaml | 162 +++++++++++ .../starfive,jh8100-sys-west-pinctrl.yaml | 219 +++++++++++++++ .../pinctrl/starfive,jh8100-pinctrl.h | 13 + 5 files changed, 876 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml new file mode 100644 index 000000000000..abd2a7570a54 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-aon-pinctrl.yaml @@ -0,0 +1,260 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-aon-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 AON (always-on) Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "aon" pinctrl domain. + + The "aon" domain has a pin controller which provides + - I/O multiplexing for peripheral signals specific to this domain. + - GPIO pins which support external GPIO interrupts or external wake-up. + - syscon registers to configure device I/O reference voltage. + + In the AON Pin Controller, the pins named PAD_RGPIO0 to PAD_GPIO15 can be + multiplexed and have configurable bias, drive strength, schmitt trigger etc. + Only peripherals in the AON domain can have their I/O go through the 16 + "PAD_RGPIOs". This includes I2C, UART, watchdog, eMMC, SDIO0, XSPI etc. + + All these peripherals can be connected to any of the 16 PAD_RGPIOs in such a way + that any iopad can be set up to be controlled by any of the peripherals. + + The pin muxing is illustrated by the diagram below. + _____________ + | | + RGPIO0 --------------| |--- PAD_RGPIO0 + RGPIO1 --------------| AON I/O MUX |--- PAD_RGPIO1 + ... | | ... + I2C8 SDA interface --| |--- PAD_RGPIO15 + | | + ------------- + + The AON Pin Controller provides syscon registers to configure + + 1. reference voltage of + - eMMC I/O interface + supported voltage - 1.8V + - SDIO0 I/O interface + supported voltage - 3.3V, 1.8V + - PAD_RGPIO bank + - 16 PAD_RGPIOs (PAD_RGPIO0 to PAD_GPIO15) + - all devices attached to PAD_RGPIOs must use I/O voltage 3.3V. + - XSPI I/O interface + supported voltage level - 3.3V + + Regulator supplies the device voltage, and each device has a corresponding syscon + register bit [1:0] that must be configured to indicate the device voltage level. + + +--------+--------+-------------------+ + | Bit[1] | Bit[0] | Reference Voltage | + +--------+--------+-------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+-------------------+ + | 0 | 1 | 2.5 V | + +--------+--------+-------------------+ + | 1 | x | 1.8 V | + +--------+--------+-------------------+ + + 2. reference voltage and slew rate of GMAC0 + + Voltage level on GMAC0 interface is dependent on the PHY that it is pairing with. The + supported voltage levels are 3.3V, 2.5V, and 1.8V. + + GMAC0 has 2 set of syscon registers - + + 2.1 PAD_VREF_GMAC0_syscon - bit [1:0] must be configured to indicate the voltage level on + GMAC0 interface. The default setting is 3.3V. + + +--------+--------+-----------------------------------+ + | Bit[1] | Bit[0] | GMAC0 Interface Reference Voltage | + +--------+--------+-----------------------------------+ + | 0 | 0 | 3.3V | + +--------+--------+-----------------------------------+ + | 0 | 1 | 2.5V | + +--------+--------+-----------------------------------+ + | 1 | x | 1.8V | + +--------+--------+-----------------------------------+ + + 2.2 PAD_GMAC0__syscon - each GMAC0 pad has a corresponding syscon bit [0] set + to 0 by default. When GMAC0 mode is RGMII and voltage level is 2.5V, the bit [0] must be + set to 1. + + +-------------+-----------------------+---------+ + | GMAC0 Mode | GMAC0 Voltage Level | Bit[0] | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RGMII | 2.5V | 1 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RMII | 2.5V | 0 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + + the bit [2] can be used to configure GMAC0 signal slew rate, + + +--------+-----------+ + | Bit[2] | Slew Rate | + +--------+-----------+ + | 0 | Fast | + +--------+-----------+ + | 1 | Slow | + +--------+-----------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual device voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-aon-pinctrl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-gpios: + maxItems: 1 + description: GPIO pin to be used for waking up the system from sleep mode. + + wakeup-source: + maxItems: 1 + description: to indicate pinctrl has wakeup capability. + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings or function select. + The GPIOMUX and PINMUX macros are used to configure the + I/O multiplexing and function selection respectively. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow (half frequency) + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_aon: pinctrl@1f300000 { + compatible = "starfive,jh8100-aon-pinctrl", "syscon", "simple-mfd"; + reg = <0x0 0x1f300000 0x0 0x10000>; + resets = <&aoncrg 0>; + interrupts = <160>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aon 0 0 16>; + + i2c7_pins: i2c7-grp { + i2c7-scl-pins { + pinmux = <0x23265409>; + bias-pull-up; + input-enable; + }; + + i2c7-sda-pins { + pinmux = <0x2427580a>; + bias-pull-up; + input-enable; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml new file mode 100644 index 000000000000..6ad518e9bee2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml @@ -0,0 +1,222 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-sys-east-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 SYS_EAST Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "sys_east" pinctrl domain. + + The "sys_east" domain has a pin controller which provides + - I/O multiplexing for peripheral signals specific to this domain. + - function selection for GPIO pads. + - GPIO interrupt handling. + - syscon for device voltage reference. + + In the SYS_EAST Pin Controller, the pins named PAD_GPIO0_E to PAD_GPIO47_E can + be multiplexed and have configurable bias, drive strength, schmitt trigger etc. + Only peripherals in the SYS_EAST domain can have their I/O go through the 48 + "PAD_GPIOs". This includes CANs, I2Cs, I2Ss, SPIs, UARTs, PWMs, SMBUS0, SDIO1 etc. + + All these peripherals can be connected to any of the 48 PAD_GPIOs in such a way + that any iopad can be set up to be controlled by any of the peripherals. + + The pin muxing is illustrated by the diagram below. + __________________ + | | + GPIO0 ----------------------| |--- PAD_GPIO0_E + GPIO1 ----------------------| SYS_EAST I/O MUX |--- PAD_GPIO1_E + GPIO2 ----------------------| |--- PAD_GPIO2_E + ... | | ... + I2C0 Clock interface -------| |--- PAD_GPIO9_E + I2C0 Data interface -------| |--- PAD_GPIO10_E + ... | | ... + UART0 transmit interface ---| |--- PAD_GPIO20_E + UART0 receive interface ----| |--- PAD_GPIO21_E + ... | | ... + GPIO47 ---------------------| |--- PAD_GPIO47_E + | | + ------------------ + + Alternatively, the "PAD_GPIOs" can be multiplexed to other peripherals through + function selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2. + Function 0 is the default function or peripheral signal of an iopad. + The function 1 and function 2 are other optional functions or peripheral signals + available to an iopad. The function selection can be carried out by writing the + function number to the iopad function select register. + + The "sys_east" domain has 4 PAD_GPIO banks - + E0 - 16 PAD_GPIOs (PAD_GPIO0_E to PAD_GPIO15_E) + E1 - 16 PAD_GPIOs (PAD_GPIO16_E to PAD_GPIO31_E) + E2 - 8 PAD_GPIOs (PAD_GPIO32_E to PAD_GPIO39_E) + E3 - 8 PAD_GPIOs (PAD_GPIO40_E to PAD_GPIO47_E) + + Each PAD_GPIO bank can be set to a voltage level 3.3V or 1.8V. All devices attached + to the PAD_GPIOs must use the same I/O voltage level as the bank voltage setting. + This allows user to select different I/O voltages for their devices. For instance, + the UART have 3.3V/1.8V requirement, the UART devices that use 1.8V are attached + to a PAD_GPIO bank which is configured to 1.8V. + + Regulators supply voltages to the PAD_GPIO banks, and each PAD_GPIO bank has a corresponding + syscon bit [1:0] that must be configured to indicate its voltage level. The default setting + is 3.3V. + + +--------+--------+-------------------+ + | Bit[1] | Bit[0] | Reference Voltage | + +--------+--------+-------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+-------------------+ + | 1 | x | 1.8 V | + +--------+--------+-------------------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual device voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-sys-pinctrl-east + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings or function select. + The GPIOMUX and PINMUX macros are used to configure the + I/O multiplexing and function selection respectively. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow (half frequency) + 1: fast + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - interrupt-controller + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_east: pinctrl@122d0000 { + compatible = "starfive,jh8100-sys-pinctrl-east", "syscon", "simple-mfd"; + reg = <0x0 0x122d0000 0x0 0x10000>; + clocks = <&syscrg_ne 153>; + resets = <&syscrg_ne 48>; + interrupts = <182>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_east 0 0 48>; + + smbus0_pins: smbus0-grp { + smbus0-scl-pins { + pinmux = <0x1122480b>; + bias-pull-up; + input-enable; + }; + + smbus0-sda-pins { + pinmux = <0x12234c0c>; + bias-pull-up; + input-enable; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml new file mode 100644 index 000000000000..567ff0d9fd6c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-sys-gmac-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 SYS_GMAC Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "sys_gmac" pinctrl domain. + + The "sys_gmac" domain has a pin-controller which provides syscon registers to + configure device reference voltage and slew rate. + + The SYS_GMAC Pin Controller does not have any PAD_GPIOs, therefore, it does not + support the GPIO pad I/O Multiplexing and interrupt handling. + + The SYS_GMAC Pin Controller provides syscon registers to configure + + 1. reference voltage of SDIO1 + + The supported voltage levels are 3.3V and 1.8V + + The bit [1:0] must be configured to indicate the SDIO1 voltage level. + + +--------+--------+--------------------------+ + | Bit[1] | Bit[0] | SDIO1 Reference Voltage | + +--------+--------+--------------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+--------------------------+ + | 1 | 0 | 1.8 V | + +--------+--------+--------------------------+ + + 2. reference voltage and slew rate of GMAC1 + + Voltage level on GMAC1 interface is dependent on the PHY that it is pairing with. The + supported voltage levels are 3.3V, 2.5V, and 1.8V. + + GMAC1 has 2 set of syscon registers - + + 2.1 PAD_VREF_GMAC1_syscon - bit [1:0] must be configured to indicate the voltage level on + GMAC1 interface. The default setting is 3.3V. + + +--------+--------+-----------------------------------+ + | Bit[1] | Bit[0] | GMAC1 Interface Reference Voltage | + +--------+--------+-----------------------------------+ + | 0 | 0 | 3.3V | + +--------+--------+-----------------------------------+ + | 0 | 1 | 2.5V | + +--------+--------+-----------------------------------+ + | 1 | x | 1.8V | + +--------+--------+-----------------------------------+ + + 2.2 PAD_GMAC1__syscon - each GMAC1 pad has a corresponding syscon bit [0] set + to 0 by default. When GMAC1 mode is RGMII and voltage level is 2.5V, the bit [0] must be + set to 1. + + +-------------+-----------------------+---------+ + | GMAC1 Mode | GMAC1 Voltage Level | Bit[0] | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RGMII | 2.5V | 1 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + | | 3.3V | 0 | + | |-----------------------+---------+ + | RMII | 2.5V | 0 | + | |-----------------------+---------+ + | | 1.8V | 0 | + +-------------+-----------------------+---------+ + + the bit [2] can be used to configure the GMAC1 signal slew rate, + + +--------+-----------+ + | Bit[2] | Slew Rate | + +--------+-----------+ + | 0 | Fast | + +--------+-----------+ + | 1 | Slow | + +--------+-----------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-sys-pinctrl-gmac + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_gmac: pinctrl@12770000 { + compatible = "starfive,jh8100-sys-pinctrl-gmac", "syscon", "simple-mfd"; + reg = <0x0 0x12770000 0x0 0x10000>; + clocks = <&gmac_sdio_crg 16>; + resets = <&gmac_sdio_crg 3>; + }; + + }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml new file mode 100644 index 000000000000..ecff5656ecc3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh8100-sys-west-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 SYS_WEST Pin Controller + +description: | + Pinctrl bindings for JH8100 RISC-V SoC from StarFive Technology Ltd. + + The JH8100 SoC has 4 pinctrl domains - sys_east, sys_west, sys_gmac, and aon. + This document provides an overview of the "sys_west" pinctrl domain. + + The "sys_west" domain has a pin-controller which provides + - I/O multiplexing for peripheral signals specific to this domain. + - function selection for GPIO pads. + - GPIO interrupt handling. + - syscon for device voltage reference. + + In the SYS_WEST Pin Controller, the pins named PAD_GPIO0_W to PAD_GPIO15_W can + be multiplexed and have configurable bias, drive strength, schmitt trigger etc. + Only peripherals in the SYS_WEST domain can have their I/O go through the 16 + "PAD_GPIOs". This includes I2Cs, HD_AUDIO, HIFI4, SPIs, UARTs, SMBUS1 etc. + + All these peripherals can be connected to any of the 16 PAD_GPIOs in such a way + that any iopad can be set up to be controlled by any of the peripherals. + + The pin muxing is illustrated by the diagram below. + __________________ + | | + GPIO0 ----------------------| |--- PAD_GPIO0_W + GPIO1 ----------------------| SYS_WEST I/O MUX |--- PAD_GPIO1_W + GPIO2 ----------------------| |--- PAD_GPIO2_W + ... | | ... + HIFI4 JTAG TDO interface ---| |--- PAD_GPIO10_W + HIFI4 JTAG TDI interface ---| |--- PAD_GPIO11_W + SMBUS1 Data interface -----| |--- PAD_GPIO12_W + SMBUS1 Clock interface -----| |--- PAD_GPIO13_W + ... | | ... + GPIO14 ---------------------| |--- PAD_GPIO14_W + GPIO15 ---------------------| |--- PAD_GPIO15_W + | | + ------------------ + + Alternatively, the "PAD_GPIOs" can be multiplexed to other peripherals through + function selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2. + Function 0 is the default function or peripheral signal of an iopad. + The function 1 and function 2 are other optional functions or peripheral signals + available to an iopad. The function selection can be carried out by writing the + function number to the iopad function select register. + + The "sys_west" domain has one PAD_GPIO bank - + W0 - 16 PAD_GPIOs (PAD_GPIO0_W to PAD_GPIO15_W) + + The PAD_GPIO bank can be set to voltage level 3.3V or 1.8V. All devices attached + to the PAD_GPIOs must use the same I/O voltage level as the bank voltage setting. + This allows user to select different I/O voltages for their devices. For instance, + the UART have 3.3V/1.8V requirement, the UART devices that use 1.8V are attached + to a PAD_GPIO bank which is configured to 1.8V. + + Regulator supplies voltage to the PAD_GPIO bank, and the PAD_GPIO bank has a + corresponding syscon bit [1:0] that must be configured to indicate its voltage + level. The default voltage setting of each PAD_GPIO bank is 3.3V. + + +--------+--------+-------------------+ + | Bit[1] | Bit[0] | Reference Voltage | + +--------+--------+-------------------+ + | 0 | 0 | 3.3 V | + +--------+--------+-------------------+ + | 1 | x | 1.8 V | + +--------+--------+-------------------+ + + Under any circumstances, the syscon register's reference voltage setting must not be + lower than the actual device voltage, otherwise, the device I/O pads will get damaged. + + Follow the guidelines below when configure reference voltage - + + To increase the device voltage, set bit [1:0] to the new operating state first before + raising the actual voltage to the higher operating point. + + To decrease the device voltage, hold bit [1:0] to the current operating state until + the actual voltage has stabilized at the lower operating point before changing the + setting. + + Alternatively, a device voltage change can always be initiated by first setting syscon + register bit [1:0] = 0, the safe 3.3V startup condition, before changing the device + voltage. Then once the actual voltage is changed and has stabilized at the new operating + point, bit [1:0] can be reset as appropriate. + +maintainers: + - Alex Soo + +properties: + compatible: + - items: + - const: starfive,jh8100-sys-pinctrl-west + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings or function select. + The GPIOMUX and PINMUX macros are used to configure the + I/O multiplexing and function selection respectively. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow (half frequency) + 1: fast + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - interrupt-controller + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_west: pinctrl@123e0000 { + compatible = "starfive,jh8100-sys-pinctrl-west", "syscon", "simple-mfd"; + reg = <0x0 0x123e0000 0x0 0x10000>; + clocks = <&syscrg_nw 6>; + resets = <&syscrg_nw 1>; + interrupts = <183>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_west 0 0 16>; + + smbus1_pins: smbus1-grp { + smbus1-scl-pins { + pinmux = <0x1014300d>; + bias-pull-up; + input-enable; + }; + + smbus1-sda-pins { + pinmux = <0x1115340c>; + bias-pull-up; + input-enable; + }; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h new file mode 100644 index 000000000000..153ba950c062 --- /dev/null +++ b/include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH8100_H__ + +/* Pad Slew Rates */ +#define PAD_SLEW_RATE_FAST 1 +#define PAD_SLEW_RATE_SLOW 0 + +#endif From patchwork Fri May 3 11:14:36 2024 Content-Type: text/plain; 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Signed-off-by: Alex Soo --- arch/riscv/boot/dts/starfive/jh8100-evb.dts | 7 + arch/riscv/boot/dts/starfive/jh8100-pinfunc.h | 504 ++++++++++++++++++ arch/riscv/boot/dts/starfive/jh8100.dtsi | 46 ++ 3 files changed, 557 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh8100-pinfunc.h diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts index c16bc25d8988..dde01ed35e3e 100644 --- a/arch/riscv/boot/dts/starfive/jh8100-evb.dts +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts @@ -4,6 +4,8 @@ */ #include "jh8100.dtsi" +#include "jh8100-pinfunc.h" +#include / { model = "StarFive JH8100 EVB"; @@ -26,3 +28,8 @@ memory@40000000 { &uart0 { status = "okay"; }; + +&pinctrl_aon { + wakeup-gpios = <&pinctrl_aon PAD_RGPIO1 GPIO_ACTIVE_HIGH>; + wakeup-source; +}; diff --git a/arch/riscv/boot/dts/starfive/jh8100-pinfunc.h b/arch/riscv/boot/dts/starfive/jh8100-pinfunc.h new file mode 100644 index 000000000000..0325338dee08 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100-pinfunc.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#ifndef __JH8100_PINFUNC_H__ +#define __JH8100_PINFUNC_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux_east pins */ +#define PAD_GPIO0_E 0 +#define PAD_GPIO1_E 1 +#define PAD_GPIO2_E 2 +#define PAD_GPIO3_E 3 +#define PAD_GPIO4_E 4 +#define PAD_GPIO5_E 5 +#define PAD_GPIO6_E 6 +#define PAD_GPIO7_E 7 +#define PAD_GPIO8_E 8 +#define PAD_GPIO9_E 9 +#define PAD_GPIO10_E 10 +#define PAD_GPIO11_E 11 +#define PAD_GPIO12_E 12 +#define PAD_GPIO13_E 13 +#define PAD_GPIO14_E 14 +#define PAD_GPIO15_E 15 +#define PAD_GPIO16_E 16 +#define PAD_GPIO17_E 17 +#define PAD_GPIO18_E 18 +#define PAD_GPIO19_E 19 +#define PAD_GPIO20_E 20 +#define PAD_GPIO21_E 21 +#define PAD_GPIO22_E 22 +#define PAD_GPIO23_E 23 +#define PAD_GPIO24_E 24 +#define PAD_GPIO25_E 25 +#define PAD_GPIO26_E 26 +#define PAD_GPIO27_E 27 +#define PAD_GPIO28_E 28 +#define PAD_GPIO29_E 29 +#define PAD_GPIO30_E 30 +#define PAD_GPIO31_E 31 +#define PAD_GPIO32_E 32 +#define PAD_GPIO33_E 33 +#define PAD_GPIO34_E 34 +#define PAD_GPIO35_E 35 +#define PAD_GPIO36_E 36 +#define PAD_GPIO37_E 37 +#define PAD_GPIO38_E 38 +#define PAD_GPIO39_E 39 +#define PAD_GPIO40_E 40 +#define PAD_GPIO41_E 41 +#define PAD_GPIO42_E 42 +#define PAD_GPIO43_E 43 +#define PAD_GPIO44_E 44 +#define PAD_GPIO45_E 45 +#define PAD_GPIO46_E 46 +#define PAD_GPIO47_E 47 + +/* sys_iomux_west pins */ +#define PAD_GPIO0_W 0 +#define PAD_GPIO1_W 1 +#define PAD_GPIO2_W 2 +#define PAD_GPIO3_W 3 +#define PAD_GPIO4_W 4 +#define PAD_GPIO5_W 5 +#define PAD_GPIO6_W 6 +#define PAD_GPIO7_W 7 +#define PAD_GPIO8_W 8 +#define PAD_GPIO9_W 9 +#define PAD_GPIO10_W 10 +#define PAD_GPIO11_W 11 +#define PAD_GPIO12_W 12 +#define PAD_GPIO13_W 13 +#define PAD_GPIO14_W 14 +#define PAD_GPIO15_W 15 + +/* aon_iomux pins */ +#define PAD_RGPIO0 0 +#define PAD_RGPIO1 1 +#define PAD_RGPIO2 2 +#define PAD_RGPIO3 3 +#define PAD_RGPIO4 4 +#define PAD_RGPIO5 5 +#define PAD_RGPIO6 6 +#define PAD_RGPIO7 7 +#define PAD_RGPIO8 8 +#define PAD_RGPIO9 9 +#define PAD_RGPIO10 10 +#define PAD_RGPIO11 11 +#define PAD_RGPIO12 12 +#define PAD_RGPIO13 13 +#define PAD_RGPIO14 14 +#define PAD_RGPIO15 15 + +/* sys_iomux_east dout */ +#define GPOUT_LOW 0 +#define GPOUT_HIGH 1 +#define GPOUT_SYS_CAN0_STBY 2 +#define GPOUT_SYS_CAN0_TST_NEXT_BIT 3 +#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 4 +#define GPOUT_SYS_CAN0_TXD 5 +#define GPOUT_SYS_I2C0_CLK 6 +#define GPOUT_SYS_I2C0_DATA 7 +#define GPOUT_SYS_I2S0_STEREO_RSCKO 8 +#define GPOUT_SYS_I2S0_STEREO_RWSO 9 +#define GPOUT_SYS_I2S0_STEREO_SDO_0 10 +#define GPOUT_SYS_I2S0_STEREO_SDO_1 11 +#define GPOUT_SYS_I2S0_STEREO_TSCKO 12 +#define GPOUT_SYS_I2S0_STEREO_TWSO 13 +#define GPOUT_SYS_SPI0_MO 14 +#define GPOUT_SYS_SPI0_SS0 15 +#define GPOUT_SYS_SPI0_SS1 16 +#define GPOUT_SYS_SPI0_SS2 17 +#define GPOUT_SYS_SPI0_SS3 18 +#define GPOUT_SYS_SPI0_SCLK 19 +#define GPOUT_SYS_SPI0_SO 20 +#define GPOUT_SYS_UART0_DTR 21 +#define GPOUT_SYS_UART0_RTS 22 +#define GPOUT_SYS_UART0_TX 23 +#define GPOUT_SYS_USB0_DBG_DRIVE_VBUS 24 +#define GPOUT_SYS_PDM_MCLK 25 +#define GPOUT_SYS_PWM_CHANNEL0 26 +#define GPOUT_SYS_PWM_CHANNEL1 27 +#define GPOUT_SYS_PWM_CHANNEL2 28 +#define GPOUT_SYS_PWM_CHANNEL3 29 +#define GPOUT_SYS_PWM_CHANNEL4 30 +#define GPOUT_SYS_PWM_CHANNEL5 31 +#define GPOUT_SYS_PWM_CHANNEL6 32 +#define GPOUT_SYS_PWM_CHANNEL7 33 +#define GPOUT_SYS_SMBUS0_CLK 34 +#define GPOUT_SYS_SMBUS0_DATA 35 +#define GPOUT_SYS_SMBUS0_SUSPEND 36 +#define GPOUT_SYS_CLK_GCLK1 37 +#define GPOUT_SYS_CLK_GCLK2 38 +#define GPOUT_SYS_CLK_GCLK3 39 +#define GPOUT_SYS_CLK_GCLK4 40 +#define GPOUT_SYS_CLK_GCLK6 41 +#define GPOUT_SYS_CLK_GCLK7 42 +#define GPOUT_SYS_MCLK 43 +#define GPOUT_SYS_USB0_TYPEC_DRIVE_VBUS 44 +#define GPOUT_SYS_WATCHDOG0_RESET 45 +#define GPOUT_SYS_CAN1_STBY 46 +#define GPOUT_SYS_CAN1_TST_NEXT_BIT 47 +#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 48 +#define GPOUT_SYS_CAN1_TXD 49 +#define GPOUT_SYS_I2C1_CLK 50 +#define GPOUT_SYS_I2C1_DATA 51 +#define GPOUT_SYS_I2S1_RSCKO 52 +#define GPOUT_SYS_I2S1_RWSO 53 +#define GPOUT_SYS_I2S1_SDO0 54 +#define GPOUT_SYS_I2S1_SDO1 55 +#define GPOUT_SYS_I2S1_SDO2 56 +#define GPOUT_SYS_I2S1_SDO3 57 +#define GPOUT_SYS_I2S1_SDO4 58 +#define GPOUT_SYS_I2S1_SDO5 59 +#define GPOUT_SYS_I2S1_SDO6 60 +#define GPOUT_SYS_I2S1_SDO7 61 +#define GPOUT_SYS_I2S1_TSCKO 62 +#define GPOUT_SYS_I2S1_TWSO 63 +#define GPOUT_SYS_SDIO1_PU_PD_DATA2 64 +#define GPOUT_SYS_SDIO1_BUS_POWER 65 +#define GPOUT_SYS_SDIO1_RESET 66 +#define GPOUT_SYS_SDIO1_BUS_VOLTAGE_0 67 +#define GPOUT_SYS_SDIO1_BUS_VOLTAGE_1 68 +#define GPOUT_SYS_SDIO1_BUS_VOLTAGE_2 69 +#define GPOUT_SYS_SDIO1_LED 70 +#define GPOUT_SYS_SPI1_MO 71 +#define GPOUT_SYS_SPI1_SS0 72 +#define GPOUT_SYS_SPI1_SS1 73 +#define GPOUT_SYS_SPI1_SS2 74 +#define GPOUT_SYS_SPI1_SS3 75 +#define GPOUT_SYS_SPI1_SCLK 76 +#define GPOUT_SYS_SPI1_SO 77 +#define GPOUT_SYS_UART1_DTR 78 +#define GPOUT_SYS_UART1_RTS 79 +#define GPOUT_SYS_UART1_TX 80 +#define GPOUT_SYS_USB1_DBG_DRIVE_VBUS 81 +#define GPOUT_SYS_I2C2_CLK 82 +#define GPOUT_SYS_I2C2_DATA 83 +#define GPOUT_SYS_UART2_DTR 84 +#define GPOUT_SYS_UART2_RTS 85 +#define GPOUT_SYS_UART2_TX 86 +#define GPOUT_SYS_USB2_DBG_DRIVE_VBUS 87 +#define GPOUT_SYS_I2C3_CLK 88 +#define GPOUT_SYS_I2C3_DATA 89 +#define GPOUT_SYS_UART3_DTR 90 +#define GPOUT_SYS_UART3_RTS 91 +#define GPOUT_SYS_UART3_TX 92 +#define GPOUT_SYS_USB3_DBG_DRIVE_VBUS 93 +#define GPOUT_SYS_I2C4_CLK 94 +#define GPOUT_SYS_I2C4_DATA 95 +#define GPOUT_SYS_UART4_DTR 96 +#define GPOUT_SYS_UART4_RTS 97 +#define GPOUT_SYS_UART4_TX 98 +#define GPOUT_SYS_I2C5_CLK 99 +#define GPOUT_SYS_I2C5_DATA 100 + +/* sys_iomux_west dout */ +#define GPOUT_SYS_RSVD0 2 +#define GPOUT_SYS_RSVD1 3 +#define GPOUT_SYS_RSVD2 4 +#define GPOUT_SYS_RSVD3 5 +#define GPOUT_SYS_RSVD4 6 +#define GPOUT_SYS_RSVD5 7 +#define GPOUT_SYS_RSVD6 8 +#define GPOUT_SYS_RSVD7 9 +#define GPOUT_SYS_RSVD8 10 +#define GPOUT_SYS_HD_AUDIO0_BCLK 11 +#define GPOUT_SYS_HD_AUDIO0_RST 12 +#define GPOUT_SYS_HD_AUDIO0_SDI0_O 13 +#define GPOUT_SYS_HD_AUDIO0_SDI1_O 14 +#define GPOUT_SYS_HD_AUDIO0_SDO0 15 +#define GPOUT_SYS_HD_AUDIO0_SDO1 16 +#define GPOUT_SYS_HD_AUDIO0_SYNC 17 +#define GPOUT_SYS_HIFI4_JTAG_TDO 18 +#define GPOUT_SYS_CLK_GCLK5 19 +#define GPOUT_SYS_SMBUS1_CLK 20 +#define GPOUT_SYS_SMBUS1_DATA 21 +#define GPOUT_SYS_SMBUS1_SUSPEND 22 +#define GPOUT_SYS_SPI2_MO 23 +#define GPOUT_SYS_SPI2_SS0 24 +#define GPOUT_SYS_SPI2_SS1 25 +#define GPOUT_SYS_SPI2_SS2 26 +#define GPOUT_SYS_SPI2_SS3 27 +#define GPOUT_SYS_SPI2_SCLK 28 +#define GPOUT_SYS_SPI2_SO 29 +#define GPOUT_SYS_UART5_DTR 30 +#define GPOUT_SYS_UART5_RTS 31 +#define GPOUT_SYS_UART5_TX 32 +#define GPOUT_SYS_I2C6_CLK 33 +#define GPOUT_SYS_I2C6_DATA 34 +#define GPOUT_SYS_UART6_DTR 35 +#define GPOUT_SYS_UART6_RTS 36 +#define GPOUT_SYS_UART6_TX 37 +#define GPOUT_SYS_I2C7_CLK 38 +#define GPOUT_SYS_I2C7_DATA 39 + +/* aon_iomux dout */ +#define GPOUT_AON_CLK_32K 2 +#define GPOUT_AON_CLK_GCLK0 3 +#define GPOUT_AON_CLK_GCLK_OSC 4 +#define GPOUT_AON_SIG_STUB_POWER_EN_O 5 +#define GPOUT_AON_EMMC_PU_PD_DATA2 6 +#define GPOUT_AON_EMMC_BUS_POWER 7 +#define GPOUT_AON_EMMC_BUS_VOLTAGE_0 8 +#define GPOUT_AON_EMMC_BUS_VOLTAGE_1 9 +#define GPOUT_AON_EMMC_BUS_VOLTAGE_2 10 +#define GPOUT_AON_EMMC_LED 11 +#define GPOUT_AON_SDIO0_PU_PD_DATA2 12 +#define GPOUT_AON_SDIO0_BUS_POWER 13 +#define GPOUT_AON_SDIO0_RESET 14 +#define GPOUT_AON_SDIO0_BUS_VOLTAGE_0 15 +#define GPOUT_AON_SDIO0_BUS_VOLTAGE_1 16 +#define GPOUT_AON_SDIO0_BUS_VOLTAGE_2 17 +#define GPOUT_AON_SDIO0_LED 18 +#define GPOUT_AON_JTAG_TDO 19 +#define GPOUT_AON_SCP_POWER_EN 20 +#define GPOUT_AON_WATCHDOG1_RESET 21 +#define GPOUT_AON_UART7_TX 22 +#define GPOUT_AON_I2C8_CLK 23 +#define GPOUT_AON_I2C8_DATA 24 + +/* sys_iomux_east doen */ +#define GPOEN_SYS_ENABLE 0 +#define GPOEN_SYS_DISABLE 1 +#define GPOEN_SYS_I2C0_CLK 2 +#define GPOEN_SYS_I2C0_DATA 3 +#define GPOEN_SYS_I2S0_STEREO_SDOE_0 4 +#define GPOEN_SYS_I2S0_STEREO_SDOE_1 5 +#define GPOEN_SYS_SPI0_N_MO_EN 6 +#define GPOEN_SYS_SPI0_N_SCLK_EN 7 +#define GPOEN_SYS_SPI0_N_SO_EN 8 +#define GPOEN_SYS_SPI0_N_SS_EN 9 +#define GPOEN_SYS_PWM_CHANNEL0 10 +#define GPOEN_SYS_PWM_CHANNEL1 11 +#define GPOEN_SYS_PWM_CHANNEL2 12 +#define GPOEN_SYS_PWM_CHANNEL3 13 +#define GPOEN_SYS_PWM_CHANNEL4 14 +#define GPOEN_SYS_PWM_CHANNEL5 15 +#define GPOEN_SYS_PWM_CHANNEL6 16 +#define GPOEN_SYS_PWM_CHANNEL7 17 +#define GPOEN_SYS_SMBUS0_CLK 18 +#define GPOEN_SYS_SMBUS0_DATA 19 +#define GPOEN_SYS_SMBUS0_ALERT 20 +#define GPOEN_SYS_I2C1_CLK 21 +#define GPOEN_SYS_I2C1_DATA 22 +#define GPOEN_SYS_I2S1_SDO0 23 +#define GPOEN_SYS_I2S1_SDO1 24 +#define GPOEN_SYS_I2S1_SDO2 25 +#define GPOEN_SYS_I2S1_SDO3 26 +#define GPOEN_SYS_I2S1_SDO4 27 +#define GPOEN_SYS_I2S1_SDO5 28 +#define GPOEN_SYS_I2S1_SDO6 29 +#define GPOEN_SYS_I2S1_SDO7 30 +#define GPOEN_SYS_SPI1_N_MO_EN 31 +#define GPOEN_SYS_SPI1_N_SCLK_EN 32 +#define GPOEN_SYS_SPI1_N_SO_EN 33 +#define GPOEN_SYS_SPI1_N_SS_EN 34 +#define GPOEN_SYS_I2C2_CLK 35 +#define GPOEN_SYS_I2C2_DATA 36 +#define GPOEN_SYS_I2C3_CLK 37 +#define GPOEN_SYS_I2C3_DATA 38 +#define GPOEN_SYS_I2C4_CLK 39 +#define GPOEN_SYS_I2C4_DATA 40 +#define GPOEN_SYS_I2C5_CLK 41 +#define GPOEN_SYS_I2C5_DATA 42 + +/* sys_iomux_west doen */ +#define GPOEN_SYS_RSVD0 2 +#define GPOEN_SYS_RSVD1 3 +#define GPOEN_SYS_RSVD2 4 +#define GPOEN_SYS_RSVD3 5 +#define GPOEN_SYS_RSVD4 6 +#define GPOEN_SYS_RSVD5 7 +#define GPOEN_SYS_RSVD6 8 +#define GPOEN_SYS_HD_AUDIO0_SDI0 9 +#define GPOEN_SYS_HD_AUDIO0_SDI1 10 +#define GPOEN_SYS_HIFI4_JTAG_TDO 11 +#define GPOEN_SYS_SMBUS1_CLK 12 +#define GPOEN_SYS_SMBUS1_DATA 13 +#define GPOEN_SYS_SMBUS1_ALERT 14 +#define GPOEN_SYS_SPI2_MO 15 +#define GPOEN_SYS_SPI2_SCLK 16 +#define GPOEN_SYS_SPI2_SO 17 +#define GPOEN_SYS_SPI2_SS 18 +#define GPOEN_SYS_I2C6_CLK 19 +#define GPOEN_SYS_I2C6_DATA 20 +#define GPOEN_SYS_I2C7_CLK 21 +#define GPOEN_SYS_I2C7_DATA 22 + +/* aon_iomux doen */ +#define GPOEN_AON_JTAG_TDO 2 +#define GPOEN_AON_I2C8_CLK 3 +#define GPOEN_AON_I2C8_DATA 4 + +/* sys_iomux din */ +#define GPI_NONE 255 + +/* sys_iomux_east din */ +#define GPI_SYS_CAN0_RXD 0 +#define GPI_SYS_I2C0_CLK 1 +#define GPI_SYS_I2C0_DATA 2 +#define GPI_SYS_SPI0_SCLK 3 +#define GPI_SYS_SPI0_MI 4 +#define GPI_SYS_SPI0_SS_N 5 +#define GPI_SYS_SPI0_SI 6 +#define GPI_SYS_UART0_CTS 7 +#define GPI_SYS_UART0_DCD 8 +#define GPI_SYS_UART0_DSR 9 +#define GPI_SYS_UART0_RI 10 +#define GPI_SYS_UART0_RX 11 +#define GPI_SYS_USB0_DBG_OVERCURRENT 12 +#define GPI_SYS_PDM_DMIC0 13 +#define GPI_SYS_PDM_DMIC1 14 +#define GPI_SYS_I2SRX0_SDIN0 15 +#define GPI_SYS_I2SRX0_SDIN1 16 +#define GPI_SYS_SMBUS0_CLK 17 +#define GPI_SYS_SMBUS0_DATA 18 +#define GPI_SYS_SMBUS0_ALERT 19 +#define GPI_SYS_JTAG_TCK 20 +#define GPI_SYS_MCLK_EXT 21 +#define GPI_SYS_I2SRX0_BCLK 22 +#define GPI_SYS_I2SRX0_LRCK 23 +#define GPI_SYS_I2STX0_BCLK 24 +#define GPI_SYS_I2STX0_LRCK 25 +#define GPI_SYS_SPI0_SCLK_IN0 26 +#define GPI_SYS_SPI0_SCLK_IN1 27 +#define GPI_SYS_I2S0_STEREO_RX_BCLK 28 +#define GPI_SYS_I2S0_STEREO_RX_LRCK 29 +#define GPI_SYS_I2S0_STEREO_TX_BCLK 30 +#define GPI_SYS_I2S0_STEREO_TX_LRCK 31 +#define GPI_SYS_I2S1_RX_BCLK 32 +#define GPI_SYS_I2S1_RX_LRCK 33 +#define GPI_SYS_I2S1_TX_BCLK 34 +#define GPI_SYS_I2S1_TX_LRCK 35 +#define GPI_SYS_USB0_TYPEC_OVERCURRENT 36 +#define GPI_SYS_CAN1_RXD 37 +#define GPI_SYS_I2C1_CLK 38 +#define GPI_SYS_I2C1_DATA 39 +#define GPI_SYS_I2S1_SDI_0 40 +#define GPI_SYS_I2S1_SDI_1 41 +#define GPI_SYS_I2S1_SDI_2 42 +#define GPI_SYS_I2S1_SDI_3 43 +#define GPI_SYS_I2S1_SDI_4 44 +#define GPI_SYS_I2S1_SDI_5 45 +#define GPI_SYS_I2S1_SDI_6 46 +#define GPI_SYS_I2S1_SDI_7 47 +#define GPI_SYS_SDIO1_CARD_DETECT 48 +#define GPI_SYS_SDIO1_WRITE_PROTECT 49 +#define GPI_SYS_SPI1_EXT_CLK 50 +#define GPI_SYS_SPI1_MI 51 +#define GPI_SYS_SPI1_SS_IN 52 +#define GPI_SYS_SPI1_SI 53 +#define GPI_SYS_UART1_CTS 54 +#define GPI_SYS_UART1_DCD 55 +#define GPI_SYS_UART1_DSR 56 +#define GPI_SYS_UART1_RI 57 +#define GPI_SYS_UART1_RX 58 +#define GPI_SYS_USB1_DBG_OVERCURRENT 59 +#define GPI_SYS_I2C2_CLK 60 +#define GPI_SYS_I2C2_DATA 61 +#define GPI_SYS_UART2_CTS 62 +#define GPI_SYS_UART2_DCD 63 +#define GPI_SYS_UART2_DSR 64 +#define GPI_SYS_UART2_RI 65 +#define GPI_SYS_UART2_RX 66 +#define GPI_SYS_USB2_DBG_OVERCURRENT 67 +#define GPI_SYS_I2C3_CLK 68 +#define GPI_SYS_I2C3_DATA 69 +#define GPI_SYS_UART3_CTS 70 +#define GPI_SYS_UART3_DCD 71 +#define GPI_SYS_UART3_DSR 72 +#define GPI_SYS_UART3_RI 73 +#define GPI_SYS_UART3_RX 74 +#define GPI_SYS_USB3_DBG_OVERCURRENT 75 +#define GPI_SYS_I2C4_CLK 76 +#define GPI_SYS_I2C4_DATA 77 +#define GPI_SYS_UART4_CTS 78 +#define GPI_SYS_UART4_DCD 79 +#define GPI_SYS_UART4_DSR 80 +#define GPI_SYS_UART4_RI 81 +#define GPI_SYS_UART4_RX 82 +#define GPI_SYS_I2C5_CLK 83 +#define GPI_SYS_I2C5_DATA 84 + +/* sys_iomux_west din */ +#define GPI_SYS_RSVD0 0 +#define GPI_SYS_RSVD1 1 +#define GPI_SYS_RSVD2 2 +#define GPI_SYS_RSVD3 3 +#define GPI_SYS_RSVD4 4 +#define GPI_SYS_RSVD5 5 +#define GPI_SYS_RSVD6 6 +#define GPI_SYS_HD_AUDIO0_SDI0_I 7 +#define GPI_SYS_HD_AUDIO0_SDI1_I 8 +#define GPI_SYS_HIFI4_JTAG_TDI 9 +#define GPI_SYS_HIFI4_JTAG_TMS 10 +#define GPI_SYS_HIFI4_JTAG_RST 11 +#define GPI_SYS_RSVD7 12 +#define GPI_SYS_HIFI4_JTAG_TCK 13 +#define GPI_SYS_RSVD8 14 +#define GPI_SYS_SPI0_SCLK_IN2 15 +#define GPI_SYS_SMBUS1_CLK 16 +#define GPI_SYS_SMBUS1_DATA 17 +#define GPI_SYS_SMBUS1_ALERT 18 +#define GPI_SYS_SPI2_EXT_CLK 19 +#define GPI_SYS_SPI2_MI 20 +#define GPI_SYS_SPI2_SS_IN 21 +#define GPI_SYS_SPI2_SI 22 +#define GPI_SYS_UART5_CTS 23 +#define GPI_SYS_UART5_DCD 24 +#define GPI_SYS_UART5_DSR 25 +#define GPI_SYS_UART5_RI 26 +#define GPI_SYS_UART5_RX 27 +#define GPI_SYS_I2C6_CLK 28 +#define GPI_SYS_I2C6_DATA 29 +#define GPI_SYS_UART6_CTS 30 +#define GPI_SYS_UART6_DCD 31 +#define GPI_SYS_UART6_DSR 32 +#define GPI_SYS_UART6_RI 33 +#define GPI_SYS_UART6_RX 34 +#define GPI_SYS_I2C7_CLK 35 +#define GPI_SYS_I2C7_DATA 36 + +/* aon_iomux din */ +#define GPI_AON_JTAG_TCK 0 +#define GPI_AON_SIG_STUB_RESERVED_0 1 +#define GPI_AON_SIG_STUB_RESERVED_1 2 +#define GPI_AON_SIG_STUB_RESERVED_2 3 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_0 4 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_1 5 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_2 6 +#define GPI_AON_XSPI0_GP_OPEN_DRAIN_3 7 +#define GPI_AON_SDIO0_CARD_DETECTION 8 +#define GPI_AON_SDIO0_WRITE_PROTECTION 9 +#define GPI_AON_SRC_BUF_JTAG_RST 10 +#define GPI_AON_JTAG_TDI 11 +#define GPI_AON_JTAG_TMS 12 +#define GPI_AON_UART7_RX 13 +#define GPI_AON_I2C8_CLK 14 +#define GPI_AON_I2C8_DATA 15 + +#endif diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi index 5ba826e38ead..37251010d96f 100644 --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include / { @@ -563,6 +564,19 @@ uart4: serial@121a0000 { status = "disabled"; }; + pinctrl_east: pinctrl@122d0000 { + compatible = "starfive,jh8100-sys-pinctrl-east", + "syscon", "simple-mfd"; + reg = <0x0 0x122d0000 0x0 0x10000>; + clocks = <&necrg JH8100_NECLK_IOMUX_EAST_PCLK>; + resets = <&necrg JH8100_NERST_SYS_IOMUX_E>; + interrupts = <182>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_east 0 0 48>; + }; + necrg: clock-controller@12320000 { compatible = "starfive,jh8100-necrg"; reg = <0x0 0x12320000 0x0 0x10000>; @@ -634,6 +648,19 @@ nwcrg: clock-controller@123c0000 { #reset-cells = <1>; }; + pinctrl_west: pinctrl@123e0000 { + compatible = "starfive,jh8100-sys-pinctrl-west", + "syscon", "simple-mfd"; + reg = <0x0 0x123e0000 0x0 0x10000>; + clocks = <&nwcrg JH8100_NWCLK_IOMUX_WEST_PCLK>; + resets = <&nwcrg JH8100_NWRST_SYS_IOMUX_W>; + interrupts = <183>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_west 0 0 16>; + }; + syscrg: clock-controller@126d0000 { compatible = "starfive,jh8100-syscrg"; reg = <0x0 0x126d0000 0x0 0x10000>; @@ -656,6 +683,13 @@ swcrg: clock-controller@12720000 { #reset-cells = <1>; }; + pinctrl_gmac: pinctrl@12770000 { + compatible = "starfive,jh8100-sys-pinctrl-gmac", + "syscon", "simple-mfd"; + status = "disabled"; + reg = <0x0 0x12770000 0x0 0x10000>; + }; + uart5: serial@127d0000 { compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; reg = <0x0 0x127d0000 0x0 0x10000>; @@ -674,6 +708,18 @@ uart6: serial@127e0000 { status = "disabled"; }; + pinctrl_aon: pinctrl@1f300000 { + compatible = "starfive,jh8100-aon-pinctrl", + "syscon", "simple-mfd"; + reg = <0x0 0x1f300000 0x0 0x10000>; + resets = <&aoncrg JH8100_AONRST_AON_IOMUX_PRESETN>; + interrupts = <160>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aon 0 0 16>; + }; + aoncrg: clock-controller@1f310000 { compatible = "starfive,jh8100-aoncrg"; reg = <0x0 0x1f310000 0x0 0x10000>;