From patchwork Thu May 2 13:16:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Day X-Patchwork-Id: 1930622 X-Patchwork-Delegate: caleb.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=samcday.com header.i=@samcday.com header.a=rsa-sha256 header.s=protonmail2 header.b=CqRCWEe1; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VVZLH3V5dz1ydT for ; Thu, 2 May 2024 23:20:23 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E4FED88D00; Thu, 2 May 2024 15:18:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=samcday.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; secure) header.d=samcday.com header.i=@samcday.com header.b="CqRCWEe1"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8B5BC88378; Thu, 2 May 2024 15:17:08 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-40136.proton.ch (mail-40136.proton.ch [185.70.40.136]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9DA9788361 for ; Thu, 2 May 2024 15:17:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=samcday.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=me@samcday.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samcday.com; s=protonmail2; t=1714655826; x=1714915026; bh=mdAk5izBOY//fJ4gA5Fsm8JLte41MXOgZ6EHx/UHDvo=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=CqRCWEe1GFHEZiICtTSA7hxVpx4vZer8dywvLtwZzgRjB6nJo/i/nTHHA/KNCDPyE Oq/FaM6Npk/kXTCErMD1CSCR2YExZ5S/AHqpMBJI08IXhquv3zTdLpq0YUHmlbciIZ 3o8LRqMhYVBt0Al45i6GQZL00vvbWWnJ9nKfmwU9tHpXkI9h0k8Azi1cfGsl/nYhwc 9+YZdziw1F3WwAjOUPBWMZWSyycJaN9LIhUD4ccKwwR+L2peWwdS7Hxx9Mlv8LhwET Hy9kG4VjNsThuwEs7bhJlviXYxFH6FCHvhgSzT8w/KgzvhJAVUahMw0tKJ0LgTTSJI qmf42b7Nvcidg== Date: Thu, 02 May 2024 13:16:52 +0000 To: u-boot@lists.denx.de From: Sam Day Cc: Caleb Connolly , Sam Day Subject: [PATCH 1/2] clk/qcom: apq8016: add support for USB_HS clocks Message-ID: <20240502-msm8916-hs-usb-clocks-v1-1-eeccf483b68d@samcday.com> In-Reply-To: <20240502-msm8916-hs-usb-clocks-v1-0-eeccf483b68d@samcday.com> References: <20240502-msm8916-hs-usb-clocks-v1-0-eeccf483b68d@samcday.com> Feedback-ID: 25366008:user:proton X-Pm-Message-ID: a382db0c1549b186093a3790eb84841eec136301 MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 02 May 2024 15:18:08 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The newer "register map for simple gate clocks" support added for qcom clocks is used. As a result gcc_apq8016 now has a mixture of the old and new styles. I didn't (and still don't!) feel comfortable enough in this area to update the existing code. Some groundwork was also laid to dump the state of these gate clocks with the recently-added qcom dump callbacks. Signed-off-by: Sam Day --- drivers/clk/qcom/clock-apq8016.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index d3b63b9c1a..745371a289 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -17,6 +17,8 @@ #include "clock-qcom.h" +#define USB_HS_SYSTEM_CLK_CMD_RCGR 0x41010 + /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) #define APCS_GPLL_ENA_VOTE (0x45000) @@ -39,6 +41,11 @@ /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { + F(80000000, CFG_CLK_SRC_GPLL0, 10, 0, 0), + { } +}; + static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -52,6 +59,11 @@ static struct vote_clk gcc_blsp1_ahb_clk = { .vote_bit = BIT(10), }; +static const struct gate_clk apq8016_clks[] = { + GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, 0x00000001), + GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, 0x00000001), +}; + /* SDHCI */ static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { @@ -106,6 +118,7 @@ int apq8016_clk_init_uart(phys_addr_t base, unsigned long id) static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) { + const struct freq_tbl *freq; struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { @@ -117,13 +130,31 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ apq8016_clk_init_uart(priv->base, clk->id); return 7372800; + case GCC_USB_HS_SYSTEM_CLK: + freq = qcom_find_freq(ftbl_gcc_usb_hs_system_clk, rate); + clk_rcg_set_rate_mnd(priv->base, USB_HS_SYSTEM_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 0); + return freq->freq; default: return 0; } } +static int apq8016_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name); + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + static struct msm_clk_data apq8016_clk_data = { .set_rate = apq8016_clk_set_rate, + .clks = apq8016_clks, + .num_clks = ARRAY_SIZE(apq8016_clks), + .enable = apq8016_clk_enable, }; static const struct udevice_id gcc_apq8016_of_match[] = { From patchwork Thu May 2 13:16:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Day X-Patchwork-Id: 1930621 X-Patchwork-Delegate: caleb.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=samcday.com header.i=@samcday.com header.a=rsa-sha256 header.s=protonmail2 header.b=b8RZswNg; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VVZL31K6Jz1ydX for ; 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Thu, 2 May 2024 15:17:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=samcday.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=me@samcday.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samcday.com; s=protonmail2; t=1714655820; x=1714915020; bh=3YbdD02ZW+uU9zMq1XEaGgLD4yuMdKyFIu7h82jJnbU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=b8RZswNgPSPsAhT2VzBoTHkR50Mr4AQMIa+LukWYZ+f0IuDIo2z3iMcJeqno6Tp9F YkH6kLujzLV6+EJ7GO0wynnjgc3iAzG1VTa7WqzA0atBMP3vmIJJWNvGpEdhys2Yl2 K3Y7Hs4w6sUSgG1UzusMvr76rSpL1UQ7onEcVBHJEnrjBYLwEpoi+d9hwE22YSGr92 ewynrJn65WL0A01mFaZ0m111Bb/9y7D18vl4JI42HV6DXPS+oMVtU4dW/AA3N8k7nR YUH7qaQnKdTI4WZXHBfAYIkYPoaJo+/cz5FStWRPjDN4DkKemNK02TLe5CvP3uu7ba +gXGqIB5fb3JQ== Date: Thu, 02 May 2024 13:16:56 +0000 To: u-boot@lists.denx.de From: Sam Day Cc: Caleb Connolly , Sam Day Subject: [PATCH 2/2] ehci: msm: bring up iface + core clocks Message-ID: <20240502-msm8916-hs-usb-clocks-v1-2-eeccf483b68d@samcday.com> In-Reply-To: <20240502-msm8916-hs-usb-clocks-v1-0-eeccf483b68d@samcday.com> References: <20240502-msm8916-hs-usb-clocks-v1-0-eeccf483b68d@samcday.com> Feedback-ID: 25366008:user:proton X-Pm-Message-ID: 0e8f8177985e24a0bec8d6eb63c697d924d6e113 MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 02 May 2024 15:18:08 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This seems to be necessary on my samsung-a5. Without this patch, the first access of EHCI registers causes a bus stall and subsequent reset. I am unsure why this wasn't already necessary for db410c, perhaps those clocks are already enabled on boot. Signed-off-by: Sam Day Reviewed-by: Caleb Connolly --- drivers/usb/host/ehci-msm.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index 98fe7bc3bc..b2e294dd64 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -7,8 +7,10 @@ * Based on Linux driver */ +#include #include #include +#include #include #include #include @@ -25,6 +27,8 @@ struct msm_ehci_priv { struct usb_ehci *ehci; /* Start of IP core*/ struct ulpi_viewport ulpi_vp; /* ULPI Viewport */ struct phy phy; + struct clk iface_clk; + struct clk core_clk; }; static int msm_init_after_reset(struct ehci_ctrl *dev) @@ -53,20 +57,46 @@ static int ehci_usb_probe(struct udevice *dev) struct ehci_hcor *hcor; int ret; + ret = clk_get_by_name(dev, "core", &p->core_clk); + if (ret) { + dev_err(dev, "Failed to get core clock: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "iface", &p->iface_clk); + if (ret) { + dev_err(dev, "Failed to get iface clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(&p->core_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(&p->iface_clk); + if (ret) + goto cleanup_core; + hccr = (struct ehci_hccr *)((phys_addr_t)&ehci->caplength); hcor = (struct ehci_hcor *)((phys_addr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); ret = generic_setup_phy(dev, &p->phy, 0); if (ret) - return ret; + goto cleanup_iface; ret = board_usb_init(0, plat->init_type); if (ret < 0) - return ret; + goto cleanup_iface; return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0, plat->init_type); + +cleanup_iface: + clk_disable_unprepare(&p->iface_clk); +cleanup_core: + clk_disable_unprepare(&p->core_clk); + return ret; } static int ehci_usb_remove(struct udevice *dev) @@ -82,6 +112,9 @@ static int ehci_usb_remove(struct udevice *dev) /* Stop controller. */ clrbits_le32(&ehci->usbcmd, CMD_RUN); + clk_disable_unprepare(&p->iface_clk); + clk_disable_unprepare(&p->core_clk); + ret = generic_shutdown_phy(&p->phy); if (ret) return ret;