From patchwork Tue Apr 30 07:17:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1929336 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Hu4/5eHd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VTBNl4fXSz20fY for ; Tue, 30 Apr 2024 17:17:43 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D2E60384AB48 for ; Tue, 30 Apr 2024 07:17:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by sourceware.org (Postfix) with ESMTPS id CC78C3858D35 for ; Tue, 30 Apr 2024 07:17:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CC78C3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CC78C3858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714461443; cv=none; b=XDaFuC3GZrdOvRLN6vNEpkTGNpoF76Vkq9ZtlWyHNAs30v+EqsSIF7J+fzvJGYTJY6r8Aa4ziUEuw2Nx/6owvwX09gc+pcrLOYxly/N3KsKBIqBi+affQUnBFah2oc1OSIHSCRjyaYJ/moIGJb0h14BgADPUF4RAYeTnvf7cJAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714461443; c=relaxed/simple; bh=L7ED21L9J+7q/zBlxXOM1Sx4RyS73Gvl/xg764kBWxo=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=C4qnZOVI4LZNSnpU53CSQLPlSojBj7ylw4pw24+gu1I10gKYiGj+apUMGGqfx9M+MbyqQ76w1ZWeyFhukCxXZo063rtQHOnMYUMETDc57AKnDVqMwmmQIyLTxw6xiNrz9B8xqCKkKPoSeg6TBIgFpGURRuZIQtv+bXI8SPyu9G8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714461443; x=1745997443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L7ED21L9J+7q/zBlxXOM1Sx4RyS73Gvl/xg764kBWxo=; b=Hu4/5eHdwqBoJY2SW+3KwnbWBk407XlnoD9gyIBaw9cv724z1UxTdJEa CnmHRSc9hTVI6hlf2W8bT41tZdwVzzy6scDB1Qf7jucWwR37Tu3ZeM/VT PZC7asm3bdz9Le9dheG7pXaO2YTgGFk0nN0iQQdXqc9UJnrhGI/UydD93 L9Zv6lnuCrcb4XcZhc4Kqwu1Ioy0O7ODDv6JU6tZHkeobNQ3lMEGkWajw EaP024EtpfIgEZS4E+iOcx4IjZKuEgwya/Ir+1pjHgRCMGslqI+qoMoI0 QBz2h0N6eScdyASIFPVYGUaRqCJvbTC62u7cAqbRkXaLoD/n7mJALT3UE w==; X-CSE-ConnectionGUID: zKL1wdJETZOf3ice5dJ8zg== X-CSE-MsgGUID: nRtCMQLrTHKX25oG0ZDt9w== X-IronPort-AV: E=McAfee;i="6600,9927,11059"; a="9982754" X-IronPort-AV: E=Sophos;i="6.07,241,1708416000"; d="scan'208";a="9982754" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 00:17:21 -0700 X-CSE-ConnectionGUID: rwDYe82IRWGHM4uXlmj25g== X-CSE-MsgGUID: /c84JcFFSxKNg/3cPj95KQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,241,1708416000"; d="scan'208";a="26308678" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa009.fm.intel.com with ESMTP; 30 Apr 2024 00:17:18 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 9FFD51005681; Tue, 30 Apr 2024 15:17:17 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, Hongtao.Liu@intel.com, richard.guenther@gmail.com, Pan Li Subject: [PATCH v3] DSE: Fix ICE after allow vector type in get_stored_val Date: Tue, 30 Apr 2024 15:17:15 +0800 Message-Id: <20240430071715.3391799-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240226032558.587912-1-pan2.li@intel.com> References: <20240226032558.587912-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li We allowed vector type for get_stored_val when read is less than or equal to store in previous. Unfortunately, the valididate_subreg treats the vector type's size is less than vector register as invalid. Then we will have ICE here. This patch would like to fix it by filter-out the invalid type size, and make sure the subreg is valid for both the read_mode and store_mode before perform the real gen_lowpart. The below test suites are passed for this patch: * The x86 bootstrap test. * The x86 regression test. * The riscv rv64gcv regression test. * The riscv rv64gc regression test. * The aarch64 regression test. gcc/ChangeLog: * dse.cc (get_stored_val): Make sure read_mode size is greater than or equal to the vector register size before gen_lowpart. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111720-10.c: Adjust asm checker. * gcc.target/riscv/rvv/base/bug-6.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/dse.cc | 4 +++- .../gcc.target/riscv/rvv/base/bug-6.c | 22 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-10.c | 2 +- 3 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c diff --git a/gcc/dse.cc b/gcc/dse.cc index edc7a1dfecf..258d2ccc299 100644 --- a/gcc/dse.cc +++ b/gcc/dse.cc @@ -1946,7 +1946,9 @@ get_stored_val (store_info *store_info, machine_mode read_mode, copy_rtx (store_info->const_rhs)); else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) - && targetm.modes_tieable_p (read_mode, store_mode)) + && targetm.modes_tieable_p (read_mode, store_mode) + /* It's invalid in validate_subreg if read_mode size is < reg natural. */ + && known_ge (GET_MODE_SIZE (read_mode), REGMODE_NATURAL_SIZE (read_mode))) read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); else read_reg = extract_low_bits (read_mode, store_mode, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c new file mode 100644 index 00000000000..5bb00b8f587 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c @@ -0,0 +1,22 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize" } */ + +struct A { float x, y; }; +struct B { struct A u; }; + +extern void bar (struct A *); + +float +f3 (struct B *x, int y) +{ + struct A p = {1.0f, 2.0f}; + struct A *q = &x[y].u; + + __builtin_memcpy (&q->x, &p.x, sizeof (float)); + __builtin_memcpy (&q->y, &p.y, sizeof (float)); + + bar (&p); + + return x[y].u.x + x[y].u.y; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c index 215eb99ce0f..ee6b2ccf7ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c @@ -15,4 +15,4 @@ vbool4_t test () { } /* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ -/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */