From patchwork Fri Apr 12 03:32:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Zeng X-Patchwork-Id: 1922824 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VG28P2SQsz1yYM for ; Fri, 12 Apr 2024 13:28:21 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 66D45385840C for ; Fri, 12 Apr 2024 03:28:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from sgoci-sdnproxy-4.icoremail.net (sgoci-sdnproxy-4.icoremail.net [129.150.39.64]) by sourceware.org (Postfix) with ESMTP id DF5BC3858D33 for ; Fri, 12 Apr 2024 03:27:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DF5BC3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DF5BC3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=129.150.39.64 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712892481; cv=none; b=Ef8E4ysUgTHDwp4NYKKRaohpuMj5MgaZDStCD+hqBO5NUleG6zCfQqi/VWlEAdTZ43qBxtXZPs5ydcODN5FeCvtmbiPaZtRj9hhKs1cf9aufm+KRzw0brFad48SFXM6hxcRjjYeHSBHZdRzc55sekNQpzhE9JAvzfL6/N12DJSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712892481; c=relaxed/simple; bh=QsjBwrIiu0Kzzg/CEO09xI6/BZ/9pCKabQ2EHm+bYXQ=; h=From:To:Subject:Date:Message-Id; b=ST/t3bzwFHd3f86qFcnsUOtxxppgFi2tTvc5naoxrlAg76W4AmsxerA2cb1wEpd0UkLqu3rsEdOS+umxq+ud/FxUb278IR8e5nJH3iYjD7b90AzmF5/rDX20YkHgZ5rB1ztnFXYAFMP/R4OdaTG79iNO3bWP0EKUXSdbGwWO8zY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.38]) by app1 (Coremail) with SMTP id TAJkCgCnSOX1qRhmzzMGAA--.49614S4; Fri, 12 Apr 2024 11:26:46 +0800 (CST) From: Xiao Zeng To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, research_trasio@irq.a4lg.com, kito.cheng@gmail.com, palmer@dabbelt.com, zhengyu@eswincomputing.com, Xiao Zeng Subject: [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option Date: Fri, 12 Apr 2024 11:32:39 +0800 Message-Id: <20240412033239.77071-1-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TAJkCgCnSOX1qRhmzzMGAA--.49614S4 X-Coremail-Antispam: 1UD129KBjvJXoW3XFW8CFW7try5uFWrXF4UCFg_yoWxJFWDpF 45G39YkrWrXas7Wa4fta48Zw15JwsYgr43Aws7u34xA3y3J3yxJF1kK3W3AFZ8XF4Y9rya 9w4I9r1Yvr10g37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_VALIDITY_RPBL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch would like to add new sub extension (aka Zfbfmin) to the -march= option. It introduces a new data type BF16. 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. You can locate more information about Zfbfmin from below spec doc. Below test are passed for this patch * The riscv fully regression test. --- gcc/common/config/riscv/riscv-common.cc | 3 ++ gcc/config/riscv/riscv.opt | 2 + gcc/testsuite/gcc.target/riscv/arch-35.c | 5 +++ gcc/testsuite/gcc.target/riscv/arch-36.c | 5 +++ gcc/testsuite/gcc.target/riscv/predef-34.c | 47 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-35.c | 47 ++++++++++++++++++++++ 6 files changed, 109 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-36.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-35.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 43b7549e3ec..49c4783eaf2 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -155,6 +155,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zvksed", "zve32x"}, {"zvksh", "zve32x"}, + {"zfbfmin", "zfhmin"}, {"zfh", "zfhmin"}, {"zfhmin", "f"}, @@ -331,6 +332,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1698,6 +1700,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, + {"zfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZFBFMIN}, {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN}, diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 8da0764eb4b..5c96e951d45 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -393,6 +393,8 @@ Mask(ZICBOP) Var(riscv_zicmo_subext) TargetVariable int riscv_zf_subext +Mask(ZFBFMIN) Var(riscv_zf_subext) + Mask(ZFHMIN) Var(riscv_zf_subext) Mask(ZFH) Var(riscv_zf_subext) diff --git a/gcc/testsuite/gcc.target/riscv/arch-35.c b/gcc/testsuite/gcc.target/riscv/arch-35.c new file mode 100644 index 00000000000..6c783769666 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-35.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-36.c b/gcc/testsuite/gcc.target/riscv/arch-36.c new file mode 100644 index 00000000000..cbdccf12807 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-36.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-34.c b/gcc/testsuite/gcc.target/riscv/predef-34.c new file mode 100644 index 00000000000..0a993271f7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-34.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32i_zfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 32 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_zfhmin) +#error "__riscv_zfhmin" +#endif + +#if !defined(__riscv_zfbfmin) +#error "__riscv_zfbfmin" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-35.c b/gcc/testsuite/gcc.target/riscv/predef-35.c new file mode 100644 index 00000000000..76b328a8932 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-35.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64i_zfbfmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_zfhmin) +#error "__riscv_zfhmin" +#endif + +#if !defined(__riscv_zfbfmin) +#error "__riscv_zfbfmin" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + + return 0; +}