From patchwork Sun Feb 4 20:53:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1895044 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.a=rsa-sha256 header.s=fe-e1b5cab7be header.b=ua4hc2vg; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TShZG07Tzz1yhq for ; Mon, 5 Feb 2024 07:53:58 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B328487C2B; Sun, 4 Feb 2024 21:53:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.b="ua4hc2vg"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 957BE87BA8; Sun, 4 Feb 2024 21:53:41 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from smtp.forwardemail.net (smtp.forwardemail.net [149.28.215.223]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D31A687C3E for ; Sun, 4 Feb 2024 21:53:38 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=cbd4=JO=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1707080003; bh=R42VwSVQ1JTeZMBoCE5Ky2ToQxF1K4ax5bpRIJ/qlaI=; b=ua4hc2vgRItwLpVIgewh1u7NnH5I9/xuyiZdQ45y21cAbSgndUjlq/axU/xgMJY+xd4ga9QtX 4fJIi8dnPZ1b0l0sUMT64B55IbALH+J2otoGHyrLQIwEsDOo8jR0j34UFYunMWMs8Vrm6VAE4RJ +q+vSmc2DDzHvRxO9pR4GAfEhEFmKk42UxIjhLKQSwgaUlTKLnq0tgt8xbtO1DfRNs/bVKW90iv p+aW7lVA49VY8dKzDHW5npGaSsSgYuzAcM1ydgadayxPnFnp5Ul7DGsZRQfhhx0ESa+j2dVjEuH jSRNxnMOufNVJ9Pk/33Cov1uuoX+2GwV869J0uIbojCQ== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Nicolas Frattaroli , Jonas Karlman , Tom Rini , Jagan Teki , Andy Yan , Tianling Shen , Akash Gajjar , Eugen Hristev , Joshua Riek Cc: Quentin Schulz , Weizhao Ouyang , u-boot@lists.denx.de Subject: [PATCH v2 1/3] rockchip: rk35xx: Remove use of eMMC DDR52 mode Date: Sun, 4 Feb 2024 20:53:05 +0000 Message-ID: <20240204205312.2342868-2-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240204205312.2342868-1-jonas@kwiboo.se> References: <20240204205312.2342868-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65bff9426f7b756870de38f3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Testing has shown that writing to eMMC using DDR52 mode does not seem to work on RK356x and RK3588 boards. A simple test of writing a single block to e.g. sector 0x4000 fails: # Rescan using DDR52 mode => mmc rescan 4 # Write a single block to sector 0x4000 fails with ERROR => mmc write 20000000 4000 1 With the MMC_SPEED_MODE_SET Kconfig option enabled. Fix this by removing the mmc-ddr-1_8v prop from sdhci nodes in affected board u-boot.dtsi files. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Weizhao Ouyang Reviewed-by: Quentin Schulz --- Changes in v2: - Update commit message Link to v1: https://patchwork.ozlabs.org/patch/1891695/ --- arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 1 - arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 1 - arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 1 - arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 1 - arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi | 1 - arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 1 - arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 1 - arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 1 - arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 1 - arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 1 - arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi | 1 - arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 1 - 12 files changed, 12 deletions(-) diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi index 11976fd3a6e0..930d660868bb 100644 --- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -8,7 +8,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi index 8de9d1535efb..c235b4357f7d 100644 --- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi @@ -4,7 +4,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index 158f652cb3b1..e0e501deccfe 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -7,5 +7,4 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; }; diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi index f65f4067f3e9..5e46a2422d60 100644 --- a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi +++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi @@ -4,7 +4,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi index a44ac35bdacd..1597473017ed 100644 --- a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi @@ -8,7 +8,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi index 62f572c4cf9f..64c43374c042 100644 --- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -14,7 +14,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi index ecba91aa30f5..1fc71faa9e07 100644 --- a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi +++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi @@ -8,7 +8,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi index caf524443079..74755a44eaee 100644 --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -16,7 +16,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 46ebb77283f1..5b823fcca5fb 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -20,7 +20,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index e99e60185ebe..9ee9dd051e32 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -31,7 +31,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi index 471508a9ed74..ca2a684f3541 100644 --- a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi +++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi @@ -8,7 +8,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index 9a6a353088df..efba0c359ba5 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -7,6 +7,5 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; From patchwork Sun Feb 4 20:53:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1895043 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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spf=pass smtp.mailfrom=SRS0=cbd4=JO=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1707080007; bh=U+GMoqw9ptejZOFFHgbazJ899EReGQUy0CqItWLAVNQ=; b=HRWfGHqQSUxg2mHPW01FTDid3wkKKO4jdHN/vyQsC9cn201DTkKSsC8H3hTGJDUT3AoFevqYe ARtmOFaZmGY/i7q6SKC5re3LGK9vZnOy3LHWc/AIzVbEMugQGgc6ckEvPN7Ca6njPjcl7Zic8xS fy3MNgurG3GiUAGLHBzBKqsbCHneZzhp4bPPJYdh6SmdHlvQiclasJBhZUFU42dhtTMfM9RK05u aVtxe+7cjrmyaXLy3pTsZlQu8sRrIykHofNL6Vuh5ewg0D9OIy62PiN2tJ1XwIUZnc93jYjAK8U 8tB7fL2758oIhykKwO5BP00fnnSg/15zfDcnNpr78pbg== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Tianling Shen , Jonas Karlman Cc: Eugen Hristev , Quentin Schulz , Weizhao Ouyang , u-boot@lists.denx.de Subject: [PATCH v2 2/3] rockchip: rk35xx: Enable eMMC HS200 mode by default Date: Sun, 4 Feb 2024 20:53:06 +0000 Message-ID: <20240204205312.2342868-3-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240204205312.2342868-1-jonas@kwiboo.se> References: <20240204205312.2342868-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65bff9466f7b756870de3904 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Testing has shown that writing to eMMC using a slower mode then HS200 typically generate an ERROR on first attempt on RK3588. # Rescan using MMC legacy mode => mmc rescan 0 # Write a single block to sector 0x4000 fails with ERROR => mmc write 20000000 4000 1 # Write a single block to sector 0x4000 now works => mmc write 20000000 4000 1 With the MMC_SPEED_MODE_SET Kconfig option enabled. Writing to eMMC using HS200 mode work more reliably than slower modes on RK35xx boards. Enable MMC_HS200_SUPPORT Kconfig option by default to prefer use of HS200 mode on RK356x and RK3588. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Weizhao Ouyang Reviewed-by: Quentin Schulz --- Changes in v2: - Imply MMC_HS200_SUPPORT and SPL_MMC_HS200_SUPPORT in arch Kconfig instead of adding to each boards defconfig - R-b tags not collected because of above change - Combine changes for rk356x and rk3588 in one patch - Update commit message Link to v1: https://patchwork.ozlabs.org/patch/1891693/ --- arch/arm/mach-rockchip/Kconfig | 4 ++++ configs/nanopi-r5c-rk3568_defconfig | 2 -- configs/nanopi-r5s-rk3568_defconfig | 2 -- configs/radxa-e25-rk3568_defconfig | 2 -- 4 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6ff0aa6911e2..946ef5d7023d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -292,6 +292,8 @@ config ROCKCHIP_RK3568 imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT help The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, @@ -317,6 +319,8 @@ config ROCKCHIP_RK3588 imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT imply CLK_SCMI imply SCMI_FIRMWARE help diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 833cff0e457d..f5a472d03d78 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -58,8 +58,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 2736d382a352..99692d341f44 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -58,8 +58,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig index 5a613abe0d2d..fedb137877ab 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -60,8 +60,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y From patchwork Sun Feb 4 20:53:07 2024 Content-Type: text/plain; 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jonas@kwiboo.se, smtp.forwardemail.net, 167.172.40.54 X-ForwardEmail-ID: 65bff94a6f7b756870de3912 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Testing has shown that writing to eMMC using HS400 modes on RK3568 result in an ERROR. Change the tap number for transmit clock to fix this. Also stop DLL when config_dll() is called to disable DLL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- Changes in v2: - New patch to fix HS400 mode write on RK3568 --- drivers/mmc/rockchip_sdhci.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 285332d9f4fd..706fb1235796 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -71,7 +71,6 @@ #define DLL_RXCLK_NO_INVERTER BIT(29) #define DLL_RXCLK_ORI_GATE BIT(31) #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 -#define DLL_TXCLK_TAPNUM_90_DEGREES 0x9 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) #define DLL_TXCLK_NO_INVERTER BIT(29) #define DLL_STRBIN_TAPNUM_DEFAULT 0x4 @@ -314,8 +313,10 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab int val, ret; u32 extra, txclk_tapnum; - if (!enable) + if (!enable) { + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); return 0; + } if (clock >= 100 * MHz) { /* reset DLL */ @@ -648,7 +649,7 @@ static const struct sdhci_data rk3568_data = { .config_dll = rk3568_sdhci_config_dll, .flags = FLAG_INVERTER_FLAG_IN_RXCLK, .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, - .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, + .hs400_txclk_tapnum = 0x8, }; static const struct sdhci_data rk3588_data = { @@ -656,7 +657,7 @@ static const struct sdhci_data rk3588_data = { .set_clock = rk3568_sdhci_set_clock, .config_dll = rk3568_sdhci_config_dll, .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, - .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES, + .hs400_txclk_tapnum = 0x9, }; static const struct udevice_id sdhci_ids[] = {