From patchwork Thu Feb 1 09:14:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Monk Chiang X-Patchwork-Id: 1893838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=gTj4IAWZ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TQYD864Ndz23g7 for ; Thu, 1 Feb 2024 20:15:50 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A80013858297 for ; Thu, 1 Feb 2024 09:15:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by sourceware.org (Postfix) with ESMTPS id 6AEC13858D37 for ; Thu, 1 Feb 2024 09:14:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6AEC13858D37 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6AEC13858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::533 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706778878; cv=none; b=PLdx+15P/4ME6KL/kv/FVOYdjMBkIXhCt58pEvUCZYOSZP5JM/mx4re2sGQuMA+TPy+taJHF75pxYs6lkPuBfYD92i090+ROveoZx7Bvr5o78EcRG+xqcBTDoMJH3jT1WmWettqhcZamLq6Z1QtXrJfQ6tnvxehRp5i9ANRMpbs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706778878; c=relaxed/simple; bh=YWDedrnCw2Aak0rnuunz3S1uSbCjDFnSYLzex5Rj5d8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ZNbilychj4itobZkS+bjJ56UJAHjEACJvgdP4Vb9LphVRlTBBdIJ0Ho6RPiLI2Tz3lKsPf09Pyn62E7SORYT4Jt9+qzxDFmj96km75RvU0QyD2umMlmrL36NPu1Du8LZMKs1CxwFDbJI2osy74Yusi1glwh2qxwibYgqT+RTxd8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-5d8ddbac4fbso650434a12.0 for ; Thu, 01 Feb 2024 01:14:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1706778864; x=1707383664; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ePXxaJ9aazgL3xzYxUciEq8EN1GfIIct0RAUSUuXpfI=; b=gTj4IAWZDROyD/Pd8T0J0fLCJjHmXl8ovAwZ5Jf9u1ipQNR1VXK7AkME/s4xes0UBo F3ICuio2XdcnAYvM0Bv5hPVLJCjOoSqYFE9vQw8wn+rR/qTYP1j8ftPIYv1RYzulsoMy 9VOYOleHvqjDngeMzqt4T5l9ibOI651bYf0ANJ3rxXiga4tNdK29Gpb3uBj5YW/HB0wp mfN/bu6Mnf9X6IzSuwdPY5gEOZp/21lVCzNvAsYK9xot65XIYA03PzPKPcsxN8d+gR2X PerWFaqYk9JHF1yiI8jhp40GmSIDoMdhiaB3wih7da9VIL9RV+4Q1hHnkKAOpFdT5Cw4 03nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706778864; x=1707383664; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ePXxaJ9aazgL3xzYxUciEq8EN1GfIIct0RAUSUuXpfI=; b=cdTU/GZOqn9FxeTMGEH53Ghqy74NS+TdsOPEi5Xsds1NpIkTwUEsXtWvGzkJXNyxVR iABieueZukFZflD2xedUzPkZJHAvV1D8ClrTgNsbE6xrbUkSAs9oo9D6wJVSLu+TdUpu j9exditGNQOJOWlXkyYLMECarTB/RteiDb0ioHhbqH1ck/CmHL1VejC3zrsDj+itZotp po7d5o0dh8FnKDx6o+4gUPkbDlL/xOsrhmKsGGdjCanlZl/XwkkzSzaky37I6i1Pa7jD AAbt1s3s0nLBCBITsomveFZFD4m9jw5YHP0bUUM0jOyJycwbbP2aOXPAiBHKcJ7t3rzG j1JA== X-Gm-Message-State: AOJu0Yzqh7flIhLk7+13jQeX61751+fGkRX14u1tFxarngzMSmYVDf3I MFeQ6oEnJ7OqtuOBWRRJv3RSMvVyr8WI/HmfA9UlYUtejo9ORfqafTF9UWshJABz+W0KiQnXyYG yC6ScaNvihS7lNuKSQM8RZSPP24qKEAWKbUUKchydEkRlxj83W9CF3CrJ1qYdQBqkJrFqwgUjMJ ZFeNXJBFLS3kH+S7fEOw8TNApKMtu0utQrzCctWqM1oA== X-Google-Smtp-Source: AGHT+IH961UREeMeAHhFlbo8HpEz9vdLTKzGl0fX5YzpU72rhHIgovQJ6Hite55FdI2FM2ydMRBhbA== X-Received: by 2002:a05:6a21:1a1:b0:19c:8d73:721b with SMTP id le33-20020a056a2101a100b0019c8d73721bmr4410665pzb.57.1706778863689; Thu, 01 Feb 2024 01:14:23 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCVnU6WBPJJ2f/4DeRAd1Kuh1RVFIqc2OJZ6u6kc483YE6IOvP+oTlaPk4zwIu9wlVpX0SalJD4/5j0c/YUYVoK5d7zI2ys= Received: from hsinchu02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q21-20020a62ae15000000b006d97f80c4absm11320795pff.41.2024.02.01.01.14.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 01:14:23 -0800 (PST) From: Monk Chiang To: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com Cc: Monk Chiang Subject: [PATCH v2] RISC-V: Add minimal support for 7 new unprivileged extensions Date: Thu, 1 Feb 2024 17:14:18 +0800 Message-Id: <20240201091418.81874-1-monk.chiang@sifive.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org The RISC-V Profiles specification here: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions These extensions don't add any new features but describe existing features. So this patch only adds parsing. Za64rs: Reservation set size of 64 bytes Za128rs: Reservation set size of 128 bytes Ziccif: Main memory supports instruction fetch with atomicity requirement Ziccrse: Main memory supports forward progress on LR/SC sequences Ziccamoa: Main memory supports all atomics in A Zicclsm: Main memory supports misaligned loads/stores Zic64b: Cache block size isf 64 bytes gcc/ChangeLog: * config/riscv/riscv-common.cc: Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items. * config/riscv/riscv.opt: New macro for 7 new unprivileged extensions. * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/za-ext.c: New test. * gcc.target/riscv/zi-ext.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 14 ++++++++++++ gcc/config/riscv/riscv.opt | 14 ++++++++++++ gcc/doc/invoke.texi | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/za-ext.c | 17 +++++++++++++++ gcc/testsuite/gcc.target/riscv/zi-ext.c | 29 +++++++++++++++++++++++++ 5 files changed, 102 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/za-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/zi-ext.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 6ac0422ac13..631ce8309a0 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -247,6 +247,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zicond", ISA_SPEC_CLASS_NONE, 1, 0}, + {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -276,6 +278,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zic64b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ziccif", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, @@ -1494,6 +1501,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, + {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, + {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS}, {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, @@ -1523,6 +1532,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, + {"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B}, + {"ziccamoa", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCAMOA}, + {"ziccif", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCIF}, + {"zicclsm", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCLSM}, + {"ziccrse", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCRSE}, {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index b6d8e9a3f74..f6ff70b2b30 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -225,11 +225,25 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext) Mask(ZICOND) Var(riscv_zi_subext) +Mask(ZIC64B) Var(riscv_zi_subext) + +Mask(ZICCAMOA) Var(riscv_zi_subext) + +Mask(ZICCIF) Var(riscv_zi_subext) + +Mask(ZICCLSM) Var(riscv_zi_subext) + +Mask(ZICCRSE) Var(riscv_zi_subext) + TargetVariable int riscv_za_subext Mask(ZAWRS) Var(riscv_za_subext) +Mask(ZA64RS) Var(riscv_za_subext) + +Mask(ZA128RS) Var(riscv_za_subext) + TargetVariable int riscv_zb_subext diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ca2c0e90452..09abd2aef31 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30262,6 +30262,14 @@ Supported extension are listed below: @tab 1.0 @tab Integer conditional operations extension. +@item za64rs +@tab 1.0 +@tab Reservation set size of 64 bytes. + +@item za128rs +@tab 1.0 +@tab Reservation set size of 128 bytes. + @item zawrs @tab 1.0 @tab Wait-on-reservation-set extension. @@ -30370,6 +30378,26 @@ Supported extension are listed below: @tab 1.0 @tab Cache-block prefetch extension. +@item zic64b +@tab 1.0 +@tab Cache block size isf 64 bytes. + +@item ziccamoa +@tab 1.0 +@tab Main memory supports all atomics in A. + +@item ziccif +@tab 1.0 +@tab Main memory supports instruction fetch with atomicity requirement. + +@item zicclsm +@tab 1.0 +@tab Main memory supports misaligned loads/stores. + +@item ziccrse +@tab 1.0 +@tab Main memory supports forward progress on LR/SC sequences. + @item zicntr @tab 2.0 @tab Standard extension for base counters and timers. diff --git a/gcc/testsuite/gcc.target/riscv/za-ext.c b/gcc/testsuite/gcc.target/riscv/za-ext.c new file mode 100644 index 00000000000..126da2fcadd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/za-ext.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_za64rs_za128rs" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_za64rs_za128rs" { target { rv32 } } } */ + +#ifndef __riscv_za64rs +#error "Feature macro for 'za64rs' not defined" +#endif + +#ifndef __riscv_za128rs +#error "Feature macro for 'za128rs' not defined" +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/zi-ext.c b/gcc/testsuite/gcc.target/riscv/zi-ext.c new file mode 100644 index 00000000000..65a7acb32af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zi-ext.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zic64b_ziccamoa_ziccif_zicclsm_ziccrse" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zic64b_ziccamoa_ziccif_zicclsm_ziccrse" { target { rv32 } } } */ + +#ifndef __riscv_zic64b +#error "Feature macro for 'zic64b' not defined" +#endif + +#ifndef __riscv_ziccamoa +#error "Feature macro for 'ziccamoa' not defined" +#endif + +#ifndef __riscv_ziccif +#error "Feature macro for 'ziccif' not defined" +#endif + +#ifndef __riscv_zicclsm +#error "Feature macro for 'zicclsm' not defined" +#endif + +#ifndef __riscv_ziccrse +#error "Feature macro for 'ziccrse' not defined" +#endif + +int +foo (int a) +{ + return a; +}