From patchwork Wed Dec 6 11:49:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1872722 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.48.161; helo=sy.mirrors.kernel.org; envelope-from=devicetree+bounces-22255-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org [147.75.48.161]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SlbMm4S7Wz23mf for ; Wed, 6 Dec 2023 22:51:16 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 3567FB20E73 for ; Wed, 6 Dec 2023 11:51:16 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1FBEF3457B; Wed, 6 Dec 2023 11:51:06 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A942171D; Wed, 6 Dec 2023 03:50:57 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id D5E997FD6; Wed, 6 Dec 2023 19:50:54 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:50:54 +0800 Received: from jsia-virtual-machine.localdomain (175.136.135.142) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:50:47 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v1 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Date: Wed, 6 Dec 2023 19:49:49 +0800 Message-ID: <20231206115000.295825-6-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> References: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the System clocks and reset generator (SYSCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../clock/starfive,jh8100-syscrg.yaml | 66 ++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 123 ++++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 23 ++++ 3 files changed, 212 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml new file mode 100644 index 000000000000..14ff8e4ef564 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 System Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-syscrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: External I2S Rx BCLK clock + - description: External I2S Rx LRCK clock + - description: External MCLK clock + + clock-names: + items: + - const: clk_osc + - const: clk_i2srx_bclk_ext + - const: clk_i2srx_lrck_ext + - const: clk_mclk_ext + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@126d0000 { + compatible = "starfive,jh8100-syscrg"; + reg = <0x126d0000 0x10000>; + clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>, + <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>; + clock-names = "clk_osc", "clk_i2srx_bclk_ext", + "clk_i2srx_lrck_ext", "clk_mclk_ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h new file mode 100644 index 000000000000..e5bb588ce798 --- /dev/null +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Sia Jee Heng + * + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ + +/* SYSCRG_CLK */ +#define SYSCRG_CLK_VDEC_ROOT_PREOSC 0 +#define SYSCRG_CLK_VDEC_ROOT 1 +#define SYSCRG_CLK_VENC_ROOT_PREOSC 2 +#define SYSCRG_CLK_VENC_ROOT 3 +#define SYSCRG_CLK_GPU_ROOT 4 +#define SYSCRG_CLK_GPU_CORE 5 +#define SYSCRG_CLK_VOUT_ROOT0_PREOSC 6 +#define SYSCRG_CLK_VOUT_ROOT0 7 +#define SYSCRG_CLK_VOUT_ROOT1_PREOSC 8 +#define SYSCRG_CLK_VOUT_ROOT1 9 +#define SYSCRG_CLK_VOUT_SCAN_ATS 10 +#define SYSCRG_CLK_PERH_ROOT_PREOSC 11 +#define SYSCRG_CLK_PERH_ROOT 12 +#define SYSCRG_CLK_AXI_200_PREOSC 13 +#define SYSCRG_CLK_AXI_200 14 +#define SYSCRG_CLK_AXI_200_GMAC 15 +#define SYSCRG_CLK_AXI_500_PREOSC 16 +#define SYSCRG_CLK_AXI_500 17 +#define SYSCRG_CLK_AXI_500_PCIEX1A 18 +#define SYSCRG_CLK_AXI_500_PCIEX1B 19 +#define SYSCRG_CLK_AXI_500_PCIEX2 20 +#define SYSCRG_CLK_AXI_500_PCIEX8 21 +#define SYSCRG_CLK_AXI_400_PREOSC 22 +#define SYSCRG_CLK_AXI_400 23 +#define SYSCRG_CLK_AXI_400_APBOOTRAM 24 +#define SYSCRG_CLK_AXI_125_PREOSC 25 +#define SYSCRG_CLK_AXI_125 26 +#define SYSCRG_CLK_AHB0_PREOSC 27 +#define SYSCRG_CLK_AHB0 28 +#define SYSCRG_CLK_APB_BUS_FUNC 29 +#define SYSCRG_CLK_APB_BUS 30 +#define SYSCRG_CLK_APB_BUS_PER0 31 +#define SYSCRG_CLK_APB_BUS_PER1 32 +#define SYSCRG_CLK_APB_BUS_PER2 33 +#define SYSCRG_CLK_APB_BUS_PER3 34 +#define SYSCRG_CLK_APB_BUS_PER4 35 +#define SYSCRG_CLK_APB_BUS_PER5 36 +#define SYSCRG_CLK_APB_BUS_PER6 37 +#define SYSCRG_CLK_APB_BUS_PER7 38 +#define SYSCRG_CLK_APB_BUS_PER8 39 +#define SYSCRG_CLK_APB_BUS_PER9 40 +#define SYSCRG_CLK_APB_BUS_PER10 41 +#define SYSCRG_CLK_SPI_CORE_100 42 +#define SYSCRG_CLK_PLL1_DIV2 43 +#define SYSCRG_CLK_PLL2_DIV2 44 +#define SYSCRG_CLK_PLL3_DIV2 45 +#define SYSCRG_CLK_PLL4_DIV2 46 +#define SYSCRG_CLK_PLL6_DIV2 47 +#define SYSCRG_CLK_PLL7_DIV2 48 +#define SYSCRG_CLK_AUDIO_ROOT 49 +#define SYSCRG_CLK_MCLK_INNER 50 +#define SYSCRG_CLK_MCLK 51 +#define SYSCRG_CLK_MCLK_OUT 52 +#define SYSCRG_CLK_ISP_2X_PREOSC 53 +#define SYSCRG_CLK_ISP_2X 54 +#define SYSCRG_CLK_ISP_AXI 55 +#define SYSCRG_CLK_GCLK1 56 +#define SYSCRG_CLK_GCLK2 57 +#define SYSCRG_CLK_GCLK3 58 +#define SYSCRG_CLK_GCLK4 59 +#define SYSCRG_CLK_GCLK6 60 +#define SYSCRG_CLK_GCLK7 61 +#define SYSCRG_CLK_FLEXNOC0_PREOSC 62 +#define SYSCRG_CLK_FLEXNOC0 63 +#define SYSCRG_CLK_FLEXNOC1_PREOSC 64 +#define SYSCRG_CLK_FLEXNOC1 65 +#define SYSCRG_CLK_FLEXNOC2_PREOSC 66 +#define SYSCRG_CLK_FLEXNOC2 67 +#define SYSCRG_CLK_VDEC_CORE 68 +#define SYSCRG_CLK_GPU_CORE_ICG 69 +#define SYSCRG_CLK_IMG_GPU_CLK_APB 70 +#define SYSCRG_CLK_IMG_GPU_RTC_TOGGLE 71 +#define SYSCRG_CLK_IMG_GPU_TIMER_USC 72 +#define SYSCRG_CLK_HIFI4_CORE_PREOSC 73 +#define SYSCRG_CLK_HIFI4_CORE 74 +#define SYSCRG_CLK_ESPI_200_PREOSC 75 +#define SYSCRG_CLK_ESPI_200 76 +#define SYSCRG_CLK_HD_AUDIO_48M 77 +#define SYSCRG_CLK_VOUT_DC_CORE 78 +#define SYSCRG_CLK_VOUT_AXI 79 +#define SYSCRG_CLK_USB_WRAP_625 80 +#define SYSCRG_CLK_USB_WRAP_480 81 +#define SYSCRG_CLK_USB_WRAP_240 82 +#define SYSCRG_CLK_USB_WRAP_60 83 +#define SYSCRG_CLK_USB_WRAP_156P25 84 +#define SYSCRG_CLK_USB_WRAP_312P5 85 +#define SYSCRG_CLK_USB_125M 86 +#define SYSCRG_CLK_FLEXNOC_APBOOTRAM 87 +#define SYSCRG_CLK_FLEXNOC_PCIEX1AMST 88 +#define SYSCRG_CLK_FLEXNOC_PCIEX1ASLV 89 +#define SYSCRG_CLK_FLEXNOC_PCIEX1BMST 90 +#define SYSCRG_CLK_FLEXNOC_PCIEX1BSLV 91 +#define SYSCRG_CLK_FLEXNOC_PCIEX2MST 92 +#define SYSCRG_CLK_FLEXNOC_PCIEX2SLV 93 +#define SYSCRG_CLK_FLEXNOC_PCIEX8MST 94 +#define SYSCRG_CLK_FLEXNOC_PCIEX8SLV 95 +#define SYSCRG_CLK_FLEXNOC_GMACSYSSLV 96 +#define SYSCRG_CLK_GMAC_SRC 97 +#define SYSCRG_CLK_GMAC1_GTXCLK_TOP 98 +#define SYSCRG_CLK_GMAC1_PTP 99 +#define SYSCRG_CLK_HD_AUDIO_SYSTEM_CLOCK 100 +#define SYSCRG_CLK_HD_AUDIO_CLOCK_48 101 +#define SYSCRG_CLK_HD_AUDIO_BCLK_POST_OCC_IN 102 +#define SYSCRG_CLK_NNE_VIP_ACLK 103 +#define SYSCRG_CLK_NNE_VIP_HCLK 104 +#define SYSCRG_CLK_NNE_VIP_CLKCORE 105 +#define SYSCRG_CLK_GPU_ICG_EN 106 +#define SYSCRG_CLK_HD_AUDIO_ICG_EN 107 +#define SYSCRG_CLK_NNE_ICG_EN 108 + +#define SYSCRG_CLK_END 109 +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h new file mode 100644 index 000000000000..3b7b92488e76 --- /dev/null +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (c) 2022-2023 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ + +/* + * syscrg: assert0 + */ +#define SYSCRG_RSTN_SYS_SYSCON 0 +#define SYSCRG_RSTN_CLK_MOD 1 +#define SYSCRG_RSTN_GPU 2 +#define SYSCRG_RSTN_GPU_SPU 3 +#define SYSCRG_RSTN_GPU_TVSENSOR 4 +#define SYSCRG_RSTN_PPU_OP_NORET_GPU_RESET 5 +#define SYSCRG_RSTN_NNE 6 +#define SYSCRG_RSTN_HD_AUDIO 7 + +#define SYSCRG_RESET_NR_RESETS 8 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Wed Dec 6 11:49:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1872723 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:40f1:3f00::1; helo=sy.mirrors.kernel.org; envelope-from=devicetree+bounces-22257-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org [IPv6:2604:1380:40f1:3f00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SlbN44RVNz23mf for ; Wed, 6 Dec 2023 22:51:32 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 5E1EDB20DE5 for ; Wed, 6 Dec 2023 11:51:32 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C12B83457B; Wed, 6 Dec 2023 11:51:24 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 795E51981; Wed, 6 Dec 2023 03:51:12 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id DDD0C24E311; Wed, 6 Dec 2023 19:51:10 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:51:10 +0800 Received: from jsia-virtual-machine.localdomain (175.136.135.142) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:51:03 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v1 07/16] dt-bindings: clock: Add StarFive JH8100 System-North-West clock and reset generator Date: Wed, 6 Dec 2023 19:49:51 +0800 Message-ID: <20231206115000.295825-8-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> References: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the System-North-West clock and reset generator (SYSCRG-NW) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 45 +++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 15 +++ 3 files changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml new file mode 100644 index 000000000000..b16a874828dd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-nw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 System-North-West Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-syscrg-nw + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: APB_BUS clock from SYSCRG + - description: ISP_2X clock from SYSCRG + - description: ISP_AXI clock from SYSCRG + - description: VOUT_ROOT0 clock from SYSCRG + - description: VOUT_ROOT1 clock from SYSCRG + - description: VOUT_SCAN_ATS clock from SYSCRG + - description: VOUT_DC_CORE clock from SYSCRG + - description: VOUT_AXI clock from SYSCRG + - description: AXI_400 clock from SYSCRG + - description: AXI_200 clock from SYSCRG + - description: Peripheral clock from SYSCRG + - description: External DVP clock + - description: External ISP DPHY TAP TCK clock + - description: External golbal clock + - description: External i2s_tscko clock + - description: External VOUT MIPI DPHY TAP TCK + - description: External VOUT eDP TAP TCK + - description: External SPI In2 clock + + clock-names: + items: + - const: clk_osc + - const: sys_clk_apb_bus + - const: sys_clk_isp_2x + - const: sys_clk_isp_axi + - const: sys_clk_vout_root0 + - const: sys_clk_vout_root1 + - const: sys_clk_vout_scan_ats + - const: sys_clk_vout_dc_core + - const: sys_clk_vout_axi + - const: sys_clk_axi_400 + - const: sys_clk_axi_200 + - const: sys_clk_perh_root_preosc + - const: clk_dvp_ext + - const: clk_isp_dphy_tap_tck_ext + - const: clk_glb_ext_clk + - const: clk_i2s_tscko + - const: clk_vout_mipi_dphy_tap_tck_ext + - const: clk_vout_edp_tap_tck_ext + - const: clk_spi_in2_ext + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@123c0000 { + compatible = "starfive,jh8100-syscrg-nw"; + reg = <0x123c0000 0x10000>; + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>, + <&syscrg SYSCRG_CLK_ISP_2X>, + <&syscrg SYSCRG_CLK_ISP_AXI>, + <&syscrg SYSCRG_CLK_VOUT_ROOT0>, + <&syscrg SYSCRG_CLK_VOUT_ROOT1>, + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>, + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>, + <&syscrg SYSCRG_CLK_VOUT_AXI>, + <&syscrg SYSCRG_CLK_AXI_400>, + <&syscrg SYSCRG_CLK_AXI_200>, + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>, + <&clk_dvp_ext>, + <&clk_isp_dphy_tap_tck_ext>, + <&clk_glb_ext_clk>, + <&clk_i2s_tscko>, + <&clk_vout_mipi_dphy_tap_tck_ext>, + <&clk_vout_edp_tap_tck_ext>, + <&clk_spi_in2_ext>; + clock-names = "clk_osc", "sys_clk_apb_bus", "sys_clk_isp_2x", + "sys_clk_isp_axi", "sys_clk_vout_root0", + "sys_clk_vout_root1", "sys_clk_vout_scan_ats", + "sys_clk_vout_dc_core", "sys_clk_vout_axi", + "sys_clk_axi_400", "sys_clk_axi_200", + "sys_clk_perh_root_preosc", "clk_dvp_ext", + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk", + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext", + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index e5bb588ce798..8417455c2409 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -120,4 +120,49 @@ #define SYSCRG_CLK_NNE_ICG_EN 108 #define SYSCRG_CLK_END 109 + +/* SYSCRG_NW_CLK */ +#define SYSCRG_NW_CLK_PLL5_DIV2 0 +#define SYSCRG_NW_CLK_GCLK5 1 +#define SYSCRG_NW_CLK_GPIO_100 2 +#define SYSCRG_NW_CLK_GPIO_50 3 +#define SYSCRG_NW_CLK_GPIO_150 4 +#define SYSCRG_NW_CLK_GPIO_60 5 +#define SYSCRG_NW_CLK_IOMUX_WEST_PCLK 6 +#define SYSCRG_NW_CLK_I2C6_APB 7 +#define SYSCRG_NW_CLK_I2C7_APB 8 +#define SYSCRG_NW_CLK_SPI2_APB 9 +#define SYSCRG_NW_CLK_SPI2_CORE 10 +#define SYSCRG_NW_CLK_SPI2_SCLK_IN 11 +#define SYSCRG_NW_CLK_SMBUS1_APB 12 +#define SYSCRG_NW_CLK_SMBUS1_CORE 13 +#define SYSCRG_NW_CLK_ISP_DVP 14 +#define SYSCRG_NW_CLK_ISP_CORE_2X 15 +#define SYSCRG_NW_CLK_ISP_AXI 16 +#define SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK 17 +#define SYSCRG_NW_CLK_FLEXNOC_ISPSLV 18 +#define SYSCRG_NW_CLK_VOUT_PIX0 19 +#define SYSCRG_NW_CLK_VOUT_PIX1 20 +#define SYSCRG_NW_CLK_VOUT_SCAN_ATS 21 +#define SYSCRG_NW_CLK_VOUT_DC_CORE 22 +#define SYSCRG_NW_CLK_VOUT_APB 23 +#define SYSCRG_NW_CLK_VOUT_DSI 24 +#define SYSCRG_NW_CLK_VOUT_AHB 25 +#define SYSCRG_NW_CLK_VOUT_AXI 26 +#define SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK 27 +#define SYSCRG_NW_CLK_VOUT_EDP_PHY_TAP_TCK 28 +#define SYSCRG_NW_CLK_UART5_CORE_PREOSC 29 +#define SYSCRG_NW_CLK_UART5_APB 30 +#define SYSCRG_NW_CLK_UART5_CORE 31 +#define SYSCRG_NW_CLK_UART6_CORE_PREOSC 32 +#define SYSCRG_NW_CLK_UART6_APB 33 +#define SYSCRG_NW_CLK_UART6_CORE 34 +#define SYSCRG_NW_CLK_SPI2_ICG_EN 35 +#define SYSCRG_NW_CLK_SMBUS1_ICG_EN 36 +#define SYSCRG_NW_CLK_ISP_ICG_EN 37 +#define SYSCRG_NW_CLK_VOUT_ICG_EN 38 +#define SYSCRG_NW_CLK_UART5_ICG_EN 39 +#define SYSCRG_NW_CLK_UART6_ICG_EN 40 + +#define SYSCRG_NW_CLK_END 41 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 3b7b92488e76..8c3a858bdf6a 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -20,4 +20,19 @@ #define SYSCRG_RESET_NR_RESETS 8 +/* + * syscrg_nw: assert0 + */ +#define SYSCRG_NW_RSTN_PRESETN 0 +#define SYSCRG_NW_RSTN_SYS_IOMUX_W 1 +#define SYSCRG_NW_RSTN_I2C6 2 +#define SYSCRG_NW_RSTN_I2C7 3 +#define SYSCRG_NW_RSTN_SPI2 4 +#define SYSCRG_NW_RSTN_SMBUS1 5 +#define SYSCRG_NW_RSTN_UART5 6 +#define SYSCRG_NW_RSTN_UART6 7 +#define SYSCRG_NW_RSTN_MERAK0_TVSENSOR 8 +#define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9 + +#define SYSCRG_NW_RESET_NR_RESETS 10 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Wed Dec 6 11:49:53 2023 Content-Type: text/plain; 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Wed, 6 Dec 2023 19:51:19 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v1 09/16] dt-bindings: clock: Add StarFive JH8100 System-North-East clock and reset generator Date: Wed, 6 Dec 2023 19:49:53 +0800 Message-ID: <20231206115000.295825-10-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> References: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the System-North-East clock and reset generator (SYSCRG-NE) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../clock/starfive,jh8100-syscrg-ne.yaml | 158 ++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 179 ++++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 61 ++++++ 3 files changed, 398 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml new file mode 100644 index 000000000000..e9c1156489b2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-ne.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 System-North-East Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-syscrg-ne + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: AXI_400 clock from SYSCRG + - description: VOUT_ROOT0 clock from SYSCRG + - description: VOUT_ROOT1 clock from SYSCRG + - description: USB_WRAP_480 clock from SYSCRG + - description: USB_WRAP_625 clock from SYSCRG + - description: USB_WRAP_240 clock from SYSCRG + - description: USB_WRAP_60 clock from SYSCRG + - description: USB_WRAP_156P25 clock from SYSCRG + - description: USB_WRAP_312P5 clock from SYSCRG + - description: USB_125M clock from SYSCRG + - description: GPIO_100 clock from SYSCRG_NW + - description: PERH_ROOT clock from SYSCRG + - description: Master clock from SYSCRG + - description: PERH_ROOT_PREOSC clock from SYSCRG + - description: AHB0 clock from SYSCRG + - description: APB_BUS_PER1 clock from SYSCRG + - description: APB_BUS PER2 clock from SYSCRG + - description: APB_BUS_PER3 clock from SYSCRG + - description: APB_BUS_PER5 clock from SYSCRG + - description: VENC_ROOT clock from SYSCRG + - description: SPI_CORE_100 clock from SYSCRG + - description: External global clock + - description: External USB3_TAP_TCK clock + - description: External USB1_TAP_TCK clock + - description: External USB2_TAP_TCK clock + - description: External TYPEC_TAP_TCK clock + - description: External SPI_IN0 clock + - description: External SPI_IN1 clock + - description: External I2STX_BCLK clock + - description: External I2STX_LRCK clock + + clock-names: + items: + - const: clk_osc + - const: sys_clk_axi_400 + - const: sys_clk_vout_root0 + - const: sys_clk_vout_root1 + - const: sys_clk_usb_wrap_480 + - const: sys_clk_usb_wrap_625 + - const: sys_clk_usb_wrap_240 + - const: sys_clk_usb_wrap_60 + - const: sys_clk_usb_wrap_156p25 + - const: sys_clk_usb_wrap_312p5 + - const: sys_clk_usb_125m + - const: sys_nw_clk_gpio_100 + - const: sys_clk_perh_root + - const: sys_clk_mclk + - const: sys_clk_perh_root_preosc + - const: sys_clk_ahb0 + - const: sys_clk_apb_bus_per1 + - const: sys_clk_apb_bus_per2 + - const: sys_clk_apb_bus_per3 + - const: sys_clk_apb_bus_per5 + - const: sys_clk_venc_root + - const: sys_clk_spi_core_100 + - const: clk_glb_ext_clk + - const: clk_usb3_tap_tck_ext + - const: clk_usb1_tap_tck_ext + - const: clk_usb2_tap_tck_ext + - const: clk_typec_tap_tck_ext + - const: clk_spi_in0_ext + - const: clk_spi_in1_ext + - const: clk_i2stx_bclk_ext + - const: clk_i2stx_lrck_ext + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@12320000 { + compatible = "starfive,jh8100-syscrg-ne"; + reg = <0x12320000 0x10000>; + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_AXI_400>, + <&syscrg SYSCRG_CLK_VOUT_ROOT0>, + <&syscrg SYSCRG_CLK_VOUT_ROOT1>, + <&syscrg SYSCRG_CLK_USB_WRAP_480>, + <&syscrg SYSCRG_CLK_USB_WRAP_625>, + <&syscrg SYSCRG_CLK_USB_WRAP_240>, + <&syscrg SYSCRG_CLK_USB_WRAP_60>, + <&syscrg SYSCRG_CLK_USB_WRAP_156P25>, + <&syscrg SYSCRG_CLK_USB_WRAP_312P5>, + <&syscrg SYSCRG_CLK_USB_125M>, + <&syscrg_nw SYSCRG_NW_CLK_GPIO_100>, + <&syscrg SYSCRG_CLK_PERH_ROOT>, + <&syscrg SYSCRG_CLK_MCLK>, + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>, + <&syscrg SYSCRG_CLK_AHB0>, + <&syscrg SYSCRG_CLK_APB_BUS_PER1>, + <&syscrg SYSCRG_CLK_APB_BUS_PER2>, + <&syscrg SYSCRG_CLK_APB_BUS_PER3>, + <&syscrg SYSCRG_CLK_APB_BUS_PER5>, + <&syscrg SYSCRG_CLK_VENC_ROOT>, + <&syscrg SYSCRG_CLK_SPI_CORE_100>, + <&clk_glb_ext_clk>, <&clk_usb3_tap_tck_ext>, + <&clk_usb1_tap_tck_ext>, <&clk_usb2_tap_tck_ext>, + <&clk_typec_tap_tck_ext>, <&clk_spi_in0_ext>, + <&clk_spi_in1_ext>, <&clk_i2stx_bclk_ext>, + <&clk_i2stx_lrck_ext>; + clock-names = "clk_osc", "sys_clk_axi_400", + "sys_clk_vout_root0", "sys_clk_vout_root1", + "sys_clk_usb_wrap_480", "sys_clk_usb_wrap_625", + "sys_clk_usb_wrap_240", "sys_clk_usb_wrap_60", + "sys_clk_usb_wrap_156p25", "sys_clk_usb_wrap_312p5", + "sys_clk_usb_125m", "sys_nw_clk_gpio_100", + "sys_clk_perh_root", "sys_clk_mclk", + "sys_clk_perh_root_preosc", + "sys_clk_ahb0", "sys_clk_apb_bus_per1", + "sys_clk_apb_bus_per2", "sys_clk_apb_bus_per3", + "sys_clk_apb_bus_per5", "sys_clk_venc_root", + "sys_clk_spi_core_100", "clk_glb_ext_clk", + "clk_usb3_tap_tck_ext", "clk_usb1_tap_tck_ext", + "clk_usb2_tap_tck_ext", "clk_typec_tap_tck_ext", + "clk_spi_in0_ext", "clk_spi_in1_ext", + "clk_i2stx_bclk_ext", "clk_i2stx_lrck_ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 8417455c2409..b30ccd16a802 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -165,4 +165,183 @@ #define SYSCRG_NW_CLK_UART6_ICG_EN 40 #define SYSCRG_NW_CLK_END 41 + +/* SYSCRG_NE_CLK */ +#define SYSCRG_NE_CLK_FLEXNOC_DMASLV 0 +#define SYSCRG_NE_CLK_MAILBOX_APB 1 +#define SYSCRG_NE_CLK_SR5_TIMER0_APB 2 +#define SYSCRG_NE_CLK_SR5_TIMER0_CH0 3 +#define SYSCRG_NE_CLK_SR5_TIMER0_CH1 4 +#define SYSCRG_NE_CLK_SR5_TIMER0_CH2 5 +#define SYSCRG_NE_CLK_SR5_TIMER0_CH3 6 +#define SYSCRG_NE_CLK_SR5_TIMER1_APB 7 +#define SYSCRG_NE_CLK_SR5_TIMER1_CH0 8 +#define SYSCRG_NE_CLK_SR5_TIMER1_CH1 9 +#define SYSCRG_NE_CLK_SR5_TIMER1_CH2 10 +#define SYSCRG_NE_CLK_SR5_TIMER1_CH3 11 +#define SYSCRG_NE_CLK_USB3_CMN_SCAN_PLL 12 +#define SYSCRG_NE_CLK_USB3_CMN_SCAN_SER 13 +#define SYSCRG_NE_CLK_USB3_PIPE_IN_SCAN 14 +#define SYSCRG_NE_CLK_USB3_SCAN_PIPE 15 +#define SYSCRG_NE_CLK_USB3_SCAN_PSM 16 +#define SYSCRG_NE_CLK_USB3_SCAN_REF 17 +#define SYSCRG_NE_CLK_USB3_USB2_SCAN 18 +#define SYSCRG_NE_CLK_USB3_HSCLK 19 +#define SYSCRG_NE_CLK_USB3_HSSICLK 20 +#define SYSCRG_NE_CLK_USB3_SIECLK 21 +#define SYSCRG_NE_CLK_USB3_XCVR_SCAN_PLL 22 +#define SYSCRG_NE_CLK_USB3_XCVR_SCAN_SER 23 +#define SYSCRG_NE_CLK_USB3_TAP_TCK 24 +#define SYSCRG_NE_CLK_USB1_CMN_SCAN_PLL 25 +#define SYSCRG_NE_CLK_USB1_CMN_SCAN_SER 26 +#define SYSCRG_NE_CLK_USB1_PIPE_IN_SCAN 27 +#define SYSCRG_NE_CLK_USB1_SCAN_PIPE 28 +#define SYSCRG_NE_CLK_USB1_SCAN_PSM 29 +#define SYSCRG_NE_CLK_USB1_SCAN_REF 30 +#define SYSCRG_NE_CLK_USB1_USB2_SCAN 31 +#define SYSCRG_NE_CLK_USB1_HSCLK 32 +#define SYSCRG_NE_CLK_USB1_HSSICLK 33 +#define SYSCRG_NE_CLK_USB1_SIECLK 34 +#define SYSCRG_NE_CLK_USB1_XCVR_SCAN_PLL 35 +#define SYSCRG_NE_CLK_USB1_XCVR_SCAN_SER 36 +#define SYSCRG_NE_CLK_USB1_TAP_TCK 37 +#define SYSCRG_NE_CLK_USB2_CMN_SCAN_PLL 38 +#define SYSCRG_NE_CLK_USB2_CMN_SCAN_SER 39 +#define SYSCRG_NE_CLK_USB2_PIPE_IN_SCAN 40 +#define SYSCRG_NE_CLK_USB2_SCAN_PIPE 41 +#define SYSCRG_NE_CLK_USB2_SCAN_PSM 42 +#define SYSCRG_NE_CLK_USB2_SCAN_REF 43 +#define SYSCRG_NE_CLK_USB2_USB2_SCAN 44 +#define SYSCRG_NE_CLK_USB2_HSCLK 45 +#define SYSCRG_NE_CLK_USB2_HSSICLK 46 +#define SYSCRG_NE_CLK_USB2_SIECLK 47 +#define SYSCRG_NE_CLK_USB2_XCVR_SCAN_PLL 48 +#define SYSCRG_NE_CLK_USB2_XCVR_SCAN_SER 49 +#define SYSCRG_NE_CLK_USB2_TAP_TCK 50 +#define SYSCRG_NE_CLK_TYPEC_PIPE_DIV_SCAN 51 +#define SYSCRG_NE_CLK_TYPEC_CMN_SCAN_PLL 52 +#define SYSCRG_NE_CLK_TYPEC_CMN_SCAN_SER 53 +#define SYSCRG_NE_CLK_TYPEC_SCAN_PIPE 54 +#define SYSCRG_NE_CLK_TYPEC_SCAN_PSM 55 +#define SYSCRG_NE_CLK_TYPEC_SCAN_REF 56 +#define SYSCRG_NE_CLK_TYPEC_USB2_SCAN 57 +#define SYSCRG_NE_CLK_TYPEC_HSCLK 58 +#define SYSCRG_NE_CLK_TYPEC_HSSICLK 59 +#define SYSCRG_NE_CLK_TYPEC_SIECLK 60 +#define SYSCRG_NE_CLK_TYPEC_VID0 61 +#define SYSCRG_NE_CLK_TYPEC_VID1 62 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL0 63 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL1 64 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL2 65 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL3 66 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER0 67 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER1 68 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER2 69 +#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER3 70 +#define SYSCRG_NE_CLK_TYPEC_TAP_TCK 71 +#define SYSCRG_NE_CLK_VENC_AXI 72 +#define SYSCRG_NE_CLK_VC9000LE_AXI 73 +#define SYSCRG_NE_CLK_VC9000LE_APB 74 +#define SYSCRG_NE_CLK_VC9000LE_CORECLK 75 +#define SYSCRG_NE_CLK_INT_CTRL_APB 76 +#define SYSCRG_NE_CLK_PWM_8CH_APB 77 +#define SYSCRG_NE_CLK_WDT_APB 78 +#define SYSCRG_NE_CLK_WDT 79 +#define SYSCRG_NE_CLK_SPI0_APB 80 +#define SYSCRG_NE_CLK_SPI0_CORE 81 +#define SYSCRG_NE_CLK_SPI0_SCLK_IN 82 +#define SYSCRG_NE_CLK_SPI1_APB 83 +#define SYSCRG_NE_CLK_SPI1_CORE 84 +#define SYSCRG_NE_CLK_SPI1_SCLK_IN 85 +#define SYSCRG_NE_CLK_I2C0_APB 86 +#define SYSCRG_NE_CLK_I2C1_APB 87 +#define SYSCRG_NE_CLK_I2C2_APB 88 +#define SYSCRG_NE_CLK_I2C3_APB 89 +#define SYSCRG_NE_CLK_I2C4_APB 90 +#define SYSCRG_NE_CLK_I2C5_APB 91 +#define SYSCRG_NE_CLK_UART0_APB 92 +#define SYSCRG_NE_CLK_UART0_CORE 93 +#define SYSCRG_NE_CLK_UART1_CORE_PREOSC 94 +#define SYSCRG_NE_CLK_UART1_APB 95 +#define SYSCRG_NE_CLK_UART1_CORE 96 +#define SYSCRG_NE_CLK_UART2_CORE_PREOSC 97 +#define SYSCRG_NE_CLK_UART2_APB 98 +#define SYSCRG_NE_CLK_UART2_CORE 99 +#define SYSCRG_NE_CLK_UART3_CORE_PREOSC 100 +#define SYSCRG_NE_CLK_UART3_APB 101 +#define SYSCRG_NE_CLK_UART3_CORE 102 +#define SYSCRG_NE_CLK_UART4_CORE_PREOSC 103 +#define SYSCRG_NE_CLK_UART4_APB 104 +#define SYSCRG_NE_CLK_UART4_CORE 105 +#define SYSCRG_NE_CLK_I2S0_BCLK 106 +#define SYSCRG_NE_CLK_I2S0_LRCK 107 +#define SYSCRG_NE_CLK_I2S0_APB 108 +#define SYSCRG_NE_CLK_I2S0 109 +#define SYSCRG_NE_CLK_I2S0_N 110 +#define SYSCRG_NE_CLK_I2S0_BCLK_TX 111 +#define SYSCRG_NE_CLK_I2S0_LRCK_TX 112 +#define SYSCRG_NE_CLK_I2S0_BCLK_RX 113 +#define SYSCRG_NE_CLK_I2S0_LRCK_RX 114 +#define SYSCRG_NE_CLK_I2S1_BCLK 115 +#define SYSCRG_NE_CLK_I2S1_LRCK 116 +#define SYSCRG_NE_CLK_I2S1_APB 117 +#define SYSCRG_NE_CLK_I2S1 118 +#define SYSCRG_NE_CLK_I2S1_N 119 +#define SYSCRG_NE_CLK_I2S1_BCLK_TX 120 +#define SYSCRG_NE_CLK_I2S1_LRCK_TX 121 +#define SYSCRG_NE_CLK_I2S1_BCLK_RX 122 +#define SYSCRG_NE_CLK_I2S1_LRCK_RX 123 +#define SYSCRG_NE_CLK_I2S2_BCLK 124 +#define SYSCRG_NE_CLK_I2S2_LRCK 125 +#define SYSCRG_NE_CLK_I2S2_APB 126 +#define SYSCRG_NE_CLK_I2S2 127 +#define SYSCRG_NE_CLK_I2S2_N 128 +#define SYSCRG_NE_CLK_I2S2_BCLK_TX 129 +#define SYSCRG_NE_CLK_I2S2_LRCK_TX 130 +#define SYSCRG_NE_CLK_I2S2_BCLK_RX 131 +#define SYSCRG_NE_CLK_I2S2_LRCK_RX 132 +#define SYSCRG_NE_CLK_I2S3_BCLK 133 +#define SYSCRG_NE_CLK_I2S3_LRCK 134 +#define SYSCRG_NE_CLK_I2S0_STEREO_APB 135 +#define SYSCRG_NE_CLK_I2S0_STEREO 136 +#define SYSCRG_NE_CLK_I2S0_STEREO_N 137 +#define SYSCRG_NE_CLK_I2S0_STEREO_BCLK_TX 138 +#define SYSCRG_NE_CLK_I2S0_STEREO_LRCK_TX 139 +#define SYSCRG_NE_CLK_I2S0_STEREO_BCLK_RX_ICG 140 +#define SYSCRG_NE_CLK_I2S0_STEREO_LRCK_RX 141 +#define SYSCRG_NE_CLK_PDM_4MIC_DMIC 142 +#define SYSCRG_NE_CLK_PDM_4MIC_APB 143 +#define SYSCRG_NE_CLK_PDM_4MIC_SCAN 144 +#define SYSCRG_NE_CLK_CAN0_CTRL_PCLK 145 +#define SYSCRG_NE_CLK_CAN0_CTRL 146 +#define SYSCRG_NE_CLK_CAN0_CTRL_TIMER 147 +#define SYSCRG_NE_CLK_CAN1_CTRL_PCLK 148 +#define SYSCRG_NE_CLK_CAN1_CTRL 149 +#define SYSCRG_NE_CLK_CAN1_CTRL_TIMER 150 +#define SYSCRG_NE_CLK_SMBUS0_APB 151 +#define SYSCRG_NE_CLK_SMBUS0_CORE 152 +#define SYSCRG_NE_CLK_IOMUX_EAST_PCLK 153 +#define SYSCRG_NE_CLK_USB3_ICG_EN 154 +#define SYSCRG_NE_CLK_USB1_ICG_EN 155 +#define SYSCRG_NE_CLK_USB2_ICG_EN 156 +#define SYSCRG_NE_CLK_USBC_ICG_EN 157 +#define SYSCRG_NE_CLK_VENC_ICG_EN 158 +#define SYSCRG_NE_CLK_WDT0_ICG_EN 159 +#define SYSCRG_NE_CLK_SPI0_ICG_EN 160 +#define SYSCRG_NE_CLK_SPI1_ICG_EN 161 +#define SYSCRG_NE_CLK_UART0_ICG_EN 162 +#define SYSCRG_NE_CLK_UART1_ICG_EN 163 +#define SYSCRG_NE_CLK_UART2_ICG_EN 164 +#define SYSCRG_NE_CLK_UART3_ICG_EN 165 +#define SYSCRG_NE_CLK_UART4_ICG_EN 166 +#define SYSCRG_NE_CLK_I2S0_ICG_EN 167 +#define SYSCRG_NE_CLK_I2S1_ICG_EN 168 +#define SYSCRG_NE_CLK_I2S2_ICG_EN 169 +#define SYSCRG_NE_CLK_I2S_STEREO_ICG_EN 170 +#define SYSCRG_NE_CLK_PDM_4MIC_ICG_EN 171 +#define SYSCRG_NE_CLK_CAN0_ICG_EN 172 +#define SYSCRG_NE_CLK_CAN1_ICG_EN 173 +#define SYSCRG_NE_CLK_SMBUS0_ICG_EN 174 + +#define SYSCRG_NE_CLK_END 175 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 8c3a858bdf6a..7626da648686 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -35,4 +35,65 @@ #define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9 #define SYSCRG_NW_RESET_NR_RESETS 10 + +/* + * syscrg_ne: assert0 + */ +#define SYSCRG_NE_RSTN_PRESETN 0 +#define SYSCRG_NE_RSTN_USB3_APB 1 +#define SYSCRG_NE_RSTN_USB3_TORR_PHY 2 +#define SYSCRG_NE_RSTN_USB3_CONFIG 3 +#define SYSCRG_NE_RSTN_USB1_APB 4 +#define SYSCRG_NE_RSTN_USB1_TORRENT_PHY 5 +#define SYSCRG_NE_RSTN_USB1_CONFIG 6 +#define SYSCRG_NE_RSTN_USB2_APB 7 +#define SYSCRG_NE_RSTN_USB2_TORRENT_PHY 8 +#define SYSCRG_NE_RSTN_USB2_CONFIG 9 +#define SYSCRG_NE_RSTN_USBC_APB 10 +#define SYSCRG_NE_RSTN_USBC_CONFIG 11 +#define SYSCRG_NE_RSTN_VC9000LE 12 +#define SYSCRG_NE_RSTN_INT_CTRL_APB 13 +#define SYSCRG_NE_RSTN_PWM_8CH_APB 14 +#define SYSCRG_NE_RSTN_WDT0 15 +#define SYSCRG_NE_RSTN_SPI0 16 +#define SYSCRG_NE_RSTN_SPI1 17 +#define SYSCRG_NE_RSTN_I2C0 18 +#define SYSCRG_NE_RSTN_I2C1 19 +#define SYSCRG_NE_RSTN_I2C2 20 +#define SYSCRG_NE_RSTN_I2C3 21 +#define SYSCRG_NE_RSTN_I2C4 22 +#define SYSCRG_NE_RSTN_I2C5 23 +#define SYSCRG_NE_RSTN_UART0 24 +#define SYSCRG_NE_RSTN_UART1 25 +#define SYSCRG_NE_RSTN_UART2 26 +#define SYSCRG_NE_RSTN_UART3 27 +#define SYSCRG_NE_RSTN_UART4 28 +#define SYSCRG_NE_RSTN_MAILBOX_PRESETN 29 +#define SYSCRG_NE_RSTN_TIMER0_APB 30 +#define SYSCRG_NE_RSTN_TIMER0_CH0 31 + +/* + * syscrg_ne: assert1 + */ + +#define SYSCRG_NE_RSTN_TIMER0_CH1 32 +#define SYSCRG_NE_RSTN_TIMER0_CH2 33 +#define SYSCRG_NE_RSTN_TIMER0_CH3 34 +#define SYSCRG_NE_RSTN_TIMER1_APB 35 +#define SYSCRG_NE_RSTN_TIMER1_CH0 36 +#define SYSCRG_NE_RSTN_TIMER1_CH1 37 +#define SYSCRG_NE_RSTN_TIMER1_CH2 38 +#define SYSCRG_NE_RSTN_TIMER1_CH3 39 +#define SYSCRG_NE_RSTN_I2S0_RSTN_APB 40 +#define SYSCRG_NE_RSTN_I2S1_RSTN_APB 41 +#define SYSCRG_NE_RSTN_I2S2_RSTN_APB 42 +#define SYSCRG_NE_RSTN_I2S0_STEREO_APB 43 +#define SYSCRG_NE_RSTN_PDM 44 +#define SYSCRG_NE_RSTN_CAN0 45 +#define SYSCRG_NE_RSTN_CAN1 46 +#define SYSCRG_NE_RSTN_SMBUS0 47 +#define SYSCRG_NE_RSTN_SYS_IOMUX_E 48 +#define SYSCRG_NE_RSTN_DUBHE_TVSENSOR 49 + +#define SYSCRG_NE_RESET_NR_RESETS 50 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Wed Dec 6 11:49:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1872725 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.199.223; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-22261-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [147.75.199.223]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SlbNs3Xh3z23mf for ; Wed, 6 Dec 2023 22:52:13 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id BB99C1C20A33 for ; Wed, 6 Dec 2023 11:52:11 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C9A0B347D7; Wed, 6 Dec 2023 11:52:07 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2906F10C3; Wed, 6 Dec 2023 03:51:43 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 8B6D77FD6; Wed, 6 Dec 2023 19:51:42 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:51:42 +0800 Received: from jsia-virtual-machine.localdomain (175.136.135.142) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:51:35 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v1 11/16] dt-bindings: clock: Add StarFive JH8100 System-South-West clock and reset generator Date: Wed, 6 Dec 2023 19:49:55 +0800 Message-ID: <20231206115000.295825-12-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> References: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the System-South-West clock and reset generator (SYSCRG-SW) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../clock/starfive,jh8100-syscrg-sw.yaml | 66 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 14 ++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 10 +++ 3 files changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml new file mode 100644 index 000000000000..8bd41af040b7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-sw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 System-South-West Clock And Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-syscrg-sw + + reg: + maxItems: 1 + + clocks: + items: + - description: APB_BUS clock from SYSCRG + - description: VDEC_ROOT clock from SYSCRG + - description: FLEXNOC1 clock from SYSCRG + + clock-names: + items: + - const: sys_clk_apb_bus + - const: sys_clk_vdec_root + - const: sys_clk_flexnoc1 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@12720000 { + compatible = "starfive,jh8100-syscrg-sw"; + reg = <0x12720000 0x10000>; + clocks = <&syscrg SYSCRG_CLK_APB_BUS>, + <&syscrg SYSCRG_CLK_VDEC_ROOT>, + <&syscrg SYSCRG_CLK_FLEXNOC1>; + clock-names = "sys_clk_apb_bus", + "sys_clk_vdec_root", + "sys_clk_flexnoc1"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index b30ccd16a802..3ce0b9ec66be 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -344,4 +344,18 @@ #define SYSCRG_NE_CLK_SMBUS0_ICG_EN 174 #define SYSCRG_NE_CLK_END 175 + +/* SYSCRG_SW_CLK */ +#define SYSCRG_SW_CLK_JPEG_AXI 0 +#define SYSCRG_SW_CLK_VC9000DJ_AXI 1 +#define SYSCRG_SW_CLK_VC9000DJ_VDEC 2 +#define SYSCRG_SW_CLK_VC9000DJ_APB 3 +#define SYSCRG_SW_CLK_VDEC_AXI 4 +#define SYSCRG_SW_CLK_VC9000D_AXI 5 +#define SYSCRG_SW_CLK_VC9000D_VDEC 6 +#define SYSCRG_SW_CLK_VC9000D_APB 7 +#define SYSCRG_SW_CLK_JPEG_ICG_EN 8 +#define SYSCRG_SW_CLK_VDEC_ICG_EN 9 + +#define SYSCRG_SW_CLK_END 10 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 7626da648686..55209382e00e 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -96,4 +96,14 @@ #define SYSCRG_NE_RSTN_DUBHE_TVSENSOR 49 #define SYSCRG_NE_RESET_NR_RESETS 50 + +/* + * syscrg_sw: assert0 + */ +#define SYSCRG_SW_RSTN_PRESETN 0 +#define SYSCRG_SW_RSTN_VC9000DJ 1 +#define SYSCRG_SW_RSTN_VC9000D 2 +#define SYSCRG_SW_RSTN_DDR_TVSENSOR 3 + +#define SYSCRG_SW_RESET_NR_RESETS 4 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Wed Dec 6 11:49:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1872727 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org; envelope-from=devicetree+bounces-22266-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [IPv6:2604:1380:4601:e00::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SlbRZ6Pbqz23mf for ; Wed, 6 Dec 2023 22:54:34 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 5F74A1F215BE for ; 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Wed, 6 Dec 2023 19:51:50 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v1 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator Date: Wed, 6 Dec 2023 19:49:57 +0800 Message-ID: <20231206115000.295825-14-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> References: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the Always-On clock and reset generator (AONCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../clock/starfive,jh8100-aoncrg.yaml | 77 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 69 +++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 18 +++++ 3 files changed, 164 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml new file mode 100644 index 000000000000..fd55bf212259 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 Always-On Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-aoncrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII func + - description: GMAC0 RGMII func + - description: AON 125MHz clock + - description: AON 2000MHz clock + - description: AON 200MHz clock + - description: AON 667MHz clock + - description: RTC clock + + clock-names: + items: + - const: clk_osc + - const: clk_gmac0_rmii_func + - const: clk_gmac0_rgmii_func + - const: clk_aon125 + - const: clk_aon2000 + - const: clk_aon200 + - const: clk_aon667 + - const: clk_rtc + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1f310000 { + compatible = "starfive,jh8100-aoncrg"; + reg = <0x1f310000 0x10000>; + clocks = <&clk_osc>, <&clk_gmac0_rmii_func>, + <&clk_gmac0_rgmii_func>, <&clk_aon125>, + <&clk_aon2000>, <&clk_aon200>, + <&clk_aon667>, <&clk_rtc>; + clock-names = "clk_osc", "clk_gmac0_rmii_func", "clk_gmac0_rgmii_func", + "clk_aon125", "clk_aon2000", "clk_aon200", + "clk_aon667", "clk_rtc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 3ce0b9ec66be..65e719bd51a5 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -358,4 +358,73 @@ #define SYSCRG_SW_CLK_VDEC_ICG_EN 9 #define SYSCRG_SW_CLK_END 10 + +/* AONCRG_CLK */ +#define AONCRG_CLK_GMAC0_RMII_REFIN 0 +#define AONCRG_CLK_GMAC0_RGMII_RXIN 1 +#define AONCRG_CLK_GMAC0_GTXCLK 2 +#define AONCRG_CLK_AON_1000 3 +#define AONCRG_CLK_AON_400 4 +#define AONCRG_CLK_AON_400_POSTOSC 5 +#define AONCRG_CLK_AON_500 6 +#define AONCRG_CLK_AON_500_POSTOSC 7 +#define AONCRG_CLK_XSPI_PHY 8 +#define AONCRG_CLK_AON_100 9 +#define AONCRG_CLK_AON_100_POSTOSC 10 +#define AONCRG_CLK_AON_50_POSTOSC 11 +#define AONCRG_CLK_DDR50_POSTOCC_ICG 12 +#define AONCRG_CLK_DDR100_POSTOCC_ICG 13 +#define AONCRG_CLK_PUFRT_APB 14 +#define AONCRG_CLK_RTC_HMS_APB 15 +#define AONCRG_CLK_RTC_INTERNAL 16 +#define AONCRG_CLK_RTC_HMS_OSC32K 17 +#define AONCRG_CLK_RTC_HMS_CAL 18 +#define AONCRG_CLK_GMAC0_AXI128_AHB 19 +#define AONCRG_CLK_GMAC0_AXI128_MSTRCLK 20 +#define AONCRG_CLK_GMAC0_AXI128_AXI 21 +#define AONCRG_CLK_GMAC0_RMII_RTX 22 +#define AONCRG_CLK_GMAC0_AXI128_TX 23 +#define AONCRG_CLK_GMAC0_AXI128_TX_INV 24 +#define AONCRG_CLK_GMAC0_AXI128_RX 25 +#define AONCRG_CLK_GMAC0_AXI128_RX_INV 26 +#define AONCRG_CLK_GMAC0_GTXC 27 +#define AONCRG_CLK_XSPI_AXI 28 +#define AONCRG_CLK_XSPI_APB 29 +#define AONCRG_CLK_XSPI_XSPI_PHY 30 +#define AONCRG_CLK_TVSENSOR_PCLK 31 +#define AONCRG_CLK_TVSENSOR_TSADC 32 +#define AONCRG_CLK_TVSENSOR_BG 33 +#define AONCRG_CLK_MEU_PCLK_AP 34 +#define AONCRG_CLK_MEU_PCLK_SCP 35 +#define AONCRG_CLK_MEU_MEM_AXI 36 +#define AONCRG_CLK_AXIMEM_128B_ACLK 37 +#define AONCRG_CLK_APB2BISR_APB 38 +#define AONCRG_CLK_APB2BISR_BISR 39 +#define AONCRG_CLK_EMMC_S_PCLK 40 +#define AONCRG_CLK_EMMC_MSTRCLK 41 +#define AONCRG_CLK_EMMC 42 +#define AONCRG_CLK_EMMC_SDMCLK 43 +#define AONCRG_CLK_EMMC_SDPHY_PCLK 44 +#define AONCRG_CLK_SDIO0_PCLK 45 +#define AONCRG_CLK_SDIO0_MSTRCLK 46 +#define AONCRG_CLK_SDIO0 47 +#define AONCRG_CLK_SDIO0_SDMCLK 48 +#define AONCRG_CLK_SDIO0_SDPHY_PCLK 49 +#define AONCRG_CLK_HCLK 50 +#define AONCRG_CLK_ACLK 51 +#define AONCRG_CLK_PERF_MSTRCLK 52 +#define AONCRG_CLK_PERF_SLVCLK 53 +#define AONCRG_CLK_GCLK0 54 +#define AONCRG_CLK_GCLK_OSC 55 +#define AONCRG_CLK_RTC_ICG_EN 56 +#define AONCRG_CLK_GMAC0_ICG_EN 57 +#define AONCRG_CLK_XSPI_ICG_EN 58 +#define AONCRG_CLK_TVSENSOR0_ICG_EN 59 +#define AONCRG_CLK_MEU_ICG_EN 60 +#define AONCRG_CLK_APB2BISR_ICG_EN 61 +#define AONCRG_CLK_EMMC_ICG_EN 62 +#define AONCRG_CLK_SDIO0_ICG_EN 63 +#define AONCRG_CLK_TOP_ICG_EN 64 + +#define AONCRG_CLK_END 65 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 55209382e00e..a89ba78b9bf8 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -106,4 +106,22 @@ #define SYSCRG_SW_RSTN_DDR_TVSENSOR 3 #define SYSCRG_SW_RESET_NR_RESETS 4 + +/* + * aoncrg + */ +#define AONCRG_RSTN_AON_IOMUX_PRESETN 0 +#define AONCRG_RSTN_RTC 1 +#define AONCRG_RSTN_GMAC0 2 +#define AONCRG_RSTN_XSPI 3 +#define AONCRG_RSTN_TVSENSOR 4 +#define AONCRG_RSTN_MEU 5 +#define AONCRG_RSTN_AXIMEM_128B_ARESET 6 +#define AONCRG_RSTN_APB2BISR_APB 7 +#define AONCRG_RSTN_SDIO0 8 +#define AONCRG_RSTN_EMMC 9 +#define AONCRG_RSTN_TOP 10 +#define AONCRG_RSTN_IRQ_CTRL 11 + +#define AONCRG_RESET_NR_RESETS 12 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */