From patchwork Tue Sep 19 10:56:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 815434 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="mvSo1kHi"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xxKZc6gZcz9sP1 for ; Tue, 19 Sep 2017 20:57:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751431AbdISK5L (ORCPT ); Tue, 19 Sep 2017 06:57:11 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:9970 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751450AbdISK5K (ORCPT ); Tue, 19 Sep 2017 06:57:10 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8JAuEmX016474; Tue, 19 Sep 2017 05:56:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1505818574; bh=k8p/LqUqVDVFSLOJH+ZUps60729d8JHs9HdJk1vHZ9c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mvSo1kHi4A0iKrVp/Ee4k962o/hZCof88+yYCvxj5KbmkFZyF5v4KezafXN6ZoEWN P9Go4OIwCkNYRYFilArdWJfMtD4nYJm/Z/Oqc54AVZtRCcF9q0Y6rSbp19mhv25m/P bI/a1aYS1jUh/024TFULx+/c93BmGizKAzHwiNF8= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAuEwv008809; Tue, 19 Sep 2017 05:56:14 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 19 Sep 2017 05:56:13 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 19 Sep 2017 05:56:13 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAu6Rd022115; Tue, 19 Sep 2017 05:56:10 -0500 From: Vignesh R To: Marek Vasut , Cyrille Pitchen CC: David Woodhouse , Brian Norris , Boris Brezillon , Rob Herring , , , , Vignesh R , linux-arm-kernel Subject: [RESEND PATCH v2 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Date: Tue, 19 Sep 2017 16:26:01 +0530 Message-ID: <20170919105605.18533-2-vigneshr@ti.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170919105605.18533-1-vigneshr@ti.com> References: <20170919105605.18533-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update binding documentation to add a new compatible for TI 66AK2G SoC, to handle TI SoC specific quirks in the driver. Signed-off-by: Vignesh R Acked-by: Rob Herring --- Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index f248056da24c..7dbe3bd9ac56 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -1,7 +1,9 @@ * Cadence Quad SPI controller Required properties: -- compatible : Should be "cdns,qspi-nor". +- compatible : should be one of the following: + Generic default - "cdns,qspi-nor". + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the From patchwork Tue Sep 19 10:56:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 815436 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="HKBA/iX5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xxKbT1gxRz9s7m for ; Tue, 19 Sep 2017 20:57:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751698AbdISK53 (ORCPT ); Tue, 19 Sep 2017 06:57:29 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:48848 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751624AbdISK5Z (ORCPT ); Tue, 19 Sep 2017 06:57:25 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8JAuLQ4012189; Tue, 19 Sep 2017 05:56:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1505818581; bh=uI+4+QRwxXE07v/9ifxsyixDo7u2QnF00OF4Wf40I3o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HKBA/iX5xBqtBn8cSWwkxHRo1XRVSk0RiWZa2LtWWmR5D9YP3MGI61u4PKJXU7hLE uIF6oFM7dBhxLABPLar5g6WTlnahutM5zwcsdo+eYhCTiU6Ah2m67rnVdw5W7JMqTr cSi+rKDATFMNvUCpZ8kzFW1GgOE/z+MfGUNCGR60= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAuLFG011904; Tue, 19 Sep 2017 05:56:21 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 19 Sep 2017 05:56:20 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 19 Sep 2017 05:56:20 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAu6Rf022115; Tue, 19 Sep 2017 05:56:17 -0500 From: Vignesh R To: Marek Vasut , Cyrille Pitchen CC: David Woodhouse , Brian Norris , Boris Brezillon , Rob Herring , , , , Vignesh R , linux-arm-kernel Subject: [RESEND PATCH v2 3/5] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit Date: Tue, 19 Sep 2017 16:26:03 +0530 Message-ID: <20170919105605.18533-4-vigneshr@ti.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170919105605.18533-1-vigneshr@ti.com> References: <20170919105605.18533-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence QSPI IP has a adapted loop-back circuit which can be enabled by setting BYPASS field to 0 in READCAPTURE register. It enables use of QSPI return clock to latch the data rather than the internal QSPI reference clock. For high speed operations, adapted loop-back circuit using QSPI return clock helps to increase data valid window. Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit for boards which do have QSPI return clock provided. Update binding documentation for the same. Signed-off-by: Vignesh R Acked-by: Rob Herring --- Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index 7dbe3bd9ac56..bb2075df9b38 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -16,6 +16,9 @@ Required properties: Optional properties: - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. +- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch + the read data rather than the QSPI clock. Make sure that QSPI return + clock is populated on the board before using this property. Optional subnodes: Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional