From patchwork Tue Sep 19 10:53:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815432 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKYy3S1jz9sBZ for ; Tue, 19 Sep 2017 20:56:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 438A8C21EFE; Tue, 19 Sep 2017 10:54:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: **** X-Spam-Status: No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 92E7FC21F26; Tue, 19 Sep 2017 10:54:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C419EC21F1A; Tue, 19 Sep 2017 10:54:29 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133]) by lists.denx.de (Postfix) with ESMTPS id B8939C21F1A for ; Tue, 19 Sep 2017 10:54:26 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.153]) by lucky1.263xmail.com (Postfix) with ESMTP id 6C9B28F80A; Tue, 19 Sep 2017 18:54:22 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 257483AA; Tue, 19 Sep 2017 18:54:22 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <59836ec7a66eb3b758a5ad2174179c46> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 8576BX6V0; Tue, 19 Sep 2017 18:54:23 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:53:12 +0800 Message-Id: <1505818405-49082-2-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot,v2,01/14] adc: Add driver for Rockchip SARADC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The ADC can support some channels signal-ended some bits Successive Approximation Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog input signal into some bits binary digital codes. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - Order the the include file. - Use structures for I/O access. - Use dev_read_add. drivers/adc/Kconfig | 9 +++ drivers/adc/Makefile | 1 + drivers/adc/rockchip-saradc.c | 183 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/adc/rockchip-saradc.c diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index e5335f7..8094420 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -28,3 +28,12 @@ config ADC_SANDBOX - 4 analog input channels - 16-bit resolution - single and multi-channel conversion mode + +config SARADC_ROCKCHIP + bool "Enable Rockchip SARADC driver" + help + This enables driver for Rockchip SARADC. + It provides: + - 2~6 analog input channels + - 1O or 12 bits resolution + - Up to 1MSPS of sample rate diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index cebf26d..4b5aa69 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_ADC) += adc-uclass.o obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o obj-$(CONFIG_ADC_SANDBOX) += sandbox.o +obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c new file mode 100644 index 0000000..0e6271d --- /dev/null +++ b/drivers/adc/rockchip-saradc.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Rockchip SARADC driver for U-Boot + */ + +#include +#include +#include +#include +#include +#include + +#define SARADC_CTRL_CHN_MASK GENMASK(2, 0) +#define SARADC_CTRL_POWER_CTRL BIT(3) +#define SARADC_CTRL_IRQ_ENABLE BIT(5) +#define SARADC_CTRL_IRQ_STATUS BIT(6) + +#define SARADC_TIMEOUT (100 * 1000) + +struct rockchip_saradc_regs { + unsigned int data; + unsigned int stas; + unsigned int ctrl; + unsigned int dly_pu_soc; +}; + +struct rockchip_saradc_data { + int num_bits; + int num_channels; + unsigned long clk_rate; +}; + +struct rockchip_saradc_priv { + struct rockchip_saradc_regs *regs; + int active_channel; + const struct rockchip_saradc_data *data; +}; + +int rockchip_saradc_channel_data(struct udevice *dev, int channel, + unsigned int *data) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + + if (channel != priv->active_channel) { + error("Requested channel is not active!"); + return -EINVAL; + } + + if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) != + SARADC_CTRL_IRQ_STATUS) + return -EBUSY; + + /* Read value */ + *data = readl(&priv->regs->data); + *data &= uc_pdata->data_mask; + + /* Power down adc */ + writel(0, &priv->regs->ctrl); + + return 0; +} + +int rockchip_saradc_start_channel(struct udevice *dev, int channel) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + if (channel < 0 || channel >= priv->data->num_channels) { + error("Requested channel is invalid!"); + return -EINVAL; + } + + /* 8 clock periods as delay between power up and start cmd */ + writel(8, &priv->regs->dly_pu_soc); + + /* Select the channel to be used and trigger conversion */ + writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) | + SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl); + + priv->active_channel = channel; + + return 0; +} + +int rockchip_saradc_stop(struct udevice *dev) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + /* Power down adc */ + writel(0, &priv->regs->ctrl); + + priv->active_channel = -1; + + return 0; +} + +int rockchip_saradc_probe(struct udevice *dev) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_set_rate(&clk, priv->data->clk_rate); + if (IS_ERR_VALUE(ret)) + return ret; + + priv->active_channel = -1; + + return 0; +} + +int rockchip_saradc_ofdata_to_platdata(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + struct rockchip_saradc_data *data; + + data = (struct rockchip_saradc_data *)dev_get_driver_data(dev); + priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev); + if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) { + error("Dev: %s - can't get address!", dev->name); + return -ENODATA; + } + + priv->data = data; + uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; + uc_pdata->data_format = ADC_DATA_FORMAT_BIN; + uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; + uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; + + return 0; +} + +static const struct adc_ops rockchip_saradc_ops = { + .start_channel = rockchip_saradc_start_channel, + .channel_data = rockchip_saradc_channel_data, + .stop = rockchip_saradc_stop, +}; + +static const struct rockchip_saradc_data saradc_data = { + .num_bits = 10, + .num_channels = 3, + .clk_rate = 1000000, +}; + +static const struct rockchip_saradc_data rk3066_tsadc_data = { + .num_bits = 12, + .num_channels = 2, + .clk_rate = 50000, +}; + +static const struct rockchip_saradc_data rk3399_saradc_data = { + .num_bits = 10, + .num_channels = 6, + .clk_rate = 1000000, +}; + +static const struct udevice_id rockchip_saradc_ids[] = { + { .compatible = "rockchip,saradc", + .data = (ulong)&saradc_data }, + { .compatible = "rockchip,rk3066-tsadc", + .data = (ulong)&rk3066_tsadc_data }, + { .compatible = "rockchip,rk3399-saradc", + .data = (ulong)&rk3399_saradc_data }, + { } +}; + +U_BOOT_DRIVER(rockchip_saradc) = { + .name = "rockchip_saradc", + .id = UCLASS_ADC, + .of_match = rockchip_saradc_ids, + .ops = &rockchip_saradc_ops, + .probe = rockchip_saradc_probe, + .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv), +}; From patchwork Tue Sep 19 10:53:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815431 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKYx6Dnsz9s7m for ; Tue, 19 Sep 2017 20:56:37 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A2BE8C21F2A; Tue, 19 Sep 2017 10:55:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: **** X-Spam-Status: No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BEE79C21F03; Tue, 19 Sep 2017 10:54:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1C2C5C21DA1; Tue, 19 Sep 2017 10:54:48 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.130]) by lists.denx.de (Postfix) with ESMTPS id 122AEC21F31 for ; Tue, 19 Sep 2017 10:54:42 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.153]) by lucky1.263xmail.com (Postfix) with ESMTP id D65F71EF1B3; Tue, 19 Sep 2017 18:54:37 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 48197387; Tue, 19 Sep 2017 18:54:38 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <4ee7268fe7178e7a446eab3a2c737621> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 857CQANH2; Tue, 19 Sep 2017 18:54:39 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:53:13 +0800 Message-Id: <1505818405-49082-3-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 02/14] configs: rockchip: Enable the ROCKCHIP_SARADC config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Except for 3036 and 3228 Socs, which don't support SARADC, enable the ROCKCHIP_SARADC config at the other Socs' defconfig. Signed-off-by: David Wu --- Change in v2: - Enable the ROCKCHIP_SARADC at other configs configs/chromebit_mickey_defconfig | 2 ++ configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/evb-px5_defconfig | 2 ++ configs/evb-rk3288_defconfig | 2 ++ configs/evb-rk3328_defconfig | 2 ++ configs/evb-rk3399_defconfig | 2 ++ configs/evb-rv1108_defconfig | 2 ++ configs/fennec-rk3288_defconfig | 2 ++ configs/firefly-rk3288_defconfig | 2 ++ configs/firefly-rk3399_defconfig | 2 ++ configs/geekbox_defconfig | 2 ++ configs/lion-rk3368_defconfig | 2 ++ configs/miqi-rk3288_defconfig | 2 ++ configs/phycore-rk3288_defconfig | 2 ++ configs/popmetal-rk3288_defconfig | 2 ++ configs/puma-rk3399_defconfig | 2 ++ configs/rock2_defconfig | 2 ++ configs/rock_defconfig | 2 ++ configs/sheep-rk3368_defconfig | 2 ++ configs/tinker-rk3288_defconfig | 2 ++ 21 files changed, 42 insertions(+) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index f40c0b9..e84706d 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index cdeabaa..f612d31 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -42,6 +42,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index c1e36fa..38a4b42 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -41,6 +41,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 4323b77..cbf467f 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -13,6 +13,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 5294ba9..f09b769 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -37,6 +37,8 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 7bec001..b44b029 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_MMC_DW=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7a0bd4a..6d0d1a0 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -30,6 +30,8 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index ab4276a..3278104 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -13,6 +13,8 @@ CONFIG_CMD_TIME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 96a07de..913849e 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 82da601..75f8cdb 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 94b9209..e9e4324 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -30,6 +30,8 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 19255fb..a270515 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -9,6 +9,8 @@ CONFIG_DEBUG_UART=y # CONFIG_CMD_IMLS is not set CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3368=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 45a12a8..5ef6d4b 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -52,6 +52,8 @@ CONFIG_TPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y CONFIG_TPL_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_TPL_CLK=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index b0437e1..7825467 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 93ee353..911600d 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -42,6 +42,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 5e99f9c..9f5d78d 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 1badf80..7929a69 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -41,6 +41,8 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index b41644e..7d91b68 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -39,6 +39,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index aaf2775..33418ea 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -29,6 +29,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index b862a14..d4877d3 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -10,6 +10,8 @@ CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_CMD_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 00e2d81..e7eba10 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -41,6 +41,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y From patchwork Tue Sep 19 10:53:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815433 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKZ76xpFz9sBZ for ; Tue, 19 Sep 2017 20:56:47 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A340BC21F44; Tue, 19 Sep 2017 10:55:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: **** X-Spam-Status: No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A9644C21F03; Tue, 19 Sep 2017 10:55:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0845CC21EFB; Tue, 19 Sep 2017 10:54:52 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.130]) by lists.denx.de (Postfix) with ESMTPS id 21982C21F06 for ; Tue, 19 Sep 2017 10:54:47 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.153]) by lucky1.263xmail.com (Postfix) with ESMTP id A91B41EF2ED; Tue, 19 Sep 2017 18:54:42 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id B8189387; Tue, 19 Sep 2017 18:54:40 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 857DD46IG; Tue, 19 Sep 2017 18:54:43 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:53:14 +0800 Message-Id: <1505818405-49082-4-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 03/14] clk: rockchip: Add rv1108 SARADC clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Change in v2: - Use extract_bits. arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 ++++ drivers/clk/rockchip/clk_rv1108.c | 33 ++++++++++++++++++++++++- include/dt-bindings/clock/rv1108-cru.h | 2 ++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h index 2a1ae69..ad2dc96 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -90,6 +90,11 @@ enum { CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + /* CLKSEL_CON22 */ + CLK_SARADC_DIV_CON_SHIFT= 0, + CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), + CLK_SARADC_DIV_CON_WIDTH= 10, + /* CLKSEL24_CON */ MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index cf966bb..86e73e4 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -36,7 +37,7 @@ enum { #hz "Hz cannot be hit with PLL "\ "divisors on line " __stringify(__LINE__)); -/* use interge mode*/ +/* use integer mode */ static inline int rv1108_pll_id(enum rk_clk_id clk_id) { int id = 0; @@ -130,6 +131,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) return DIV_TO_RATE(pll_rate, div); } +static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[22]); + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[22], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rv1108_saradc_get_clk(cru); +} + static ulong rv1108_clk_get_rate(struct clk *clk) { struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); @@ -137,6 +163,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk) switch (clk->id) { case 0 ... 63: return rkclk_pll_get_rate(priv->cru, clk->id); + case SCLK_SARADC: + return rv1108_saradc_get_clk(priv->cru); default: return -ENOENT; } @@ -154,6 +182,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SFC: new_rate = rv1108_sfc_set_clk(priv->cru, rate); break; + case SCLK_SARADC: + new_rate = rv1108_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h index d2ad3bb..7defc6b 100644 --- a/include/dt-bindings/clock/rv1108-cru.h +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -39,6 +39,7 @@ #define SCLK_MAC_TX 88 #define SCLK_MACREF 89 #define SCLK_MACREF_OUT 90 +#define SCLK_SARADC 91 /* aclk gates */ @@ -67,6 +68,7 @@ #define PCLK_TIMER 270 #define PCLK_PERI 271 #define PCLK_GMAC 272 +#define PCLK_SARADC 273 /* hclk gates */ #define HCLK_I2S0_8CH 320 From patchwork Tue Sep 19 10:53:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815435 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKZk0Pf9z9sBZ for ; Tue, 19 Sep 2017 20:57:17 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 29404C21F44; Tue, 19 Sep 2017 10:56:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.9 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L4,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 963BCC21EFB; Tue, 19 Sep 2017 10:56:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 22406C21F3D; Tue, 19 Sep 2017 10:54:55 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.134]) by lists.denx.de (Postfix) with ESMTPS id E1BFEC21F19 for ; Tue, 19 Sep 2017 10:54:50 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.153]) by lucky1.263xmail.com (Postfix) with ESMTP id 58BE6163B; Tue, 19 Sep 2017 18:54:47 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 4BF983AA; Tue, 19 Sep 2017 18:54:44 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <3c5ef4fbd02198ee5ab6d911881cda49> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 857BXWEW6; Tue, 19 Sep 2017 18:54:47 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:53:15 +0800 Message-Id: <1505818405-49082-5-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 04/14] clk: rockchip: Add SARADC clock support for rk3288 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu Reviewed-by: Philipp Tomsich Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- Change in v2: - Use extract_bits. drivers/clk/rockchip/clk_rk3288.c | 41 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 478195b..a133810 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -111,6 +112,15 @@ enum { PERI_ACLK_DIV_SHIFT = 0, PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + /* + * CLKSEL24 + * saradc_div_con: + * clk_saradc=24MHz/(saradc_div_con+1) + */ + CLK_SARADC_DIV_CON_SHIFT = 8, + CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), + CLK_SARADC_DIV_CON_WIDTH = 8, + SOCSTS_DPLL_LOCK = 1 << 5, SOCSTS_APLL_LOCK = 1 << 6, SOCSTS_CPLL_LOCK = 1 << 7, @@ -634,6 +644,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, return rockchip_spi_get_clk(cru, gclk_rate, periph); } +static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) +{ + u32 div, val; + + val = readl(&cru->cru_clksel_con[24]); + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->cru_clksel_con[24], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rockchip_saradc_get_clk(cru); +} + static ulong rk3288_clk_get_rate(struct clk *clk) { struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); @@ -666,6 +701,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk) return gclk_rate; case PCLK_PWM: return PD_BUS_PCLK_HZ; + case SCLK_SARADC: + new_rate = rockchip_saradc_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -756,6 +794,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) new_rate = rate; break; #endif + case SCLK_SARADC: + new_rate = rockchip_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } From patchwork Tue Sep 19 10:57:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKbk2dlPz9sBZ for ; Tue, 19 Sep 2017 20:58:10 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0A35EC21F29; Tue, 19 Sep 2017 10:57:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 19D9BC21F00; Tue, 19 Sep 2017 10:57:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B3A9AC21F00; Tue, 19 Sep 2017 10:57:54 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Tue, 19 Sep 2017 10:57:54 +0000 From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:57:10 +0800 Message-Id: <1505818630-49239-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 05/14] clk: rockchip: Add rk3328 SARADC clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- [...] Content analysis details: (6.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 1.2 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net [Blocked - see ] 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.135 listed in psbl.surriel.com] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.135 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Change in v2: - Use extract_bits. drivers/clk/rockchip/clk_rk3328.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index c3a6650..540d910 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -114,7 +115,8 @@ enum { /* CLKSEL_CON23 */ CLK_SARADC_DIV_CON_SHIFT = 0, - CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), + CLK_SARADC_DIV_CON_WIDTH = 10, /* CLKSEL_CON24 */ CLK_PWM_PLL_SEL_CPLL = 0, @@ -478,6 +480,31 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) return DIV_TO_RATE(GPLL_HZ, div); } +static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[23]); + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[23], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rk3328_saradc_get_clk(cru); +} + static ulong rk3328_clk_get_rate(struct clk *clk) { struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); @@ -501,6 +528,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case SCLK_PWM: rate = rk3328_pwm_get_clk(priv->cru); break; + case SCLK_SARADC: + rate = rk3328_saradc_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -531,6 +561,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_PWM: ret = rk3328_pwm_set_clk(priv->cru, rate); break; + case SCLK_SARADC: + ret = rk3328_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } From patchwork Tue Sep 19 10:58:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815440 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKdQ5yKpz9s7m for ; Tue, 19 Sep 2017 20:59:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 97CBCC21FB4; Tue, 19 Sep 2017 10:59:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: **** X-Spam-Status: No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6EA6DC21F10; Tue, 19 Sep 2017 10:59:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 08F56C21F10; Tue, 19 Sep 2017 10:59:04 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133]) by lists.denx.de (Postfix) with ESMTPS id F1373C21FAA for ; Tue, 19 Sep 2017 10:59:03 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.223]) by lucky1.263xmail.com (Postfix) with ESMTP id 1A94A8F7A3; Tue, 19 Sep 2017 18:59:00 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 194B0369; Tue, 19 Sep 2017 18:58:59 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 27406I6GNIU; Tue, 19 Sep 2017 18:59:01 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:58:21 +0800 Message-Id: <1505818701-49308-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 06/14] clk: rockchip: Add rk3368 SARADC clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Change in v2: - Use GENMASK. arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++ drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 2b1197f..5f6a5fb 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -89,6 +89,11 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL_CON25 */ + CLK_SARADC_DIV_CON_SHIFT = 8, + CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), + CLK_SARADC_DIV_CON_WIDTH = 8, + /* CLKSEL43_CON */ GMAC_MUX_SEL_EXTCLK = BIT(8), diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 2be1f57..2eedf77 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) return rk3368_spi_get_clk(cru, clk_id); } +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[25]); + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[25], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rk3368_saradc_get_clk(cru); +} + static ulong rk3368_clk_get_rate(struct clk *clk) { struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); @@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk) rate = rk3368_mmc_get_clk(priv->cru, clk->id); break; #endif + case SCLK_SARADC: + rate = rk3368_saradc_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate); break; #endif + case SCLK_SARADC: + ret = rk3368_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } From patchwork Tue Sep 19 10:59:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815441 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKfV3f8fz9s7m for ; Tue, 19 Sep 2017 21:00:34 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2FF38C21FCD; Tue, 19 Sep 2017 11:00:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9F301C21F22; Tue, 19 Sep 2017 11:00:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BE5FBC21F22; Tue, 19 Sep 2017 11:00:18 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Tue, 19 Sep 2017 11:00:18 +0000 From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:59:29 +0800 Message-Id: <1505818769-49370-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 07/14] clk: rockchip: Add rk3399 SARADC clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- [...] Content analysis details: (6.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 1.2 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net [Blocked - see ] 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.135 listed in psbl.surriel.com] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.135 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Change in v2: - Use GENMASK. drivers/clk/rockchip/clk_rk3399.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 3edafea..105c499 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -181,7 +182,8 @@ enum { /* CLKSEL_CON26 */ CLK_SARADC_DIV_CON_SHIFT = 8, - CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), + CLK_SARADC_DIV_CON_WIDTH = 8, /* CLKSEL_CON27 */ CLK_TSADC_SEL_X24M = 0x0, @@ -860,6 +862,32 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, return set_rate; } + +static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[26]); + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[26], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rk3399_saradc_get_clk(cru); +} + static ulong rk3399_clk_get_rate(struct clk *clk) { struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); @@ -895,6 +923,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) break; case PCLK_EFUSE1024NS: break; + case SCLK_SARADC: + rate = rk3399_saradc_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -943,6 +974,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) break; case PCLK_EFUSE1024NS: break; + case SCLK_SARADC: + ret = rk3399_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } From patchwork Tue Sep 19 11:00:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815444 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKgj15twz9rxj for ; Tue, 19 Sep 2017 21:01:37 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D8488C22029; Tue, 19 Sep 2017 11:01:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: **** X-Spam-Status: No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7A839C21F94; Tue, 19 Sep 2017 11:01:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4EB0EC21FF6; Tue, 19 Sep 2017 11:01:29 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133]) by lists.denx.de (Postfix) with ESMTPS id BAC49C21F94 for ; Tue, 19 Sep 2017 11:01:28 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.232]) by lucky1.263xmail.com (Postfix) with ESMTP id BA0F58F833; Tue, 19 Sep 2017 19:01:24 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id D9A2A360; Tue, 19 Sep 2017 19:01:24 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <341b967e843ee7e66e54b0883be426b2> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 31362YTJ3JS; Tue, 19 Sep 2017 19:01:26 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 19:00:44 +0800 Message-Id: <1505818844-49433-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 08/14] arm: dts: rv1108: Add SARADC node at dtsi level X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/dts/rv1108.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi index 77ca24e..d6927ee 100644 --- a/arch/arm/dts/rv1108.dtsi +++ b/arch/arm/dts/rv1108.dtsi @@ -126,6 +126,17 @@ reg = <0x10300000 0x1000>; }; + saradc: saradc@1038c000 { + compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; + reg = <0x1038c000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clock-frequency = <1000000>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + pmugrf: syscon@20060000 { compatible = "rockchip,rv1108-pmugrf", "syscon"; reg = <0x20060000 0x1000>; From patchwork Tue Sep 19 11:02:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815446 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKjb10RHz9rxj for ; Tue, 19 Sep 2017 21:03:13 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id EDC47C2201C; Tue, 19 Sep 2017 11:03:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.9 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L4,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 88D05C21F94; Tue, 19 Sep 2017 11:02:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3CB37C21F94; Tue, 19 Sep 2017 11:02:57 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.134]) by lists.denx.de (Postfix) with ESMTPS id A67DAC21F2D for ; Tue, 19 Sep 2017 11:02:56 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.223]) by lucky1.263xmail.com (Postfix) with ESMTP id 3836F15DE; Tue, 19 Sep 2017 19:02:53 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 6B3053AC; Tue, 19 Sep 2017 19:02:50 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <3c22d7597351c0618a9f1d900a6100bb> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 30163JJ11JR; Tue, 19 Sep 2017 19:02:52 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 19:02:02 +0800 Message-Id: <1505818922-49500-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot,v2,09/14] arm: dts: Enable SARADC for rv1108-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: David Wu --- arch/arm/dts/rv1108-evb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts index 0128dd8..e21b57f 100644 --- a/arch/arm/dts/rv1108-evb.dts +++ b/arch/arm/dts/rv1108-evb.dts @@ -30,6 +30,10 @@ snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; }; +&saradc { + status = "okay"; +}; + &sfc { status = "okay"; flash@0 { From patchwork Tue Sep 19 11:04:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815455 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKqS0Cynz9rxj for ; Tue, 19 Sep 2017 21:08:19 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 43DC1C21F6F; Tue, 19 Sep 2017 11:08:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: **** X-Spam-Status: No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 29D75C21F12; Tue, 19 Sep 2017 11:08:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 73B17C21F12; Tue, 19 Sep 2017 11:08:09 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.130]) by lists.denx.de (Postfix) with ESMTPS id 10AF6C21F06 for ; Tue, 19 Sep 2017 11:08:07 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.161]) by lucky1.263xmail.com (Postfix) with ESMTP id 7FF391EF485; Tue, 19 Sep 2017 19:04:45 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 3416E308; Tue, 19 Sep 2017 19:04:45 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 41106YBHSM; Tue, 19 Sep 2017 19:04:46 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 19:04:06 +0800 Message-Id: <1505819046-49585-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 10/14] arm: dts: Enable SARADC for rk3288-popmetal X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: David Wu --- arch/arm/dts/rk3288-popmetal.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi index dd6ce8b..63785eb 100644 --- a/arch/arm/dts/rk3288-popmetal.dtsi +++ b/arch/arm/dts/rk3288-popmetal.dtsi @@ -491,6 +491,10 @@ }; }; +&saradc { + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; From patchwork Tue Sep 19 11:05:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815463 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxL2t5Nn7z9s7m for ; Tue, 19 Sep 2017 21:18:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3DE7FC21F9E; Tue, 19 Sep 2017 11:18:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: **** X-Spam-Status: No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DB7A4C21F3E; Tue, 19 Sep 2017 11:18:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D7649C21F3E; Tue, 19 Sep 2017 11:18:05 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133]) by lists.denx.de (Postfix) with ESMTPS id 5EF0CC21F29 for ; Tue, 19 Sep 2017 11:18:05 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.76]) by lucky1.263xmail.com (Postfix) with ESMTP id B9AEF8F8F4; Tue, 19 Sep 2017 19:05:46 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 5097A323; Tue, 19 Sep 2017 19:05:46 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <12df9418835349dc1955b8d986d542b1> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 79482P1ZUC; Tue, 19 Sep 2017 19:05:47 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 19:05:08 +0800 Message-Id: <1505819108-49649-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot,v2,11/14] arm: dts: Enable SARADC for rk3328-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: David Wu --- arch/arm/dts/rk3328-evb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 8a14c65..df44ccb 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -42,6 +42,10 @@ }; }; +&saradc { + status = "okay"; +}; + &uart2 { status = "okay"; }; From patchwork Tue Sep 19 11:08:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815456 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKrt4Dh4z9rxj for ; Tue, 19 Sep 2017 21:09:34 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3DA35C21F3F; Tue, 19 Sep 2017 11:09:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.9 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L4,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 424F9C21F12; Tue, 19 Sep 2017 11:09:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6CE63C21F12; Tue, 19 Sep 2017 11:09:29 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id 2B612C21F06 for ; Tue, 19 Sep 2017 11:09:28 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.152]) by lucky1.263xmail.com (Postfix) with ESMTP id 7231B8FBB3; Tue, 19 Sep 2017 19:09:11 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id B9C66359; Tue, 19 Sep 2017 19:09:10 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 6577ZROKHG; Tue, 19 Sep 2017 19:09:11 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 19:08:33 +0800 Message-Id: <1505819313-49837-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot,v2,14/14] arm: dts: Enable SARADC for rk3399-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: David Wu --- arch/arm/dts/rk3399-evb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index be0c6d9..0e5d8d7 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -149,6 +149,10 @@ status = "okay"; }; +&saradc { + status = "okay"; +}; + &sdmmc { bus-width = <4>; status = "okay";