From patchwork Mon Oct 23 09:19:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahao Xu X-Patchwork-Id: 1853580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDV5R60Fxz23jV for ; Mon, 23 Oct 2023 20:19:55 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A75023858410 for ; Mon, 23 Oct 2023 09:19:53 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 428683858D37 for ; Mon, 23 Oct 2023 09:19:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 428683858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 428683858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698052780; cv=none; b=quexaeT7xEZfbj2jpKzS1sMRA4/w9ATBZm0s1pZFy3R7egUrt1Obhs+dL8dBDFtRqXIdAh1GJPpLqMDVXV7oSe1lMfrEuQ9oqxozEqGCYKt3KmH1Z7qEYJc/pKyFfKKe9MheivNcbj1iXacD3RTnWnlIv52sy9894EZMoK5wL8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698052780; c=relaxed/simple; bh=EKucnaGA8bhwRxRIA9YSVCiIUKdFE7Scra59lpPvCgs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=m/OdmjiFD15Ul/bUKJBFjHbG7aT3Fb9k+jwYmZqz/ie37bGTaufEGwLrezeGaapsYGlJe9A81qOiH1ECOR5e+xtPz5XXzcb/nXKdLsp+nbncMq9eSfKw9T5otR+WvXids3MU13X9x88/ErcXMhzK+I2BjOIOoD3jMxLr2V78JKk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qur5x-0001h8-2e for gcc-patches@gcc.gnu.org; Mon, 23 Oct 2023 05:19:36 -0400 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8BxXeuZOjZlJeozAA--.30316S3; Mon, 23 Oct 2023 17:19:23 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx3y+WOjZlmSMvAA--.34492S4; Mon, 23 Oct 2023 17:19:18 +0800 (CST) From: Jiahao Xu To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn, Jiahao Xu Subject: [PATCH] LoongArch:Enable vcond_mask_mn expanders for SF/DF modes. Date: Mon, 23 Oct 2023 17:19:15 +0800 Message-Id: <20231023091915.385-1-xujiahao@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bx3y+WOjZlmSMvAA--.34492S4 X-CM-SenderInfo: 50xmxthkdrqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoW3Ary7tr4xXw45urW7Cr48GrX_yoWfXF4Dp3 y7Xa4jvrWfGan7G3WkJFW5Jw42yrsrt34I9F9xWrWjya4Yqw1Ig34DKFW7Gr42yw43JrW2 qF48Gw42gwnxJ3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVWxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1wL05UUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=xujiahao@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-14.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org If the vcond_mask patterns don't support fp modes, the vector FP comparison instructions will not be generated. gcc/ChangeLog: * config/loongarch/lasx.md (vcond_mask_): Change to (vcond_mask_): this. * config/loongarch/lsx.md (vcond_mask_): Change to (vcond_mask_): this. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vcond-1.c: New test. * gcc.target/loongarch/vcond-2.c: Ditto. Change-Id: If9716f356c0b83748a208235e835feb402b5c78f diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 442fda24606..ba2c5eec7d0 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -906,15 +906,15 @@ (define_expand "vcond" }) ;; Same as vcond_ -(define_expand "vcond_mask_" - [(match_operand:ILASX 0 "register_operand") - (match_operand:ILASX 1 "reg_or_m1_operand") - (match_operand:ILASX 2 "reg_or_0_operand") - (match_operand:ILASX 3 "register_operand")] +(define_expand "vcond_mask_" + [(match_operand:LASX 0 "register_operand") + (match_operand:LASX 1 "reg_or_m1_operand") + (match_operand:LASX 2 "reg_or_0_operand") + (match_operand: 3 "register_operand")] "ISA_HAS_LASX" { - loongarch_expand_vec_cond_mask_expr (mode, - mode, operands); + loongarch_expand_vec_cond_mask_expr (mode, + mode, operands); DONE; }) diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index b4e92ae9c54..7e77ac4ad6a 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -644,15 +644,15 @@ (define_expand "vcond" DONE; }) -(define_expand "vcond_mask_" - [(match_operand:ILSX 0 "register_operand") - (match_operand:ILSX 1 "reg_or_m1_operand") - (match_operand:ILSX 2 "reg_or_0_operand") - (match_operand:ILSX 3 "register_operand")] +(define_expand "vcond_mask_" + [(match_operand:LSX 0 "register_operand") + (match_operand:LSX 1 "reg_or_m1_operand") + (match_operand:LSX 2 "reg_or_0_operand") + (match_operand: 3 "register_operand")] "ISA_HAS_LSX" { - loongarch_expand_vec_cond_mask_expr (mode, - mode, operands); + loongarch_expand_vec_cond_mask_expr (mode, + mode, operands); DONE; }) diff --git a/gcc/testsuite/gcc.target/loongarch/vcond-1.c b/gcc/testsuite/gcc.target/loongarch/vcond-1.c new file mode 100644 index 00000000000..57064eac9dc --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vcond-1.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-unroll-loops -fno-vect-cost-model -mlasx" } */ + +#include + +#define DEF_VCOND_VAR(DATA_TYPE, CMP_TYPE, COND, SUFFIX) \ + void __attribute__ ((noinline, noclone)) \ + vcond_var_##CMP_TYPE##_##SUFFIX (DATA_TYPE *__restrict__ r, \ + DATA_TYPE *__restrict__ x, \ + DATA_TYPE *__restrict__ y, \ + CMP_TYPE *__restrict__ a, \ + CMP_TYPE *__restrict__ b, \ + int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + DATA_TYPE xval = x[i], yval = y[i]; \ + CMP_TYPE aval = a[i], bval = b[i]; \ + r[i] = aval COND bval ? xval : yval; \ + } \ + } + +#define TEST_COND_VAR_SIGNED_ALL(T, COND, SUFFIX) \ + T (int8_t, int8_t, COND, SUFFIX) \ + T (int16_t, int16_t, COND, SUFFIX) \ + T (int32_t, int32_t, COND, SUFFIX) \ + T (int64_t, int64_t, COND, SUFFIX) \ + T (float, int32_t, COND, SUFFIX##_float) \ + T (double, int64_t, COND, SUFFIX##_double) + +#define TEST_COND_VAR_UNSIGNED_ALL(T, COND, SUFFIX) \ + T (uint8_t, uint8_t, COND, SUFFIX) \ + T (uint16_t, uint16_t, COND, SUFFIX) \ + T (uint32_t, uint32_t, COND, SUFFIX) \ + T (uint64_t, uint64_t, COND, SUFFIX) \ + T (float, uint32_t, COND, SUFFIX##_float) \ + T (double, uint64_t, COND, SUFFIX##_double) + +#define TEST_COND_VAR_ALL(T, COND, SUFFIX) \ + TEST_COND_VAR_SIGNED_ALL (T, COND, SUFFIX) \ + TEST_COND_VAR_UNSIGNED_ALL (T, COND, SUFFIX) + +#define TEST_VAR_ALL(T) \ + TEST_COND_VAR_ALL (T, >, _gt) \ + TEST_COND_VAR_ALL (T, <, _lt) \ + TEST_COND_VAR_ALL (T, >=, _ge) \ + TEST_COND_VAR_ALL (T, <=, _le) \ + TEST_COND_VAR_ALL (T, ==, _eq) \ + TEST_COND_VAR_ALL (T, !=, _ne) + +TEST_VAR_ALL (DEF_VCOND_VAR) + +/* { dg-final { scan-assembler-times {\txvslt\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\txvslt\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\txvslt\.w} 8 } } */ +/* { dg-final { scan-assembler-times {\txvslt\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.w} 8 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.w} 8 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.d} 8 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vcond-2.c b/gcc/testsuite/gcc.target/loongarch/vcond-2.c new file mode 100644 index 00000000000..55d5a084c88 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vcond-2.c @@ -0,0 +1,87 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -mlasx" } */ + +#include + +#define eq(A, B) ((A) == (B)) +#define ne(A, B) ((A) != (B)) +#define olt(A, B) ((A) < (B)) +#define ole(A, B) ((A) <= (B)) +#define oge(A, B) ((A) >= (B)) +#define ogt(A, B) ((A) > (B)) +#define ordered(A, B) (!__builtin_isunordered (A, B)) +#define unordered(A, B) (__builtin_isunordered (A, B)) +#define ueq(A, B) (!__builtin_islessgreater (A, B)) +#define ult(A, B) (__builtin_isless (A, B)) +#define ule(A, B) (__builtin_islessequal (A, B)) +#define uge(A, B) (__builtin_isgreaterequal (A, B)) +#define ugt(A, B) (__builtin_isgreater (A, B)) +#define nueq(A, B) (__builtin_islessgreater (A, B)) +#define nult(A, B) (!__builtin_isless (A, B)) +#define nule(A, B) (!__builtin_islessequal (A, B)) +#define nuge(A, B) (!__builtin_isgreaterequal (A, B)) +#define nugt(A, B) (!__builtin_isgreater (A, B)) + +#define TEST_LOOP(TYPE1, TYPE2, CMP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE1##_##TYPE2##_##CMP##_var (TYPE1 *restrict dest, \ + TYPE1 *restrict src, \ + TYPE1 fallback, \ + TYPE2 *restrict a, \ + TYPE2 *restrict b, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + {\ + TYPE2 aval = a[i]; \ + TYPE2 bval = b[i]; \ + TYPE1 srcval = src[i]; \ + dest[i] = CMP (aval, bval) ? srcval : fallback; \ + }\ + } + +#define TEST_CMP(CMP) \ + TEST_LOOP (int32_t, float, CMP) \ + TEST_LOOP (uint32_t, float, CMP) \ + TEST_LOOP (float, float, CMP) \ + TEST_LOOP (int64_t, double, CMP) \ + TEST_LOOP (uint64_t, double, CMP) \ + TEST_LOOP (double, double, CMP) + +TEST_CMP (eq) +TEST_CMP (ne) +TEST_CMP (olt) +TEST_CMP (ole) +TEST_CMP (oge) +TEST_CMP (ogt) +TEST_CMP (ordered) +TEST_CMP (unordered) +TEST_CMP (ueq) +TEST_CMP (ult) +TEST_CMP (ule) +TEST_CMP (uge) +TEST_CMP (ugt) +TEST_CMP (nueq) +TEST_CMP (nult) +TEST_CMP (nule) +TEST_CMP (nuge) +TEST_CMP (nugt) + +/* { dg-final { scan-assembler-times {\txvfcmp\.ceq\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.ceq\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cne\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cne\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.slt\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.slt\.d} 6 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.sle\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.sle\.d} 6 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cor\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cor\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cun\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cun\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cueq\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cueq\.d} 6 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cule\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cule\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cult\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cult\.d} 12 } } */