From patchwork Mon Oct 23 00:40:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1853443 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-10682-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDGhs37RKz23jV for ; Mon, 23 Oct 2023 11:46:21 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 04CAA28143F for ; Mon, 23 Oct 2023 00:46:20 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E1AF81116; Mon, 23 Oct 2023 00:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68ECC7EB; Mon, 23 Oct 2023 00:46:07 +0000 (UTC) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E1E2E9; Sun, 22 Oct 2023 17:46:04 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39N0iYPY079029; Mon, 23 Oct 2023 08:44:34 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 23 Oct 2023 08:44:31 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 RESEND 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Date: Mon, 23 Oct 2023 08:40:51 +0800 Message-ID: <20231023004100.2663486-5-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023004100.2663486-1-peterlin@andestech.com> References: <20231023004100.2663486-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 39N0iYPY079029 Add "andestech,cpu-intc" compatible string which indicates that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt can be handled in supervisor mode: - Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE. Signed-off-by: Yu Chien Peter Lin --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Updated commit message - Fixed possible compatibles for Andes INTC --- Documentation/devicetree/bindings/riscv/cpus.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 97e8441eda1c..4c1bbcf07406 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -99,7 +99,12 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - enum: + - andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true From patchwork Mon Oct 23 00:40:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1853444 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-10686-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDGj20Hlqz23jV for ; Mon, 23 Oct 2023 11:46:30 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 618F32814DD for ; Mon, 23 Oct 2023 00:46:28 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BE65F7E9; Mon, 23 Oct 2023 00:46:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1710810EF; Mon, 23 Oct 2023 00:46:20 +0000 (UTC) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25700D7E; Sun, 22 Oct 2023 17:46:16 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39N0j0Ah079788; Mon, 23 Oct 2023 08:45:00 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 23 Oct 2023 08:44:56 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 RESEND 09/13] dt-bindings: riscv: Add T-Head PMU extension description Date: Mon, 23 Oct 2023 08:40:56 +0800 Message-ID: <20231023004100.2663486-10-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023004100.2663486-1-peterlin@andestech.com> References: <20231023004100.2663486-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 39N0j0Ah079788 Document the ISA string for T-Head performance monitor extension which provides counter overflow interrupt mechanism. Signed-off-by: Yu Chien Peter Lin --- Changes v2 -> v3: - New patch --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..5e9291d258d5 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -246,5 +246,11 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. + - const: xtheadpmu + description: + The T-Head performance monitor extension for counter overflow. For more + details, see the chapter 12 in the Xuantie C906 user manual. + https://github.com/T-head-Semi/openc906/tree/main/doc + additionalProperties: true ... From patchwork Mon Oct 23 00:40:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1853445 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-10687-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDGjS1kc3z23jV for ; Mon, 23 Oct 2023 11:46:52 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 721AC1C208DB for ; Mon, 23 Oct 2023 00:46:50 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E4D087EB; Mon, 23 Oct 2023 00:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86F3D366; Mon, 23 Oct 2023 00:46:44 +0000 (UTC) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8159D7A; Sun, 22 Oct 2023 17:46:30 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39N0j5YY079922; Mon, 23 Oct 2023 08:45:05 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 23 Oct 2023 08:45:01 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU extension description Date: Mon, 23 Oct 2023 08:40:57 +0800 Message-ID: <20231023004100.2663486-11-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023004100.2663486-1-peterlin@andestech.com> References: <20231023004100.2663486-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 39N0j5YY079922 Document the ISA string for Andes Technology performance monitor extension which provides counter overflow interrupt and mode filtering mechanisms. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v2 -> v3: - New patch --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 5e9291d258d5..e0694e2adbc2 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -246,6 +246,13 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter overflow + and privilege mode filtering. For more details, see Counter Related + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + - const: xtheadpmu description: The T-Head performance monitor extension for counter overflow. For more