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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:30 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 04/19] dt-bindings: riscv: add scalar crypto ISA extensions description Date: Tue, 17 Oct 2023 15:14:41 +0200 Message-ID: <20231017131456.2053396-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add description for scalar crypto ISA extensions which can now be reported through hwprobe for userspace usage. These extensions are the following: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zkr - Zksed - Zksh - Zkt Signed-off-by: Clément Léger --- .../devicetree/bindings/riscv/extensions.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..96ed3d22d3c4 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -184,12 +184,89 @@ properties: multiplication as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zbkb + description: + The standard Zbkb bitmanip instructions for cryptography as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkc + description: + The standard Zbkc carry-less multiply instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkx + description: + The standard Zbkx crossbar permutation instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zbs description: | The standard Zbs bit-manipulation extension for single-bit instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zk + description: + The standard Zk Standard Scalar cryptography extension as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zkn + description: + The standard Zkn NIST algorithm suite extensions as ratified in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zknd + description: | + The standard Zknd for NIST suite: AES decryption instructions as + ratified in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zkne + description: | + The standard Zkne for NIST suite: AES encryption instructions as + ratified in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zknh + description: | + The standard Zknh for NIST suite: hash function instructions as + ratified in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zkr + description: + The standard Zkr entropy source extension as ratified in version + 1.0 of RISC-V Cryptography Extensions Volume I specification. + + - const: zks + description: + The standard Zks ShangMi algorithm suite extensions as ratified in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zksed + description: | + The standard Zksed for ShangMi suite: SM4 block cipher instructions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zksh + description: | + The standard Zksh for ShangMi suite: SM3 hash function instructions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zkt + description: + The standard Zkt for data independent execution latency as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zicbom description: The standard Zicbom extension for base cache management operations as From patchwork Tue Oct 17 13:14:44 2023 Content-Type: text/plain; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:32 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 07/19] dt-bindings: riscv: add vector crypto ISA extensions description Date: Tue, 17 Oct 2023 15:14:44 +0200 Message-ID: <20231017131456.2053396-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add Zv* vector crypto extensions that were added in "RISC-V Cryptography Extensions Volume II" specificationi[1]: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1] Signed-off-by: Clément Léger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 96ed3d22d3c4..93beb9872900 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -323,5 +323,101 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. + - const: zvbb + description: + The standard Zvbb extension for vectored basic bit-manipulation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvbc + description: + The standard Zvbc extension for vectored carryless multiplication + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkb + description: + The standard Zvkb extension for vector cryptography bit-manipulation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkg + description: + The standard Zvkg extension for vector GCM/GMAC instructions, as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") + of riscv-crypto. + + - const: zvkn + description: + The standard Zvkn extension for NIST algorithm suite instructions, as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") + of riscv-crypto. + + - const: zvknc + description: + The standard Zvknc extension for NIST algorithm suite with carryless + multiply instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkned + description: + The standard Zvkned extension for Vector AES block cipher + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkng + description: + The standard Zvkng extension for NIST algorithm suite with GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvknha + description: | + The standard Zvknha extension for NIST suite: vector SHA-2 secure, + hash (SHA-256 only) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvknhb + description: | + The standard Zvknhb extension for NIST suite: vector SHA-2 secure, + hash (SHA-256 and SHA-512) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvks + description: + The standard Zvks extension for ShangMi algorithm suite + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksc + description: + The standard Zvksc extension for ShangMi algorithm suite with + carryless multiplication instructions, as ratified in commit 56ed795 + ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksed + description: | + The standard Zvksed extension for ShangMi suite: SM4 block cipher + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksh + description: | + The standard Zvksh extension for ShangMi suite: SM3 secure hash + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksg + description: + The standard Zvksg extension for ShangMi algorithm suite with GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkt + description: + The standard Zvkt extension for vector data-independent execution + latency, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + additionalProperties: true ... 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:35 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 10/19] dt-bindings: riscv: add Zfh[min] ISA extensions description Date: Tue, 17 Oct 2023 15:14:47 +0200 Message-ID: <20231017131456.2053396-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add description of Zfh[min] ISA extensions[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1] Signed-off-by: Clément Léger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 93beb9872900..b0a0d1bdf369 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -208,6 +208,19 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zfh + description: + The standard Zfh extension for 16-bit half-precision binary + floating-point instructions, as ratified in commit 64074bc ("Update + version numbers for Zfh/Zfinx") of riscv-isa-manual. + + - const: zfhmin + description: + The standard Zfhmin extension which provides minimal support for + 16-bit half-precision binary floating-point instructions, as ratified + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + - const: zk description: The standard Zk Standard Scalar cryptography extension as ratified From patchwork Tue Oct 17 13:14:50 2023 Content-Type: text/plain; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:39 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 13/19] dt-bindings: riscv: add Zihintntl ISA extension description Date: Tue, 17 Oct 2023 15:14:50 +0200 Message-ID: <20231017131456.2053396-14-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add description for Zihintntl ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1] Signed-off-by: Clément Léger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index b0a0d1bdf369..eb4c77b319fb 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -324,6 +324,12 @@ properties: The standard Zihintpause extension for pause hints, as ratified in commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. + - const: zihintntl + description: + The standard Zihintntl extension for non-temporal locality hints, as + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the + riscv-isa-manual. + - const: zihpm description: The standard Zihpm extension for hardware performance counters, as From patchwork Tue Oct 17 13:14:53 2023 Content-Type: text/plain; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:41 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 16/19] dt-bindings: riscv: add Zvfh[min] ISA extension description Date: Tue, 17 Oct 2023 15:14:53 +0200 Message-ID: <20231017131456.2053396-17-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add description for Zvfh[min] ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1] Signed-off-by: Clément Léger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index eb4c77b319fb..07678564f11d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -354,6 +354,18 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zvfh + description: + The standard Zvfh extension for vectored half-precision + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + + - const: zvfhmin + description: + The standard Zvfhmin extension for vectored minimal half-precision + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + - const: zvkb description: The standard Zvkb extension for vector cryptography bit-manipulation From patchwork Tue Oct 17 13:14:56 2023 Content-Type: text/plain; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:45 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 19/19] dt-bindings: riscv: add Zfa ISA extension description Date: Tue, 17 Oct 2023 15:14:56 +0200 Message-ID: <20231017131456.2053396-20-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add description for the Zfa ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1] Signed-off-by: Clément Léger --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 07678564f11d..3033afcea033 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -208,6 +208,12 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zfa + description: + The standard Zfa extension for additional floating point + instructions, as ratified in commit 056b6ff ("Zfa is ratified") of + riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary