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Fri, 13 Oct 2023 05:56:40 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id da6-20020a056402176600b0053dfd3519f4sm2439193edb.22.2023.10.13.05.56.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 05:56:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , qemu-ppc@nongnu.org, Nicholas Piggin , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Subject: [PATCH 1/7] hw/ppc/spapr: Restrict PPCTimebase structure declaration to sPAPR Date: Fri, 13 Oct 2023 14:56:24 +0200 Message-ID: <20231013125630.95116-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013125630.95116-1-philmd@linaro.org> References: <20231013125630.95116-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The PPCTimebase structure is only used by the sPAPR machine. Move its declaration to "hw/ppc/spapr.h". Move vmstate_ppc_timebase and the VMSTATE_PPC_TIMEBASE_V() macro to hw/ppc/spapr.c, along with the timebase_foo() migration helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- include/hw/ppc/spapr.h | 6 +++ target/ppc/cpu-qom.h | 22 -------- hw/ppc/ppc.c | 107 ------------------------------------- hw/ppc/spapr.c | 116 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 122 insertions(+), 129 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index e91791a1a9..3cf9978cba 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -163,6 +163,12 @@ struct SpaprMachineClass { SpaprIrq *irq; }; +typedef struct PPCTimebase { + uint64_t guest_timebase; + int64_t time_of_the_day_ns; + bool runstate_paused; +} PPCTimebase; + #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ #define TYPE_SPAPR_WDT "spapr-wdt" diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index be33786bd8..b5deef5ca5 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -197,26 +197,4 @@ struct PowerPCCPUClass { int (*check_pow)(CPUPPCState *env); }; -#ifndef CONFIG_USER_ONLY -typedef struct PPCTimebase { - uint64_t guest_timebase; - int64_t time_of_the_day_ns; - bool runstate_paused; -} PPCTimebase; - -extern const VMStateDescription vmstate_ppc_timebase; - -#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ - .name = (stringify(_field)), \ - .version_id = (_version), \ - .size = sizeof(PPCTimebase), \ - .vmsd = &vmstate_ppc_timebase, \ - .flags = VMS_STRUCT, \ - .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ -} - -void cpu_ppc_clock_vm_state_change(void *opaque, bool running, - RunState state); -#endif - #endif diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index be167710a3..340cd6192f 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -32,7 +32,6 @@ #include "qemu/main-loop.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" -#include "sysemu/replay.h" #include "sysemu/runstate.h" #include "kvm_ppc.h" #include "migration/vmstate.h" @@ -967,112 +966,6 @@ void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) _cpu_ppc_store_purr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), value); } -static void timebase_save(PPCTimebase *tb) -{ - uint64_t ticks = cpu_get_host_ticks(); - PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); - - if (!first_ppc_cpu->env.tb_env) { - error_report("No timebase object"); - return; - } - - if (replay_mode == REPLAY_MODE_NONE) { - /* not used anymore, we keep it for compatibility */ - tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); - } else { - /* simpler for record-replay to avoid this event, compat not needed */ - tb->time_of_the_day_ns = 0; - } - - /* - * tb_offset is only expected to be changed by QEMU so - * there is no need to update it from KVM here - */ - tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; - - tb->runstate_paused = - runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM); -} - -static void timebase_load(PPCTimebase *tb) -{ - CPUState *cpu; - PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); - int64_t tb_off_adj, tb_off; - unsigned long freq; - - if (!first_ppc_cpu->env.tb_env) { - error_report("No timebase object"); - return; - } - - freq = first_ppc_cpu->env.tb_env->tb_freq; - - tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); - - tb_off = first_ppc_cpu->env.tb_env->tb_offset; - trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, - (tb_off_adj - tb_off) / freq); - - /* Set new offset to all CPUs */ - CPU_FOREACH(cpu) { - PowerPCCPU *pcpu = POWERPC_CPU(cpu); - pcpu->env.tb_env->tb_offset = tb_off_adj; - kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); - } -} - -void cpu_ppc_clock_vm_state_change(void *opaque, bool running, - RunState state) -{ - PPCTimebase *tb = opaque; - - if (running) { - timebase_load(tb); - } else { - timebase_save(tb); - } -} - -/* - * When migrating a running guest, read the clock just - * before migration, so that the guest clock counts - * during the events between: - * - * * vm_stop() - * * - * * pre_save() - * - * This reduces clock difference on migration from 5s - * to 0.1s (when max_downtime == 5s), because sending the - * final pages of memory (which happens between vm_stop() - * and pre_save()) takes max_downtime. - */ -static int timebase_pre_save(void *opaque) -{ - PPCTimebase *tb = opaque; - - /* guest_timebase won't be overridden in case of paused guest or savevm */ - if (!tb->runstate_paused) { - timebase_save(tb); - } - - return 0; -} - -const VMStateDescription vmstate_ppc_timebase = { - .name = "timebase", - .version_id = 1, - .minimum_version_id = 1, - .pre_save = timebase_pre_save, - .fields = (VMStateField []) { - VMSTATE_UINT64(guest_timebase, PPCTimebase), - VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), - VMSTATE_END_OF_LIST() - }, -}; - /* Set up (once) timebase frequency (in Hz) */ void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq) { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index cb840676d3..fe8b425ffd 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -37,6 +37,7 @@ #include "sysemu/numa.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" +#include "sysemu/replay.h" #include "sysemu/runstate.h" #include "qemu/log.h" #include "hw/fw-path-provider.h" @@ -1809,6 +1810,100 @@ static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) } } +static void timebase_save(PPCTimebase *tb) +{ + uint64_t ticks = cpu_get_host_ticks(); + PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); + + if (!first_ppc_cpu->env.tb_env) { + error_report("No timebase object"); + return; + } + + if (replay_mode == REPLAY_MODE_NONE) { + /* not used anymore, we keep it for compatibility */ + tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); + } else { + /* simpler for record-replay to avoid this event, compat not needed */ + tb->time_of_the_day_ns = 0; + } + + /* + * tb_offset is only expected to be changed by QEMU so + * there is no need to update it from KVM here + */ + tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; + + tb->runstate_paused = + runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM); +} + +static void timebase_load(PPCTimebase *tb) +{ + CPUState *cpu; + PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); + int64_t tb_off_adj, tb_off; + unsigned long freq; + + if (!first_ppc_cpu->env.tb_env) { + error_report("No timebase object"); + return; + } + + freq = first_ppc_cpu->env.tb_env->tb_freq; + + tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); + + tb_off = first_ppc_cpu->env.tb_env->tb_offset; + trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, + (tb_off_adj - tb_off) / freq); + + /* Set new offset to all CPUs */ + CPU_FOREACH(cpu) { + PowerPCCPU *pcpu = POWERPC_CPU(cpu); + pcpu->env.tb_env->tb_offset = tb_off_adj; + kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); + } +} + +static void cpu_ppc_clock_vm_state_change(void *opaque, bool running, + RunState state) +{ + PPCTimebase *tb = opaque; + + if (running) { + timebase_load(tb); + } else { + timebase_save(tb); + } +} + +/* + * When migrating a running guest, read the clock just + * before migration, so that the guest clock counts + * during the events between: + * + * * vm_stop() + * * + * * pre_save() + * + * This reduces clock difference on migration from 5s + * to 0.1s (when max_downtime == 5s), because sending the + * final pages of memory (which happens between vm_stop() + * and pre_save()) takes max_downtime. + */ +static int timebase_pre_save(void *opaque) +{ + PPCTimebase *tb = opaque; + + /* guest_timebase won't be overridden in case of paused guest or savevm */ + if (!tb->runstate_paused) { + timebase_save(tb); + } + + return 0; +} + static int spapr_pre_load(void *opaque) { int rc; @@ -2081,6 +2176,27 @@ static const VMStateDescription vmstate_spapr_fwnmi = { }, }; +static const VMStateDescription vmstate_spapr_timebase = { + .name = "timebase", + .version_id = 1, + .minimum_version_id = 1, + .pre_save = timebase_pre_save, + .fields = (VMStateField []) { + VMSTATE_UINT64(guest_timebase, PPCTimebase), + VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), + VMSTATE_END_OF_LIST() + }, +}; + +#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ + .name = (stringify(_field)), \ + .version_id = (_version), \ + .size = sizeof(PPCTimebase), \ + .vmsd = &vmstate_spapr_timebase, \ + .flags = VMS_STRUCT, \ + .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ +} + static const VMStateDescription vmstate_spapr = { .name = "spapr", .version_id = 3, From patchwork Fri Oct 13 12:56:25 2023 Content-Type: text/plain; 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Fri, 13 Oct 2023 05:56:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , qemu-ppc@nongnu.org, Nicholas Piggin , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Subject: [PATCH 2/7] target/ppc: Define powerpc_pm_insn_t in 'internal.h' Date: Fri, 13 Oct 2023 14:56:25 +0200 Message-ID: <20231013125630.95116-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013125630.95116-1-philmd@linaro.org> References: <20231013125630.95116-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org PM instructions are only used by TCG helpers. No need to expose to other hardware. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 10 ---------- target/ppc/internal.h | 9 +++++++++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index b5deef5ca5..b86fd46d25 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -115,16 +115,6 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER10, }; -/*****************************************************************************/ -/* PM instructions */ -typedef enum { - PPC_PM_DOZE, - PPC_PM_NAP, - PPC_PM_SLEEP, - PPC_PM_RVWINKLE, - PPC_PM_STOP, -} powerpc_pm_insn_t; - /*****************************************************************************/ /* Input pins model */ typedef enum powerpc_input_t powerpc_input_t; diff --git a/target/ppc/internal.h b/target/ppc/internal.h index c881c67a8b..5b20ecbd33 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -20,6 +20,15 @@ #include "hw/registerfields.h" +/* PM instructions */ +typedef enum { + PPC_PM_DOZE, + PPC_PM_NAP, + PPC_PM_SLEEP, + PPC_PM_RVWINKLE, + PPC_PM_STOP, +} powerpc_pm_insn_t; + #define FUNC_MASK(name, ret_type, size, max_val) \ static inline ret_type name(uint##size##_t start, \ uint##size##_t end) \ From patchwork Fri Oct 13 12:56:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1848268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=qpHZEqDD; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S6RPk3cbmz1yqn for ; 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Fri, 13 Oct 2023 05:56:52 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id g22-20020a50d0d6000000b0053e3d8f1d9fsm922774edf.67.2023.10.13.05.56.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 05:56:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , qemu-ppc@nongnu.org, Nicholas Piggin , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Subject: [PATCH 3/7] target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h' Date: Fri, 13 Oct 2023 14:56:26 +0200 Message-ID: <20231013125630.95116-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013125630.95116-1-philmd@linaro.org> References: <20231013125630.95116-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org ppc_cpu_class_by_name() is only called in target/ppc/, no need to expose outside (in particular to hw/). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 2 -- target/ppc/cpu.h | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index b86fd46d25..3dc92a852e 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -37,8 +37,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -ObjectClass *ppc_cpu_class_by_name(const char *name); - typedef struct CPUArchState CPUPPCState; typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_dcr_t ppc_dcr_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 30392ebeee..8bb66fbea4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1342,6 +1342,7 @@ struct ArchCPU { }; +ObjectClass *ppc_cpu_class_by_name(const char *name); PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); 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Fri, 13 Oct 2023 05:56:59 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id h14-20020aa7de0e000000b00532eba07773sm11554780edv.25.2023.10.13.05.56.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 05:56:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , qemu-ppc@nongnu.org, Nicholas Piggin , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Richard Henderson Subject: [PATCH 4/7] target/ppc: Move PowerPCCPUClass definition to 'cpu.h' Date: Fri, 13 Oct 2023 14:56:27 +0200 Message-ID: <20231013125630.95116-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013125630.95116-1-philmd@linaro.org> References: <20231013125630.95116-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The OBJECT_DECLARE_CPU_TYPE() macro forward-declares the PowerPCCPUClass type. This forward declaration is sufficient for code in hw/ to use the QOM definitions. No need to expose the structure definition. Keep it local to target/ppc/ by moving it to target/ppc/cpu.h. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/ppc/ppc.h | 2 +- target/ppc/cpu-qom.h | 56 -------------------------------------------- target/ppc/cpu.h | 51 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 57 deletions(-) diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 17a8dfc107..d5d119ea7f 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -1,7 +1,7 @@ #ifndef HW_PPC_H #define HW_PPC_H -#include "target/ppc/cpu-qom.h" +#include "target/ppc/cpu.h" void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level); PowerPCCPU *ppc_get_vcpu_by_pir(int pir); diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 3dc92a852e..41e97a0ea1 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_PPC_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #ifdef TARGET_PPC64 #define TYPE_POWERPC_CPU "powerpc64-cpu" @@ -37,10 +36,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -typedef struct CPUArchState CPUPPCState; -typedef struct ppc_tb_t ppc_tb_t; -typedef struct ppc_dcr_t ppc_dcr_t; - /*****************************************************************************/ /* MMU model */ typedef enum powerpc_mmu_t powerpc_mmu_t; @@ -134,55 +129,4 @@ enum powerpc_input_t { PPC_FLAGS_INPUT_RCPU, }; -typedef struct PPCHash64Options PPCHash64Options; - -/** - * PowerPCCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A PowerPC CPU model. - */ -struct PowerPCCPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - - DeviceRealize parent_realize; - DeviceUnrealize parent_unrealize; - ResettablePhases parent_phases; - void (*parent_parse_features)(const char *type, char *str, Error **errp); - - uint32_t pvr; - /* - * If @best is false, match if pcc is in the family of pvr - * Else match only if pcc is the best match for pvr in this family. - */ - bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best); - uint64_t pcr_mask; /* Available bits in PCR register */ - uint64_t pcr_supported; /* Bits for supported PowerISA versions */ - uint32_t svr; - uint64_t insns_flags; - uint64_t insns_flags2; - uint64_t msr_mask; - uint64_t lpcr_mask; /* Available bits in the LPCR */ - uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ - powerpc_mmu_t mmu_model; - powerpc_excp_t excp_model; - powerpc_input_t bus_model; - uint32_t flags; - int bfd_mach; - uint32_t l1_dcache_size, l1_icache_size; -#ifndef CONFIG_USER_ONLY - unsigned int gdb_num_sprs; - const char *gdb_spr_xml; -#endif - const PPCHash64Options *hash64_opts; - struct ppc_radix_page_info *radix_page_info; - uint32_t lrg_decr_bits; - int n_host_threads; - void (*init_proc)(CPUPPCState *env); - int (*check_pow)(CPUPPCState *env); -}; - #endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8bb66fbea4..d521ee97bb 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -198,9 +198,14 @@ typedef struct opc_handler_t opc_handler_t; /*****************************************************************************/ /* Types used to describe some PowerPC registers etc. */ typedef struct DisasContext DisasContext; +typedef struct ppc_dcr_t ppc_dcr_t; typedef struct ppc_spr_t ppc_spr_t; +typedef struct ppc_tb_t ppc_tb_t; typedef union ppc_tlb_t ppc_tlb_t; typedef struct ppc_hash_pte64 ppc_hash_pte64_t; +typedef struct PPCHash64Options PPCHash64Options; + +typedef struct CPUArchState CPUPPCState; /* SPR access micro-ops generations callbacks */ struct ppc_spr_t { @@ -1341,6 +1346,52 @@ struct ArchCPU { int32_t mig_slb_nr; }; +/** + * PowerPCCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A PowerPC CPU model. + */ +struct PowerPCCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; + ResettablePhases parent_phases; + void (*parent_parse_features)(const char *type, char *str, Error **errp); + + uint32_t pvr; + /* + * If @best is false, match if pcc is in the family of pvr + * Else match only if pcc is the best match for pvr in this family. + */ + bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best); + uint64_t pcr_mask; /* Available bits in PCR register */ + uint64_t pcr_supported; /* Bits for supported PowerISA versions */ + uint32_t svr; + uint64_t insns_flags; + uint64_t insns_flags2; + uint64_t msr_mask; + uint64_t lpcr_mask; /* Available bits in the LPCR */ + uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ + powerpc_mmu_t mmu_model; + powerpc_excp_t excp_model; + powerpc_input_t bus_model; + uint32_t flags; + int bfd_mach; + uint32_t l1_dcache_size, l1_icache_size; +#ifndef CONFIG_USER_ONLY + unsigned int gdb_num_sprs; + const char *gdb_spr_xml; +#endif + const PPCHash64Options *hash64_opts; + struct ppc_radix_page_info *radix_page_info; + uint32_t lrg_decr_bits; + int n_host_threads; + void (*init_proc)(CPUPPCState *env); + int (*check_pow)(CPUPPCState *env); +}; ObjectClass *ppc_cpu_class_by_name(const char *name); PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); From patchwork Fri Oct 13 12:56:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1848264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=AVEkOjIy; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S6RPK05GMz23jd for ; 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Fri, 13 Oct 2023 05:57:05 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id j18-20020a508a92000000b0053deb97e8e6sm3069380edj.28.2023.10.13.05.57.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 05:57:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , qemu-ppc@nongnu.org, Nicholas Piggin , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Subject: [PATCH 5/7] target/ppc: Move powerpc_excp_t definition to 'cpu.h' Date: Fri, 13 Oct 2023 14:56:28 +0200 Message-ID: <20231013125630.95116-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013125630.95116-1-philmd@linaro.org> References: <20231013125630.95116-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The powerpc_excp_t definition is only used by target/ppc/, no need to expose it. Restrict it by moving it to "target/ppc/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 29 ----------------------------- target/ppc/cpu.h | 27 +++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 29 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 41e97a0ea1..b2e42c2996 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -79,35 +79,6 @@ static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) return mmu_model & POWERPC_MMU_64; } -/*****************************************************************************/ -/* Exception model */ -typedef enum powerpc_excp_t powerpc_excp_t; -enum powerpc_excp_t { - POWERPC_EXCP_UNKNOWN = 0, - /* Standard PowerPC exception model */ - POWERPC_EXCP_STD, - /* PowerPC 40x exception model */ - POWERPC_EXCP_40x, - /* PowerPC 603/604/G2 exception model */ - POWERPC_EXCP_6xx, - /* PowerPC 7xx exception model */ - POWERPC_EXCP_7xx, - /* PowerPC 74xx exception model */ - POWERPC_EXCP_74xx, - /* BookE exception model */ - POWERPC_EXCP_BOOKE, - /* PowerPC 970 exception model */ - POWERPC_EXCP_970, - /* POWER7 exception model */ - POWERPC_EXCP_POWER7, - /* POWER8 exception model */ - POWERPC_EXCP_POWER8, - /* POWER9 exception model */ - POWERPC_EXCP_POWER9, - /* POWER10 exception model */ - POWERPC_EXCP_POWER10, -}; - /*****************************************************************************/ /* Input pins model */ typedef enum powerpc_input_t powerpc_input_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d521ee97bb..d8cf4c03bf 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -190,6 +190,33 @@ enum { POWERPC_EXCP_TRAP = 0x40, }; +/* Exception model */ +typedef enum powerpc_excp_t { + POWERPC_EXCP_UNKNOWN = 0, + /* Standard PowerPC exception model */ + POWERPC_EXCP_STD, + /* PowerPC 40x exception model */ + POWERPC_EXCP_40x, + /* PowerPC 603/604/G2 exception model */ + POWERPC_EXCP_6xx, + /* PowerPC 7xx exception model */ + POWERPC_EXCP_7xx, + /* PowerPC 74xx exception model */ + POWERPC_EXCP_74xx, + /* BookE exception model */ + POWERPC_EXCP_BOOKE, + /* PowerPC 970 exception model */ + POWERPC_EXCP_970, + /* POWER7 exception model */ + POWERPC_EXCP_POWER7, + /* POWER8 exception model */ + POWERPC_EXCP_POWER8, + /* POWER9 exception model */ + POWERPC_EXCP_POWER9, + /* POWER10 exception model */ + POWERPC_EXCP_POWER10, +} powerpc_excp_t; + #define PPC_INPUT(env) ((env)->bus_model) /*****************************************************************************/ From patchwork Fri Oct 13 12:56:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1848267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=SJiBlll7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S6RPX4m3Xz1yqn for ; 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Fri, 13 Oct 2023 05:57:11 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id f5-20020a170906560500b009b8dbdd5203sm12337668ejq.107.2023.10.13.05.57.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 05:57:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , qemu-ppc@nongnu.org, Nicholas Piggin , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Subject: [PATCH 6/7] target/ppc: Move powerpc_mmu_t definition to 'cpu.h' Date: Fri, 13 Oct 2023 14:56:29 +0200 Message-ID: <20231013125630.95116-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013125630.95116-1-philmd@linaro.org> References: <20231013125630.95116-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The powerpc_mmu_t definition is only used by target/ppc/, no need to expose it. Restrict it by moving it to "target/ppc/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 43 ------------------------------------------- target/ppc/cpu.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 43 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index b2e42c2996..5bdca472be 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -36,49 +36,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -/*****************************************************************************/ -/* MMU model */ -typedef enum powerpc_mmu_t powerpc_mmu_t; -enum powerpc_mmu_t { - POWERPC_MMU_UNKNOWN = 0x00000000, - /* Standard 32 bits PowerPC MMU */ - POWERPC_MMU_32B = 0x00000001, - /* PowerPC 6xx MMU with software TLB */ - POWERPC_MMU_SOFT_6xx = 0x00000002, - /* - * PowerPC 74xx MMU with software TLB (this has been - * disabled, see git history for more information. - * keywords: tlbld tlbli TLBMISS PTEHI PTELO) - */ - POWERPC_MMU_SOFT_74xx = 0x00000003, - /* PowerPC 4xx MMU with software TLB */ - POWERPC_MMU_SOFT_4xx = 0x00000004, - /* PowerPC MMU in real mode only */ - POWERPC_MMU_REAL = 0x00000006, - /* Freescale MPC8xx MMU model */ - POWERPC_MMU_MPC8xx = 0x00000007, - /* BookE MMU model */ - POWERPC_MMU_BOOKE = 0x00000008, - /* BookE 2.06 MMU model */ - POWERPC_MMU_BOOKE206 = 0x00000009, -#define POWERPC_MMU_64 0x00010000 - /* 64 bits PowerPC MMU */ - POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, - /* Architecture 2.03 and later (has LPCR) */ - POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, - /* Architecture 2.06 variant */ - POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, - /* Architecture 2.07 variant */ - POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, - /* Architecture 3.00 variant */ - POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, -}; - -static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) -{ - return mmu_model & POWERPC_MMU_64; -} - /*****************************************************************************/ /* Input pins model */ typedef enum powerpc_input_t powerpc_input_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d8cf4c03bf..c2cd069095 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -217,6 +217,48 @@ typedef enum powerpc_excp_t { POWERPC_EXCP_POWER10, } powerpc_excp_t; +/*****************************************************************************/ +/* MMU model */ +typedef enum powerpc_mmu_t { + POWERPC_MMU_UNKNOWN = 0x00000000, + /* Standard 32 bits PowerPC MMU */ + POWERPC_MMU_32B = 0x00000001, + /* PowerPC 6xx MMU with software TLB */ + POWERPC_MMU_SOFT_6xx = 0x00000002, + /* + * PowerPC 74xx MMU with software TLB (this has been + * disabled, see git history for more information. + * keywords: tlbld tlbli TLBMISS PTEHI PTELO) + */ + POWERPC_MMU_SOFT_74xx = 0x00000003, + /* PowerPC 4xx MMU with software TLB */ + POWERPC_MMU_SOFT_4xx = 0x00000004, + /* PowerPC MMU in real mode only */ + POWERPC_MMU_REAL = 0x00000006, + /* Freescale MPC8xx MMU model */ + POWERPC_MMU_MPC8xx = 0x00000007, + /* BookE MMU model */ + POWERPC_MMU_BOOKE = 0x00000008, + /* BookE 2.06 MMU model */ + POWERPC_MMU_BOOKE206 = 0x00000009, +#define POWERPC_MMU_64 0x00010000 + /* 64 bits PowerPC MMU */ + POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, + /* Architecture 2.03 and later (has LPCR) */ + POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, + /* Architecture 2.06 variant */ + POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, + /* Architecture 2.07 variant */ + POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, + /* Architecture 3.00 variant */ + POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, +} powerpc_mmu_t; + +static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) +{ + return mmu_model & POWERPC_MMU_64; +} + #define PPC_INPUT(env) ((env)->bus_model) /*****************************************************************************/ From patchwork Fri Oct 13 12:56:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1848270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=lhcKCGoo; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S6RPw0MXDz1yqn for ; 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Fri, 13 Oct 2023 05:57:17 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id h13-20020a17090619cd00b009ae587ce135sm12309552ejd.223.2023.10.13.05.57.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 05:57:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , qemu-ppc@nongnu.org, Nicholas Piggin , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Subject: [PATCH 7/7] target/ppc: Move powerpc_input_t definition to 'cpu.h' Date: Fri, 13 Oct 2023 14:56:30 +0200 Message-ID: <20231013125630.95116-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013125630.95116-1-philmd@linaro.org> References: <20231013125630.95116-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The powerpc_input_t definition is only used by target/ppc/, no need to expose it. Restrict it by moving it to "target/ppc/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 21 --------------------- target/ppc/cpu.h | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 5bdca472be..6d39ad451c 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -36,25 +36,4 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -/*****************************************************************************/ -/* Input pins model */ -typedef enum powerpc_input_t powerpc_input_t; -enum powerpc_input_t { - PPC_FLAGS_INPUT_UNKNOWN = 0, - /* PowerPC 6xx bus */ - PPC_FLAGS_INPUT_6xx, - /* BookE bus */ - PPC_FLAGS_INPUT_BookE, - /* PowerPC 405 bus */ - PPC_FLAGS_INPUT_405, - /* PowerPC 970 bus */ - PPC_FLAGS_INPUT_970, - /* PowerPC POWER7 bus */ - PPC_FLAGS_INPUT_POWER7, - /* PowerPC POWER9 bus */ - PPC_FLAGS_INPUT_POWER9, - /* Freescale RCPU bus */ - PPC_FLAGS_INPUT_RCPU, -}; - #endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c2cd069095..4b8b5d3d3e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -259,6 +259,26 @@ static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) return mmu_model & POWERPC_MMU_64; } +/*****************************************************************************/ +/* Input pins model */ +typedef enum powerpc_input_t { + PPC_FLAGS_INPUT_UNKNOWN = 0, + /* PowerPC 6xx bus */ + PPC_FLAGS_INPUT_6xx, + /* BookE bus */ + PPC_FLAGS_INPUT_BookE, + /* PowerPC 405 bus */ + PPC_FLAGS_INPUT_405, + /* PowerPC 970 bus */ + PPC_FLAGS_INPUT_970, + /* PowerPC POWER7 bus */ + PPC_FLAGS_INPUT_POWER7, + /* PowerPC POWER9 bus */ + PPC_FLAGS_INPUT_POWER9, + /* Freescale RCPU bus */ + PPC_FLAGS_INPUT_RCPU, +} powerpc_input_t; + #define PPC_INPUT(env) ((env)->bus_model) /*****************************************************************************/