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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:47 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 01/20] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible Date: Tue, 10 Oct 2023 23:49:09 +0100 Message-ID: <20231010224928.2296997-2-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add gs101-pmu compatible to the bindings documentation. Signed-off-by: Peter Griffin --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index e1d716df5dfa..9e497c310532 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -15,6 +15,7 @@ select: compatible: contains: enum: + - google,gs101-pmu - samsung,exynos3250-pmu - samsung,exynos4210-pmu - samsung,exynos4212-pmu @@ -35,6 +36,7 @@ properties: oneOf: - items: - enum: + - google,gs101-pmu - samsung,exynos3250-pmu - samsung,exynos4210-pmu - samsung,exynos4212-pmu From patchwork Tue Oct 10 22:49:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1846155 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:48 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings Date: Tue, 10 Oct 2023 23:49:10 +0100 Message-ID: <20231010224928.2296997-3-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Provide dt-schema documentation for Google gs101 SoC clock controller. Currently this adds support for cmu_top, cmu_misc and cmu_apm. Signed-off-by: Peter Griffin --- .../bindings/clock/google,gs101-clock.yaml | 125 ++++++++++ include/dt-bindings/clock/google,gs101.h | 232 ++++++++++++++++++ 2 files changed, 357 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 include/dt-bindings/clock/google,gs101.h diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml new file mode 100644 index 000000000000..f74494594b3b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 SoC clock controller + +maintainers: + - Peter Griffin + +description: | + Google GS101 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that clock tree + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate + clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/gs101.h' header. + +properties: + compatible: + enum: + - google,gs101-cmu-top + - google,gs101-cmu-apm + - google,gs101-cmu-misc + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-misc + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Misc bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_misc_bus + + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-apm + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + + clock-names: + items: + - const: oscclk + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_TOP + - | + #include + soc { + #address-cells = <2>; + #size-cells = <1>; + + cmu_top: clock-controller@1e080000 { + compatible = "google,gs101-cmu-top"; + reg = <0x0 0x1e080000 0x8000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + }; + +... diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h new file mode 100644 index 000000000000..7765ba68f734 --- /dev/null +++ b/include/dt-bindings/clock/google,gs101.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. + * Author: Peter Griffin + * + * Device Tree binding constants for Google gs101 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H + +/* CMU_TOP PLL*/ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SPARE_PLL 5 + +/* CMU_TOP MUX*/ +#define CLK_MOUT_SHARED0_PLL 6 +#define CLK_MOUT_SHARED1_PLL 7 +#define CLK_MOUT_SHARED2_PLL 8 +#define CLK_MOUT_SHARED3_PLL 9 +#define CLK_MOUT_SPARE_PLL 10 +#define CLK_MOUT_BUS0_BUS 11 +#define CLK_MOUT_CMU_BOOST 12 +#define CLK_MOUT_BUS1_BUS 13 +#define CLK_MOUT_BUS2_BUS 14 +#define CLK_MOUT_CORE_BUS 15 +#define CLK_MOUT_EH_BUS 16 +#define CLK_MOUT_CPUCL2_SWITCH 17 +#define CLK_MOUT_CPUCL1_SWITCH 18 +#define CLK_MOUT_CPUCL0_SWITCH 19 +#define CLK_MOUT_CPUCL0_DBG 20 +#define CLK_MOUT_CMU_HPM 21 +#define CLK_MOUT_G3D_SWITCH 22 +#define CLK_MOUT_G3D_GLB 23 +#define CLK_MOUT_DPU_BUS 24 +#define CLK_MOUT_DISP_BUS 25 +#define CLK_MOUT_G2D_G2D 26 +#define CLK_MOUT_G2D_MSCL 27 +#define CLK_MOUT_HSI0_USB31DRD 28 +#define CLK_MOUT_HSI0_BUS 29 +#define CLK_MOUT_HSI0_DPGTC 30 +#define CLK_MOUT_HSI0_USBDPDGB 31 +#define CLK_MOUT_HSI1_BUS 32 +#define CLK_MOUT_HSI1_PCIE 33 +#define CLK_MOUT_HSI2_BUS 34 +#define CLK_MOUT_HSI2_PCIE 35 +#define CLK_MOUT_HSI2_UFS_EMBD 36 +#define CLK_MOUT_HSI2_MMC_CARD 37 +#define CLK_MOUT_CSIS 38 +#define CLK_MOUT_PDP_BUS 39 +#define CLK_MOUT_PDP_VRA 40 +#define CLK_MOUT_IPP_BUS 41 +#define CLK_MOUT_G3AA 42 +#define CLK_MOUT_ITP 43 +#define CLK_MOUT_DNS_BUS 44 +#define CLK_MOUT_TNR_BUS 45 +#define CLK_MOUT_MCSC_ITSC 46 +#define CLK_MOUT_MCSC_MCSC 47 +#define CLK_MOUT_GDC_SCSC 48 +#define CLK_MOUT_GDC_GDC0 49 +#define CLK_MOUT_GDC_GDC1 50 +#define CLK_MOUT_MFC_MFC 51 +#define CLK_MOUT_MIF_SWITCH 52 +#define CLK_MOUT_MIF_BUS 53 +#define CLK_MOUT_MISC_BUS 54 +#define CLK_MOUT_MISC_SSS 55 +#define CLK_MOUT_PERIC0_IP 56 +#define CLK_MOUT_PERIC0_BUS 57 +#define CLK_MOUT_PERIC1_IP 58 +#define CLK_MOUT_PERIC1_BUS 59 +#define CLK_MOUT_TPU_TPU 60 +#define CLK_MOUT_TPU_TPUCTL 61 +#define CLK_MOUT_TPU_BUS 62 +#define CLK_MOUT_TPU_UART 63 +#define CLK_MOUT_TPU_HPM 64 +#define CLK_MOUT_BO_BUS 65 +#define CLK_MOUT_G3D_BUSD 66 + +/* CMU_TOP Dividers*/ +#define CLK_DOUT_SHARED0_DIV3 67 +#define CLK_DOUT_SHARED0_DIV2 68 +#define CLK_DOUT_SHARED0_DIV4 69 +#define CLK_DOUT_SHARED0_DIV5 70 +#define CLK_DOUT_SHARED1_DIV3 71 +#define CLK_DOUT_SHARED1_DIV2 72 +#define CLK_DOUT_SHARED1_DIV4 73 +#define CLK_DOUT_SHARED2_DIV2 74 +#define CLK_DOUT_SHARED3_DIV2 75 +#define CLK_DOUT_BUS0_BUS 76 +#define CLK_DOUT_CMU_BOOST 77 +#define CLK_DOUT_BUS1_BUS 78 +#define CLK_DOUT_BUS2_BUS 79 +#define CLK_DOUT_CORE_BUS 80 +#define CLK_DOUT_EH_BUS 81 +#define CLK_DOUT_CPUCL2_SWITCH 82 +#define CLK_DOUT_CPUCL1_SWITCH 83 +#define CLK_DOUT_CPUCL0_SWITCH 84 +#define CLK_DOUT_CPUCL0_DBG 85 +#define CLK_DOUT_CMU_HPM 86 +#define CLK_DOUT_G3D_SWITCH 87 +#define CLK_DOUT_G3D_GLB 88 +#define CLK_DOUT_DPU_BUS 89 +#define CLK_DOUT_DISP_BUS 90 +#define CLK_DOUT_G2D_G2D 91 +#define CLK_DOUT_G2D_MSCL 92 +#define CLK_DOUT_HSI0_USB31DRD 93 +#define CLK_DOUT_HSI0_BUS 94 +#define CLK_DOUT_HSI0_DPGTC 95 +#define CLK_DOUT_HSI0_USBDPDGB 96 +#define CLK_DOUT_HSI1_BUS 97 +#define CLK_DOUT_HSI1_PCIE 98 +#define CLK_DOUT_HSI2_BUS 100 +#define CLK_DOUT_HSI2_PCIE 101 +#define CLK_DOUT_HSI2_UFS_EMBD 102 +#define CLK_DOUT_HSI2_MMC_CARD 103 +#define CLK_DOUT_CSIS 104 +#define CLK_DOUT_PDP_BUS 105 +#define CLK_DOUT_PDP_VRA 106 +#define CLK_DOUT_IPP_BUS 107 +#define CLK_DOUT_G3AA 108 +#define CLK_DOUT_ITP 109 +#define CLK_DOUT_DNS_BUS 110 +#define CLK_DOUT_TNR_BUS 111 +#define CLK_DOUT_MCSC_ITSC 112 +#define CLK_DOUT_MCSC_MCSC 113 +#define CLK_DOUT_GDC_SCSC 114 +#define CLK_DOUT_GDC_GDC0 115 +#define CLK_DOUT_GDC_GDC1 116 +#define CLK_DOUT_MFC_MFC 117 +#define CLK_DOUT_MIF_BUS 118 +#define CLK_DOUT_MISC_BUS 119 +#define CLK_DOUT_MISC_SSS 120 +#define CLK_DOUT_PERIC0_BUS 121 +#define CLK_DOUT_PERIC0_IP 122 +#define CLK_DOUT_PERIC1_BUS 123 +#define CLK_DOUT_PERIC1_IP 124 +#define CLK_DOUT_TPU_TPU 125 +#define CLK_DOUT_TPU_TPUCTL 126 +#define CLK_DOUT_TPU_BUS 127 +#define CLK_DOUT_TPU_UART 128 +#define CLK_DOUT_TPU_HPM 129 +#define CLK_DOUT_BO_BUS 130 + +/* CMU_TOP Gates*/ +#define CLK_GOUT_BUS0_BUS 131 +#define CLK_GOUT_BUS1_BUS 132 +#define CLK_GOUT_BUS2_BUS 133 +#define CLK_GOUT_CORE_BUS 134 +#define CLK_GOUT_EH_BUS 135 +#define CLK_GOUT_CPUCL2_SWITCH 136 +#define CLK_GOUT_CPUCL1_SWITCH 137 +#define CLK_GOUT_CPUCL0_SWITCH 138 +#define CLK_GOUT_CPUCL0_DBG 139 +#define CLK_GOUT_CMU_HPM 140 +#define CLK_GOUT_G3D_SWITCH 141 +#define CLK_GOUT_G3D_GLB 142 +#define CLK_GOUT_DPU_BUS 143 +#define CLK_GOUT_DISP_BUS 144 +#define CLK_GOUT_G2D_G2D 145 +#define CLK_GOUT_G2D_MSCL 146 +#define CLK_GOUT_HSI0_USB31DRD 147 +#define CLK_GOUT_HSI0_BUS 148 +#define CLK_GOUT_HSI0_DPGTC 149 +#define CLK_GOUT_HSI0_USBDPDGB 150 +#define CLK_GOUT_HSI1_BUS 151 +#define CLK_GOUT_HSI1_PCIE 152 +#define CLK_GOUT_HSI2_BUS 153 +#define CLK_GOUT_HSI2_PCIE 154 +#define CLK_GOUT_HSI2_UFS_EMBD 155 +#define CLK_GOUT_HSI2_MMC_CARD 156 +#define CLK_GOUT_CSIS 157 +#define CLK_GOUT_PDP_BUS 158 +#define CLK_GOUT_PDP_VRA 159 +#define CLK_GOUT_IPP_BUS 160 +#define CLK_GOUT_G3AA 161 +#define CLK_GOUT_ITP 162 +#define CLK_GOUT_DNS_BUS 163 +#define CLK_GOUT_TNR_BUS 164 +#define CLK_GOUT_MCSC_ITSC 165 +#define CLK_GOUT_MCSC_MCSC 166 +#define CLK_GOUT_GDC_SCSC 167 +#define CLK_GOUT_GDC_GDC0 168 +#define CLK_GOUT_GDC_GDC1 169 +#define CLK_GOUT_MFC_MFC 170 +#define CLK_GOUT_MIF_SWITCH 171 +#define CLK_GOUT_MIF_BUS 172 +#define CLK_GOUT_MISC_BUS 173 +#define CLK_GOUT_MISC_SSS 174 +#define CLK_GOUT_PERIC0_BUS 175 +#define CLK_GOUT_PERIC0_IP 176 +#define CLK_GOUT_PERIC1_BUS 177 +#define CLK_GOUT_PERIC1_IP 178 +#define CLK_GOUT_TPU_TPU 179 +#define CLK_GOUT_TPU_TPUCTL 180 +#define CLK_GOUT_TPU_BUS 181 +#define CLK_GOUT_TPU_UART 182 +#define CLK_GOUT_TPU_HPM 183 +#define CLK_GOUT_BO_BUS 184 +#define CLK_GOUT_CMU_BOOST 185 + +/* CMU_APM */ + +#define CLK_MOUT_APM_FUNC 1 +#define CLK_MOUT_APM_FUNCSRC 2 +#define CLK_DOUT_APM_BOOST 3 +#define CLK_DOUT_APM_USI0_UART 4 +#define CLK_DOUT_APM_USI0_USI 5 +#define CLK_DOUT_APM_USI1_UART 6 +#define CLK_GOUT_APM_FUNC 7 +#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 8 +#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 9 +#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 10 +#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 11 +#define CLK_APM_PLL_DIV2_APM 12 +#define CLK_APM_PLL_DIV4_APM 13 +#define CLK_APM_PLL_DIV16_APM 14 + +/* CMU_MISC */ + +#define CLK_MOUT_MISC_BUS_USER 1 +#define CLK_MOUT_MISC_SSS_USER 2 +#define CLK_DOUT_MISC_BUSP 3 +#define CLK_DOUT_MISC_GIC 4 +#define CLK_GOUT_MISC_PCLK 5 +#define CLK_GOUT_MISC_SYSREG_PCLK 6 +#define CLK_GOUT_MISC_WDT_CLUSTER0 7 +#define CLK_GOUT_MISC_WDT_CLUSTER1 8 + +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From patchwork Tue Oct 10 22:49:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:50 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 03/20] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 Date: Tue, 10 Oct 2023 23:49:11 +0100 Message-ID: <20231010224928.2296997-4-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net GS101 has three different SYSREG controllers, add dedicated compatibles for them to the documentation. Signed-off-by: Peter Griffin --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 163e912e9cad..dbd12a97faad 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -30,6 +30,12 @@ properties: - samsung,exynos5433-fsys-sysreg - const: samsung,exynos5433-sysreg - const: syscon + - items: + - enum: + - google,gs101-peric0-sysreg + - google,gs101-peric1-sysreg + - google,gs101-apm-sysreg + - const: syscon - items: - enum: - samsung,exynos5433-sysreg From patchwork Tue Oct 10 22:49:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1846156 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:51 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 04/20] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings Date: Tue, 10 Oct 2023 23:49:12 +0100 Message-ID: <20231010224928.2296997-5-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the dt-schema documentation. gs101 SoC has two CPU clusters and each cluster has its own dedicated watchdog timer (similar to exynos850 and exynosautov9 SoCs). These WDT instances are controlled using different bits in PMU registers. Signed-off-by: Peter Griffin --- .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index 8fb6656ba0c2..67c8767f0499 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -17,6 +17,8 @@ description: |+ properties: compatible: enum: + - google,gs101-wdt # for Google gs101 + - google,gs201-wdt # for Google gs201 - samsung,s3c2410-wdt # for S3C2410 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4 - samsung,exynos5250-wdt # for Exynos5250 @@ -42,13 +44,13 @@ properties: samsung,cluster-index: $ref: /schemas/types.yaml#/definitions/uint32 description: - Index of CPU cluster on which watchdog is running (in case of Exynos850) + Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01) samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420, Exynos7 and Exynos850). + Exynos5420, Exynos7, Exynos850 and gsx01). required: - compatible @@ -69,6 +71,8 @@ allOf: - samsung,exynos7-wdt - samsung,exynos850-wdt - samsung,exynosautov9-wdt + - google,gs101-wdt + - google,gs201-wdt then: required: - samsung,syscon-phandle @@ -79,6 +83,8 @@ allOf: enum: - samsung,exynos850-wdt - samsung,exynosautov9-wdt + - google,gs101-wdt + - google,gs201-wdt then: properties: clocks: From patchwork Tue Oct 10 22:49:13 2023 Content-Type: text/plain; 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:52 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org, Rob Herring Subject: [PATCH v2 05/20] dt-bindings: arm: google: Add bindings for Google ARM platforms Date: Tue, 10 Oct 2023 23:49:13 +0100 Message-ID: <20231010224928.2296997-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net This introduces bindings and dt-schema for the Google tensor SoCs. Currently just gs101 and pixel 6 are supported. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/google.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml new file mode 100644 index 000000000000..167945e4d5ee --- /dev/null +++ b/Documentation/devicetree/bindings/arm/google.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/google.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor platforms + +maintainers: + - Peter Griffin + +description: | + ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel + devices. + + Currently upstream this is devices using "gs101" SoC which is found in Pixel + 6, Pixel 6 Pro and Pixel 6a. + + Google have a few different names for the SoC. + - Marketing name ("Tensor") + - Codename ("Whitechapel") + - SoC ID ("gs101") + - Die ID ("S5P9845"); + + Likewise there are a couple of names for the actual device + - Marketing name ("Pixel 6") + - Codename ("Oriole") + + Devicetrees should use the lowercased SoC ID and lowercased board codename. + e.g. gs101 and gs101-oriole + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Google Pixel 6 / Oriole + items: + - enum: + - google,gs101-oriole + - const: google,gs101 + +additionalProperties: true + +... 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:54 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 06/20] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible Date: Tue, 10 Oct 2023 23:49:14 +0100 Message-ID: <20231010224928.2296997-7-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add the "google,gs101-pinctrl" compatible to the dt-schema bindings documentation. Add maxItems of 50 for the interrupts property as gs101 can have multiple irqs. Signed-off-by: Peter Griffin --- .../bindings/pinctrl/samsung,pinctrl.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 26614621774a..2464bc43aacb 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -35,6 +35,7 @@ properties: compatible: enum: + - google,gs101-pinctrl - samsung,s3c2412-pinctrl - samsung,s3c2416-pinctrl - samsung,s3c2440-pinctrl @@ -134,6 +135,24 @@ allOf: minItems: 1 maxItems: 1 + - if: + properties: + compatible: + contains: + const: google,gs101-pinctrl + then: + properties: + interrupts: + description: + Required for external wakeup interrupts. List all external + wakeup interrupts supported by this bank. + minItems: 1 + maxItems: 50 + else: + properties: + interrupts: + maxItems: 1 + additionalProperties: false examples: From patchwork Tue Oct 10 22:49:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1846162 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=vEg2JvS2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-7422-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S4rhF04J8z26jV for ; Wed, 11 Oct 2023 09:50:04 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id CC8322821E9 for ; Tue, 10 Oct 2023 22:50:02 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 63EB731595; Tue, 10 Oct 2023 22:50:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vEg2JvS2" X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66031315A0 for ; Tue, 10 Oct 2023 22:50:00 +0000 (UTC) Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA891F1 for ; Tue, 10 Oct 2023 15:49:57 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40572aeb6d0so58764325e9.1 for ; Tue, 10 Oct 2023 15:49:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696978196; x=1697582996; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y4qKMp7WKTgYWQn4jdaHUw1RN+hYCPkZJUgFKC+LCBg=; b=vEg2JvS2P4cPdjf97YddAJjciyShFEruYZVqqx6QI+cM/9KqgXPUK/JX7Fsg27mijC +xikWtTXE/BTYifhtxw0Nraj+vpNdllf2dbFOsoXD4SG2nyMISUXry9uBV+UAgdpsd24 1DZmSKv+d23bmNXwK8W5Bfs7AoWeGJkgrTfeGK/PmCQZeelJNCqj9LWedwPJqQnzXmXp rjaWm9Gy9pI4Mlc/3gHs17CT2nx8ZKmM62gS6qYHwkX23Kg3AURhDUOwXZJuDhqlTGNa n5GoNFEe1+SNpGCdFdfdVuS8gJmJ/NWyy5Rh5xpFeCVS9PFWnTu6B3MvWJ+oxS0Ml++k lnBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696978196; x=1697582996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y4qKMp7WKTgYWQn4jdaHUw1RN+hYCPkZJUgFKC+LCBg=; b=dyE2X2IupWvHIY4IFgL/QtmFv6tTn/eCMuS7t2ZIPaaBxsbcXOAwC18HWS76q24a+E ZmqFhtaFmQ3VhM3T42hOwwDofHcWjlrjTbwVLWnv0u1rXDVjKmO10Z2r5KmUpVClQkrB 5ctOmmzvDgqhX7rkrO1s0ZlrQSGHNXYOslSL7IOR7DNmVfGRPNjuI96wYv6ShECFYnUA MugwVCtKwx19pSffNv7OcpTwYWRfGmbi18UV54t6HnkPlLvGJxcVrly+XF7PMDTDVu76 77x3Wo3YlLnsI/Zlf1hjBIi0IxxCWx8TPQnK4fxCo7434Bqa6o/9PcCjrDNU81Rrx63W i+gA== X-Gm-Message-State: AOJu0YyOKCADPrJvZ96eqpmIBKFCsxG4GU30XZNJn3RNnUZDfxYDXiM/ KGMUyYoQyKq63GMZ94HHuaHlYg== X-Google-Smtp-Source: AGHT+IEloZuZCLDePUs0QPFYOcybxWTkJkyfed9V3vJNhMuLIOUj4aXik2RMdRgdMNiAXc/amo3vnw== X-Received: by 2002:a1c:7212:0:b0:401:bdd7:499d with SMTP id n18-20020a1c7212000000b00401bdd7499dmr17694790wmc.25.1696978195874; Tue, 10 Oct 2023 15:49:55 -0700 (PDT) Received: from gpeter-l.lan (host-92-12-225-146.as13285.net. [92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:55 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 07/20] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible Date: Tue, 10 Oct 2023 23:49:15 +0100 Message-ID: <20231010224928.2296997-8-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9 where more than one pin controller can do external wake-up interrupt. So add a dedicated compatible for it. Signed-off-by: Peter Griffin --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 1de91a51234d..7cddce761c46 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -29,6 +29,7 @@ description: | properties: compatible: enum: + - google,gs101-wakeup-eint - samsung,s3c2410-wakeup-eint - samsung,s3c2412-wakeup-eint - samsung,s3c64xx-wakeup-eint @@ -99,6 +100,7 @@ allOf: enum: - samsung,exynos850-wakeup-eint - samsung,exynosautov9-wakeup-eint + - google,gs101-wakeup-eint then: properties: interrupts: false From patchwork Tue Oct 10 22:49:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1846166 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.49.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:49:56 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 08/20] dt-bindings: serial: samsung: Add google-gs101-uart compatible Date: Tue, 10 Oct 2023 23:49:16 +0100 Message-ID: <20231010224928.2296997-9-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add dedicated google-gs101-uart compatible to the dt-schema for representing uart of the Google Tensor gs101 SoC. Signed-off-by: Peter Griffin --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 8bd88d5cbb11..72471ebe5734 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -19,11 +19,13 @@ properties: compatible: oneOf: - items: + - const: google,gs101-uart - const: samsung,exynosautov9-uart - const: samsung,exynos850-uart - enum: - apple,s5l-uart - axis,artpec8-uart + - google,gs101-uart - samsung,s3c2410-uart - samsung,s3c2412-uart - samsung,s3c2440-uart From patchwork Tue Oct 10 22:49:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1846173 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=dDHsMq9l; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-7435-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S4rhn1zjhz1yq3 for ; Wed, 11 Oct 2023 09:50:33 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 5A0611C20F11 for ; Tue, 10 Oct 2023 22:50:31 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 09D0B315AD; Tue, 10 Oct 2023 22:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dDHsMq9l" X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34A0A3159B for ; Tue, 10 Oct 2023 22:50:26 +0000 (UTC) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02034109 for ; Tue, 10 Oct 2023 15:50:12 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-32167a4adaaso5644459f8f.1 for ; Tue, 10 Oct 2023 15:50:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696978211; x=1697583011; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pGisQqtgHWrMMIzlwH60bIvis7qiSBhtXK5ziOB9fGI=; b=dDHsMq9lqiR17t22tc0BtM4CBKEjRYncBHY12utRNsX0FIDq87eyOCHnCpSiKeOD9w /qSJcl1A+z9a79ywi9636vQtw821j2XTIIcYRgseiH2MMKNcczvAdOw9DywCtS8ZgaAd 2sbb854acwxX6J5knpr2kzkyO34jQe9o0BupK34uGJa/2EheB9zuIOzfVbOZjm6Y3pnl lP3K178CdCVAXgI27TjMVmYIEPrF88jWoBkl7LDWeES/tGNAOf44Dn0WC4n3RvUIDVo+ TMHLs0hoQs9oEdk46XOKAbTzIacBfZbAdhQSSledjFhyYymjukywh3ZjGZdf1OcDtp/A aiaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696978211; x=1697583011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pGisQqtgHWrMMIzlwH60bIvis7qiSBhtXK5ziOB9fGI=; b=txR0BHhI7oWwxXK8dR3C0OVgUYy7nepG7nfR0FNgiLXo034wnJK+b3W2uavMAKxWm8 unHTkAYkqny2TQslck0Ol/cIYlx+TbDfMM3/55bSAsmjDApXT+rU2othPyL3j+TVpLu8 XzWooj7k/f0UMmA958lnQ2LYBWhMVyOzoyf+Q94b8+zXhn5zMF3kDSZ+v+570XJih7Bt WBl+1s/9Pnu9vVSR7fMYK8ZfT+3AMPTaHltutaJWck6/Q8sFOZan7nF72ZySxLEgVmR+ QA0ZtbgbqKecV+ENBdkeeVZJIxcWNzFpb7eaBYrDydFftll4wirrDXgmsqoVOBZTvrq4 dT+Q== X-Gm-Message-State: AOJu0YzFEUZ1z5Fj+hC07v9XMJe97uBWckBq4lx1FIIuNab5Jnk1CKsL Vg7FVN7qAOEJ9AlbG1xR+V1+jg== X-Google-Smtp-Source: AGHT+IFDWzJq6rMfDpAhRVsPkvt3aq+8wLO7SfLKHkJ7Qe3r2kJ5OYFxVdnfMhZkz3/7/YfVzMp1PA== X-Received: by 2002:a5d:56c3:0:b0:31f:e32f:a503 with SMTP id m3-20020a5d56c3000000b0031fe32fa503mr15621787wrw.20.1696978210960; Tue, 10 Oct 2023 15:50:10 -0700 (PDT) Received: from gpeter-l.lan (host-92-12-225-146.as13285.net. [92.12.225.146]) by smtp.gmail.com with ESMTPSA id j13-20020adfe50d000000b003196b1bb528sm13689547wrm.64.2023.10.10.15.50.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 15:50:10 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v2 17/20] arm64: dts: google: Add initial Google gs101 SoC support Date: Tue, 10 Oct 2023 23:49:25 +0100 Message-ID: <20231010224928.2296997-18-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog In-Reply-To: <20231010224928.2296997-1-peter.griffin@linaro.org> References: <20231010224928.2296997-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile phones. It features: * 4xA55 little cluster * 2xA76 Mid cluster * 2xX1 Big cluster This commit adds the basic device tree for gs101 (SoC). Further platform support will be added over time. Signed-off-by: Peter Griffin --- arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 +++++++++++++++++ arch/arm64/boot/dts/google/gs101-pinctrl.h | 32 + arch/arm64/boot/dts/google/gs101.dtsi | 503 +++++++ 5 files changed, 1817 insertions(+) create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..a5ed1b719488 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -107,6 +107,12 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_GOOGLE_TENSOR + bool "Google Tensor SoC fmaily" + depends on ARCH_EXYNOS + help + Support for ARMv8 based Google Tensor platforms. + config ARCH_SPARX5 bool "Microchip Sparx5 SoC family" select PINCTRL diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 30dd6347a929..a4ee7b628114 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y += broadcom subdir-y += cavium subdir-y += exynos subdir-y += freescale +subdir-y += google subdir-y += hisilicon subdir-y += intel subdir-y += lg diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi new file mode 100644 index 000000000000..ba88000c3ed8 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi @@ -0,0 +1,1275 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS101 SoC pin-mux and pin-config device tree source + * + * Copyright 2019-2023 Google LLC + * + */ + +#include "gs101-pinctrl.h" + +/* GPIO_ALIVE */ +&pinctrl_0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + ; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + ; + }; + + gpa3: gpa3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpa4: gpa4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpa5: gpa5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + , + ; + }; + + gpa9: gpa9-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa10: gpa10-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + }; + + uart15_bus: uart15-bus-pins { + samsung,pins = "gpa2-3", "gpa2-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart16_bus: uart16-bus-pins { + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart16_bus_rts: uart1-bus-rts-pins { + samsung,pins = "gpa3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + }; + + uart16_bus_tx_dat: uart1-bus-tx-dat-pins { + samsung,pins = "gpa3-1"; + samsung,pin-val = <1>; + }; + + uart16_bus_tx_con: uart1-bus-tx-con-pins { + samsung,pins = "gpa3-1"; + samsung,pin-function = <1>; + }; + + uart17_bus: uart17-bus-pins { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi15_bus: spi15-bus-pins { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi15_cs: spi15-cs-pins { + samsung,pins = "gpa4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +/* GPIO_FAR_ALIVE */ +&pinctrl_1 { + gpa6: gpa6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa7: gpa7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpa8: gpa8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa11: gpa11-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + ; + }; +}; + +/* GPIO_GSACORE */ +&pinctrl_2 { + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps2: gps2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +/* GPIO_GSACTRL */ +&pinctrl_3 { + gps3: gps3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +/* GPIO_HSI1 */ +&pinctrl_6 { + gph0: gph0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcie0_clkreq: pcie0-clkreq-pins{ + samsung,pins = "gph0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + + pcie0_perst: pcie0-perst-pins { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + }; +}; + +/* GPIO_HSI2 */ +&pinctrl_7 { + gph2: gph2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph3: gph3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph4: gph4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gph4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gph4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gph4-3", "gph4-4", "gph4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + ufs_rst_n: ufs-rst-n-pins { + samsung,pins = "gph3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + ufs_refclk_out: ufs-refclk-out-pins { + samsung,pins = "gph3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + pcie1_clkreq: pcie1-clkreq-pins { + samsung,pins = "gph2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + + pcie1_perst: pcie1-perst-pins { + samsung,pins = "gph2-0"; + samsung,pin-function = <1>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + }; +}; + +/* GPIO_PERIC0 */ +&pinctrl_4 { + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp3: gpp3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp4: gpp4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp5: gpp5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp6: gpp6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp7: gpp7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp8: gpp8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp9: gpp9-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp10: gpp10-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp11: gpp11-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp12: gpp12-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp13: gpp13-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp14: gpp14-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp15: gpp15-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp16: gpp16-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp17: gpp17-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp18: gpp18-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp19: gpp19-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* USI_PERIC0_UART_DBG */ + uart0_bus: uart0-bus-pins { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + disp_te_pri_on: disp-te-pri-on-pins { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0xf>; + }; + + disp_te_pri_off: disp-te-pri-off-pins { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0>; + }; + + disp_te_sec_on: disp-te-sec-on-pins { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0xf>; + }; + + disp_te_sec_off: disp-te-sec-off-pins { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0>; + }; + + sensor_mclk1_out: sensor-mclk1-out-pins { + samsung,pins = "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_fn: sensor-mclk1-fn-pins { + samsung,pins = "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_out: sensor-mclk2-out-pins { + samsung,pins = "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_fn: sensor-mclk2-fn-pins { + samsung,pins = "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk3_out: sensor-mclk3-out-pins { + samsung,pins = "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk3_fn: sensor-mclk3-fn-pins { + samsung,pins = "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk4_out: sensor-mclk4-out-pins { + samsung,pins = "gpp9-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk4_fn: sensor-mclk4-fn-pins { + samsung,pins = "gpp9-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk5_out: sensor-mclk5-out-pins { + samsung,pins = "gpp11-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk5_fn: sensor-mclk5-fn-pins { + samsung,pins = "gpp11-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk6_out: sensor-mclk6-out-pins { + samsung,pins = "gpp13-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk6_fn: sensor-mclk6-fn-pins { + samsung,pins = "gpp13-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk7_out: sensor-mclk7-out-pins { + samsung,pins = "gpp15-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk7_fn: sensor-mclk7-fn-pins { + samsung,pins = "gpp15-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk8_out: sensor-mclk8-out-pins { + samsung,pins = "gpp17-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk8_fn: sensor-mclk8-fn-pins { + samsung,pins = "gpp17-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c14_bus: hsi2c14-bus-pins { + samsung,pins = "gpp18-0", "gpp18-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart14_bus_single: uart14-bus-pins { + samsung,pins = "gpp18-0", "gpp18-1", + "gpp18-2", "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi14_bus: spi14-bus-pins { + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi14_cs: spi14-cs-pins { + samsung,pins = "gpp18-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi14_cs_func: spi14-cs-func-pins { + samsung,pins = "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c8_bus: hsi2c8-bus-pins { + samsung,pins = "gpp16-0", "gpp16-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-pud-pdn = ; + }; + + uart8_bus_single: uart8-bus-pins { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2", + "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi8_bus: spi8-bus-pins { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi8_cs: spi8-cs-pins { + samsung,pins = "gpp16-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi8_cs_func: spi8-cs-func-pins { + samsung,pins = "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c7_bus: hsi2c7-bus-pins { + samsung,pins = "gpp14-0", "gpp14-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart7_bus_single: uart7-bus-pins { + samsung,pins = "gpp14-0", "gpp14-1", + "gpp14-2", "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi7_bus: spi7-bus-pins { + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi7_cs: spi7-cs-pins { + samsung,pins = "gpp14-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi7_cs_func: spi7-cs-func-pins { + samsung,pins = "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c6_bus: hsi2c6-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart6_bus_single: uart6-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1", + "gpp12-2", "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi6_bus: spi6-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi6_cs: spi6-cs-pins { + samsung,pins = "gpp12-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi6_cs_func: spi6-cs-func-pins { + samsung,pins = "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c5_bus: hsi2c5-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart5_bus_single: uart5-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1", + "gpp10-2", "gpp10-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi5_bus: spi5-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; + samsung,pin-drv = ; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + spi5_cs_func: spi5-cs-func-pins { + samsung,pins = "gpp10-3"; + samsung,pin-drv = ; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + hsi2c4_bus: hsi2c4-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart4_bus_single: uart4-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1", + "gpp8-2", "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi4_bus: spi4-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi4_cs: spi4-cs-pins { + samsung,pins = "gpp8-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi4_cs_func: spi4-cs-func-pins { + samsung,pins = "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c3_bus: hsi2c3-bus-pins { + samsung,pins = "gpp6-0", "gpp6-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart3_bus_single: uart3-bus-pins { + samsung,pins = "gpp6-0", "gpp6-1", + "gpp6-2", "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi3_bus: spi3-bus-pins { + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi3_cs: spi3-cs-pins { + samsung,pins = "gpp6-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi3_cs_func: spi3-cs-func-pins { + samsung,pins = "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c2_bus: hsi2c2-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart2_bus_single: uart2-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1", + "gpp4-2", "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi2_cs: spi2-cs-pins { + samsung,pins = "gpp4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi2_cs_func: spi2-cs-func-pins { + samsung,pins = "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c1_bus: hsi2c1-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart1_bus_single: uart1-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1", + "gpp2-2", "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi1_cs: spi1-cs-pins { + samsung,pins = "gpp2-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi1_cs_func: spi1-cs-func-pins { + samsung,pins = "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; +}; + +/* GPIO_PERIC1 */ +&pinctrl_5 { + gpp20: gpp20-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp21: gpp21-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp22: gpp22-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp23: gpp23-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp24: gpp24-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp25: gpp25-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp26: gpp26-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp27: gpp27-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + hsi2c13_bus: hsi2c13-bus-pins { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart13_bus_single: uart13-bus-pins { + samsung,pins = "gpp25-0", "gpp25-1", + "gpp25-2", "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi13_bus: spi13-bus-pins { + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi13_cs: spi13-cs-pins { + samsung,pins = "gpp25-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi13_cs_func: spi13-cs-func-pins { + samsung,pins = "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c12_bus: hsi2c12-bus-pins { + samsung,pins = "gpp23-4", "gpp23-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart12_bus_single: uart12-bus-pins { + samsung,pins = "gpp23-4", "gpp23-5", + "gpp23-6", "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi12_bus: spi12-bus-pins { + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi14_cs2: spi14-cs2-pins { + samsung,pins = "gpp23-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi12_cs: spi12-cs-pins { + samsung,pins = "gpp23-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi12_cs_func: spi12-cs-func-pins { + samsung,pins = "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c11_bus: hsi2c11-bus-pins { + samsung,pins = "gpp23-0", "gpp23-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart11_bus_single: uart11-bus-pins { + samsung,pins = "gpp23-0", "gpp23-1", + "gpp23-2", "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi11_bus: spi11-bus-pins { + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi11_cs: spi11-cs-pins { + samsung,pins = "gpp23-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi11_cs_func: spi11-cs-func-pins { + samsung,pins = "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c10_bus: hsi2c10-bus-pins { + samsung,pins = "gpp21-0", "gpp21-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart10_bus_single: uart10-bus-pins { + samsung,pins = "gpp21-0", "gpp21-1", + "gpp21-2", "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi10_bus: spi10-bus-pins { + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi10_cs: spi10-cs-pins { + samsung,pins = "gpp21-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi10_cs_func: spi10-cs-func-pins { + samsung,pins = "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c9_bus: hsi2c9-bus-pins { + samsung,pins = "gpp20-4", "gpp20-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart9_bus_single: uart9-bus-pins { + samsung,pins = "gpp20-4", "gpp20-5", + "gpp20-6", "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi9_bus: spi9-bus-pins { + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi9_cs: spi9-cs-pins { + samsung,pins = "gpp20-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi9_cs_func: spi9-cs-func-pins { + samsung,pins = "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + hsi2c0_bus: hsi2c0-bus-pins { + samsung,pins = "gpp20-0", "gpp20-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + uart0_bus_single: uart0-bus-pins { + samsung,pins = "gpp20-0", "gpp20-1", + "gpp20-2", "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi0_cs: spi0-cs-pins { + samsung,pins = "gpp20-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + spi0_cs_func: spi0-cs-func-pins { + samsung,pins = "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; +}; + diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h new file mode 100644 index 000000000000..16c54888f4bb --- /dev/null +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Pinctrl binding constants for GS101 + * + * Copyright (c) 2020-2023 Google, LLC. + */ + +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ +#define __DT_BINDINGS_PINCTRL_GS101_H__ + +#define GS101_PIN_PULL_NONE 0 +#define GS101_PIN_PULL_DOWN 1 +#define GS101_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define GS101_PIN_PDN_OUT0 0 +#define GS101_PIN_PDN_OUT1 1 +#define GS101_PIN_PDN_INPUT 2 +#define GS101_PIN_PDN_PREV 3 + +/* GS101 drive strengths */ +#define GS101_PIN_DRV_2_5_MA 0 +#define GS101_PIN_DRV_5_MA 1 +#define GS101_PIN_DRV_7_5_MA 2 +#define GS101_PIN_DRV_10_MA 3 + +#define GS101_PIN_FUNC_INPUT 0 +#define GS101_PIN_FUNC_OUTPUT 1 +#define GS101_PIN_FUNC_2 2 +#define GS101_PIN_FUNC_3 3 + +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi new file mode 100644 index 000000000000..28b18c594350 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs101.dtsi @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS101 SoC + * + * Copyright 2019-2023 Google LLC + * + */ + +#include +#include +#include + +/ { + compatible = "google,gs101"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + pinctrl5 = &pinctrl_5; + pinctrl6 = &pinctrl_6; + pinctrl7 = &pinctrl_7; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* TODO replace with CCF clock */ + dummy_clk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12345>; + clock-output-names = "pclk"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0000>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0100>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0200>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0300>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0400>; + enable-method = "psci"; + cpu-idle-states = <&ENYO_CPU_SLEEP>; + capacity-dmips-mhz = <620>; + dynamic-power-coefficient = <284>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0500>; + enable-method = "psci"; + cpu-idle-states = <&ENYO_CPU_SLEEP>; + capacity-dmips-mhz = <620>; + dynamic-power-coefficient = <284>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0600>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <650>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0700>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <650>; + }; + + idle-states { + entry-method = "psci"; + + ANANKE_CPU_SLEEP: cpu-ananke-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <160>; + min-residency-us = <2000>; + }; + + ENYO_CPU_SLEEP: cpu-enyo-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <150>; + exit-latency-us = <190>; + min-residency-us = <2500>; + }; + + HERA_CPU_SLEEP: cpu-hera-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <235>; + exit-latency-us = <220>; + min-residency-us = <3500>; + }; + }; + }; + + /* bootloader requires ect node */ + ect { + parameter_address = <0x90000000>; + parameter_size = <0x53000>; + }; + + ext_24_5m: clock-1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "oscclk"; + }; + + ext_200m: clock-2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "ext-200m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gsa_reserved_protected: gsa@90200000 { + reg = <0x0 0x90200000 0x400000>; + no-map; + }; + + tpu_fw_reserved: tpu-fw@93000000 { + reg = <0x0 0x93000000 0x1000000>; + no-map; + }; + + aoc_reserve: aoc@94000000 { + reg = <0x0 0x94000000 0x03000000>; + no-map; + }; + + abl_reserved: abl@f8800000 { + reg = <0x0 0xf8800000 0x02000000>; + no-map; + }; + + dss_log_reserved: dss-log-reserved@fd3f0000 { + reg = <0 0xfd3f0000 0x0000e000>; + no-map; + }; + + debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { + reg = <0 0xfd3fe000 0x00001000>; + no-map; + }; + + bldr_log_reserved: bldr-log-reserved@fd800000 { + reg = <0 0xfd800000 0x00100000>; + no-map; + }; + + bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { + reg = <0 0xfd900000 0x00002000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24576000>; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + cmu_misc: clock-controller@10010000 { + compatible = "google,gs101-cmu-misc"; + reg = <0x0 0x10010000 0x8000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>; + clock-names = "oscclk", "dout_cmu_misc_bus"; + }; + + watchdog_cl0: watchdog@10060000 { + compatible = "google,gs101-wdt"; + reg = <0x0 0x10060000 0x100>; + interrupts = ; + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + }; + + watchdog_cl1: watchdog@10070000 { + compatible = "google,gs101-wdt"; + reg = <0x0 0x10070000 0x100>; + interrupts = ; + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x10400000 0x10000>, /* GICD */ + <0x0 0x10440000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + sysreg_peric0: syscon@10821000 { + compatible = "google,gs101-peric0-sysreg", "syscon"; + reg = <0x0 0x10821000 0x40000>; + }; + + /* GPIO_PERIC0 */ + pinctrl_4: pinctrl@10840000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x10840000 0x00001000>; + interrupts = ; + }; + + serial_0: serial@10a00000 { + compatible = "google,gs101-uart"; + reg = <0x0 0x10a00000 0xc0>; + reg-io-width = <4>; + samsung,uart-fifosize = <256>; + interrupts = ; + clocks = <&dummy_clk 0>, <&dummy_clk 0>; + clock-names = "uart", "clk_uart_baud0"; + }; + + /* GPIO_PERIC1 */ + pinctrl_5: pinctrl@10c40000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x10C40000 0x00001000>; + interrupts = ; + }; + + sysreg_peric1: syscon@10c21000 { + compatible = "google,gs101-peric1-sysreg", "syscon"; + reg = <0x0 0x10C21000 0x40000>; + }; + + /* GPIO_HSI1 */ + pinctrl_6: pinctrl@11840000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x11840000 0x00001000>; + interrupts = ; + }; + + /* GPIO_HSI2 */ + pinctrl_7: pinctrl@14440000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x14440000 0x00001000>; + interrupts = ; + }; + + cmu_apm: clock-controller@17400000 { + compatible = "google,gs101-cmu-apm"; + reg = <0x0 0x17400000 0x8000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + + sysreg_apm: syscon@174204e0 { + compatible = "google,gs101-apm-sysreg", "syscon"; + reg = <0x0 0x174204e0 0x1000>; + }; + + pmu_system_controller: system-controller@17460000 { + compatible = "google,gs101-pmu", "syscon"; + reg = <0x0 0x17460000 0x10000>; + }; + + /* GPIO_ALIVE */ + pinctrl_0: pinctrl@174d0000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x174d0000 0x00001000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "google,gs101-wakeup-eint"; + }; + }; + + /* GPIO_FAR_ALIVE */ + pinctrl_1: pinctrl@174e0000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x174e0000 0x00001000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "google,gs101-wakeup-eint"; + }; + }; + + /* GPIO_GSACTRL */ + pinctrl_3: pinctrl@17940000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x17940000 0x00001000>; + }; + + /* GPIO_GSACORE */ + pinctrl_2: pinctrl@17a80000 { + compatible = "google,gs101-pinctrl"; + reg = <0x0 0x17a80000 0x00001000>; + }; + + cmu_top: clock-controller@1e080000 { + compatible = "google,gs101-cmu-top"; + reg = <0x0 0x1e080000 0x8000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + }; +}; + +#include "gs101-pinctrl.dtsi"