From patchwork Sat Oct 7 04:49:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1844692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=SNG6vSvV; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S2XsX5QSGz1yq7 for ; Sat, 7 Oct 2023 15:50:05 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 03C2A385B52A for ; Sat, 7 Oct 2023 04:50:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 2603D3858439 for ; Sat, 7 Oct 2023 04:49:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2603D3858439 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696654189; x=1728190189; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4gjByoETQBunJldzKQLakll9ojTF9RSER2rFV8Z2jSo=; b=SNG6vSvVQDryxcriIdmEdBuUFv5vxQDb728eaiQlq2lo2B9nnIHB3Guo BA+jqjzGy2WPHHT7tD2DZKZmmBbtkrD0FmYrJ/q3pdhetA2EGjvK5kOiq pO4OuNc2+837RcKJf/Hxi9Db1yJH1YjF7re4ikagGKMZKD78gP7JGnPZb rdqvPrUxvQMxSmG5as1AMPnJLC4Dt5JkOq7e+XMbyKsWSVia/ZdonemY6 PfNycDRrmG2o6ly8eOKWiIbdSoaTI2BTA1RDXIIw5XROmEo5+zPyuxb69 T3+KDKTqy/LT66RA8JQC7FFdVInmNRQNVR6icD9RnVE6az+spKKqFZn/N w==; X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="470161633" X-IronPort-AV: E=Sophos;i="6.03,204,1694761200"; d="scan'208";a="470161633" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 21:49:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="876191561" X-IronPort-AV: E=Sophos;i="6.03,204,1694761200"; d="scan'208";a="876191561" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga004.jf.intel.com with ESMTP; 06 Oct 2023 21:49:45 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id DB5991005676; Sat, 7 Oct 2023 12:49:44 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for legitimize address PR/111634 Date: Sat, 7 Oct 2023 12:49:43 +0800 Message-Id: <20231007044943.4153909-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Given we have RTL as below. (plus:DI (mult:DI (reg:DI 138 [ g.4_6 ]) (const_int 8 [0x8])) (lo_sum:DI (reg:DI 167) (symbol_ref:DI ("f") [flags 0x86] ) )) When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case, the fp will be the lo_sum operand as above. We have assumption that the fp is reg but actually not here. It will have ICE when building with option --enable-checking=rtl. This patch would like to fix it by adding the REG_P to ensure the operand is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this fix when build with --enable-checking=rtl. PR target/111634 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_address): Bugfix. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d5446b63dbf..2b839241f1a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2042,7 +2042,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, { rtx index = XEXP (base, 0); rtx fp = XEXP (base, 1); - if (REGNO (fp) == VIRTUAL_STACK_VARS_REGNUM) + if (REG_P (fp) && REGNO (fp) == VIRTUAL_STACK_VARS_REGNUM) { /* If we were given a MULT, we must fix the constant