From patchwork Fri Sep 29 05:38:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=MP94yn5l; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfLF6G74z1ypf for ; Fri, 29 Sep 2023 15:39:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232648AbjI2Fj0 (ORCPT ); Fri, 29 Sep 2023 01:39:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229541AbjI2FjZ (ORCPT ); Fri, 29 Sep 2023 01:39:25 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEC1D1B0 for ; Thu, 28 Sep 2023 22:39:22 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-9adca291f99so1772556966b.2 for ; Thu, 28 Sep 2023 22:39:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965961; x=1696570761; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xK/3dVXqgg1IkWVSTABE0q0pHwVE+qQyK/K/05HOKqI=; b=MP94yn5lefcYCv1t7k58ixpP7BpsEZ+B6+z5fukqsaO9/gR367HwesPsK+3bD6ABLg yyDzTvdFZMTUT5fkUsYcOvYwXekCoNC+ihUZyZr8zS0tOfBGK/icABHEDFUCy+d3pVC/ awXFA5OZWV6IrcmgploK2OKU03GFbi5vjxpv4xQCx+W3vi6K9zWYSmlpx3oB47OSzL/Q Lu/HMZ/UV8Zuq+2m1u3QSJIphz7VcQ9Y2SG46BP2U50sdCTHrv44fRvzCIFcPn6Ns5p3 qdb0/64XTfXbqqc3cY+2ROiTTXRbcvVqL+JkjEzhxRtbyZku+xttoj9JECo+FZtqL6bP I9jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965961; x=1696570761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xK/3dVXqgg1IkWVSTABE0q0pHwVE+qQyK/K/05HOKqI=; b=qQdql4y9YTSouyOubyB1fcgcX+/R5xaNQTb4i4SEA5zBScAlPrOMTR2QVhGBxxmbWy JdUTf0857dXApEBsVEdXXpUP2/OE/9k2vEnyhl/y9gTFGzUIWRZI8zTIKSjoctl20L0U FL91Usn+hvK4xxFKY1V5V4uS2Ce/oA/1XVmp4YUGssYey9euTPZPmpK0qVRn+y++G43E ChC9KT3frZ9/fRHYuz3vn4DDUEPewjSyoju5ydCqDXh2VlHrcCjeVEF180sXVtluaFRQ kmyurnT5ovK0d8AGVULyyxrJwY6yIPY1E7ervG6ouhrDVto2/qSmfl0s1bm6dJmjlh37 ADuw== X-Gm-Message-State: AOJu0YxpOE/3jTapuzvXppaBJMbogp5GEBY/Ttt1Mhct9NlMAxcErmaj a5SdkZ/uxu4kdYgBAZgdUkYJRg== X-Google-Smtp-Source: AGHT+IGhPIW0cOY4Oj0jbr8Hz4FWOAplpVyKIsi0LBN3q0xMZGidv8zfi4b0ooumLJKfQ/scVcl5gg== X-Received: by 2002:a17:906:3109:b0:9b2:9d6f:2949 with SMTP id 9-20020a170906310900b009b29d6f2949mr2864815ejx.57.1695965961447; Thu, 28 Sep 2023 22:39:21 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:20 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/28] dt-bindings: serial: renesas,scif: document r9a08g045 support Date: Fri, 29 Sep 2023 08:38:48 +0300 Message-Id: <20230929053915.1530607-2-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Document support for the Serial Communication Interface with FIFO (SCIF) available in the Renesas RZ/G3S (R9A08G045) SoC. SCIF interface in Renesas RZ/G3S is similar to the one available in RZ/G2L. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected tags Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 99030fc18c45..4610a5bd580c 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -79,6 +79,7 @@ properties: - enum: - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five - renesas,scif-r9a07g054 # RZ/V2L + - renesas,scif-r9a08g045 # RZ/G3S - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback reg: From patchwork Fri Sep 29 05:38:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=iXjiS5Mx; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfLF3J8pz1ynm for ; Fri, 29 Sep 2023 15:39:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232678AbjI2Fj3 (ORCPT ); Fri, 29 Sep 2023 01:39:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232651AbjI2Fj1 (ORCPT ); Fri, 29 Sep 2023 01:39:27 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE539199 for ; Thu, 28 Sep 2023 22:39:24 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-99bf3f59905so1797709766b.3 for ; Thu, 28 Sep 2023 22:39:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965963; x=1696570763; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KeROYzXT5X0vhWub03MpkUt5t0C3EfcKOwYZPDuBwCY=; b=iXjiS5MxM9RIAEPbwtRNcJX+E8z0R0L93eGAAb5VokHuXB7prx9WreoLZ/twhVQ4CT fNA7+ur0PJeFCYSBBeTeDkRPMB38/vfDFRTrfff9015aCVhGMHPaOumXhCZSNZipWmjr dw4qNcYNa7GOWt1ERRsNBH16MXTivAB7j5B+4E1rveqQI31jtnpddCyKktl49Is9DOaP I3DFzKtSKIBnleD5CcZj1HnRULeIz4NtxaZfnQACtMZhPiGvzXIloMVOxX5GN856dzEp L/MvpSJVhIbLhJiUq5bHQ75vsN8kfCHVediG64G/tc+bhjCTuwZiNF5J80p4JAiv6UI0 TWGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965963; x=1696570763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KeROYzXT5X0vhWub03MpkUt5t0C3EfcKOwYZPDuBwCY=; b=CGzD3Dla0TKXHA+E+NDWaxoMn4mlFHW1Hm0pjeoQPG5+GE7/itfyW5O5DtMvONYlIQ ZDSA9OR2dL6wurlvJfQYuX6hSP4zVK55qMFs2jFUMPF7hCOH4zDix+6rmCSt9RFRJQm8 taOn0Kcve1bouzuB+HwZYWIc8gPS17M1UbfXh9deON8nOBaLq+dPw3jRo0bt6FA8MTJC RW91TvYSwqFZqgtw7TJfTc2xkNxungQ1b+OAVFHxeBYLOaL9bLzdWut9Yi5NBamEcTH0 cM83lFAp33n/cJifkrhj+TS9RHkIg7BdyMRtXKWTUc0oth4qZ8blOfBM0yfRNdddQunW BtKQ== X-Gm-Message-State: AOJu0Yyra4HZfp5FzbkBar21Uh1S3HXKt1UyHWiJHi2CGSr+ptnmGKBc oX+LkoGYsItz51pwjzDgEqhnCA== X-Google-Smtp-Source: AGHT+IGADEnpx3heQWFHdL/4NzaHz21fAG/RuwtTOzG7s3wQgRBxCwzfIgq/eWl2F+fu8QtXUo2AmA== X-Received: by 2002:a17:906:100c:b0:9a2:24f9:fabe with SMTP id 12-20020a170906100c00b009a224f9fabemr3031122ejm.66.1695965963508; Thu, 28 Sep 2023 22:39:23 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:23 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 02/28] clk: renesas: rzg2l: wait for status bit of SD mux before continuing Date: Fri, 29 Sep 2023 08:38:49 +0300 Message-Id: <20230929053915.1530607-3-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Hardware user manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf, chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for SD clock switching status. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - initialized msk drivers/clk/renesas/rzg2l-cpg.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 9baae7bb7094..5343d04fd70d 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -188,7 +188,8 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) u32 off = GET_REG_OFFSET(hwdata->conf); u32 shift = GET_SHIFT(hwdata->conf); const u32 clk_src_266 = 2; - u32 bitmask; + u32 msk, val, bitmask; + int ret; /* * As per the HW manual, we should not directly switch from 533 MHz to @@ -202,14 +203,10 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) * the index to value mapping is done by adding 1 to the index. */ bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; + msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; if (index != clk_src_266) { - u32 msk, val; - int ret; - writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off); - msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, !(val & msk), 100, CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); @@ -221,7 +218,13 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) writel(bitmask | ((index + 1) << shift), priv->base + off); - return 0; + ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, + !(val & msk), 100, + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); + if (ret) + dev_err(priv->dev, "failed to switch clk source\n"); + + return ret; } static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) From patchwork Fri Sep 29 05:38:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841073 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=bbhcGyID; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfLK4dPHz1ynm for ; Fri, 29 Sep 2023 15:39:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232697AbjI2Fje (ORCPT ); Fri, 29 Sep 2023 01:39:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232675AbjI2Fj3 (ORCPT ); Fri, 29 Sep 2023 01:39:29 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAFA21A7 for ; Thu, 28 Sep 2023 22:39:27 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-9b275afb6abso61238066b.1 for ; Thu, 28 Sep 2023 22:39:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965966; x=1696570766; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=au5TjHif1NdZJ2Z7FrkXoOxh3rDBA3mHRRDa4P1Qy7A=; b=bbhcGyIDn/XHtayop1ONScEnDCLyGTMRomMTmeZAofjitENiGonQkKdWcLLh4Qr2w7 cFh0WJ3L/5YY72cDiDQD4/JbcDylEQXEucdtrHtshfwVe4ukATDoapBuM6yXl4XaPMCG VLJRe87tDkXKTxGr0rxVGb+pwFKuox0zE5+hLuROIKe286r+bjIB9MAm2KHnWJaZc+m4 Ass2BnhuDrxhgPwZAk1IMAsWITcNY6/qwOxEjJipIp4CnsskjLsHteqE/OzAOGHaXV5H ksHaNpHu6GkO781b3ftL6C4jOjfuMm5sFKR0qpptxNdxJSsnkJDsUdkYEcHonyI+aT+B GSvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965966; x=1696570766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=au5TjHif1NdZJ2Z7FrkXoOxh3rDBA3mHRRDa4P1Qy7A=; b=XT2Oh6W6l68AK+NCKmd0n9fRbsFDUePR/d//tgYUQDJ7W7dGToqMJbzAQz+cWyhpo1 XxJblLQClkVepzTFK26ebAAjGqLZ608IXRDM9CeMkZ65WvaRgnWJqoYH6uWvI/c2iUHW O85fuJHPuja50x84wsL8jEfupYsNvYb5ok8CeeNtQsonTY3SGSGC9f+CYkgHTJY7kbux Qc5qolXmdZapAV49iCkL+cnF/KL9fZ7F0mTGxiaaedOjdE2YH9FhfyJHEgvIAIznY5G5 80/eN0REZARo7FljQdVLfHK15VsCAO2Kw+itAYras6qgxyZulk/7mYZqNhHsUwQlqg+3 hnQQ== X-Gm-Message-State: AOJu0YyfOUNk01cYNz4HgU+h4rioEo6F1HHyHgQPrke5dmrw91kOO/vk rnMMZO6oXLM7cqHz2XsfIjt/PQ== X-Google-Smtp-Source: AGHT+IFum4h4g8el3Uw1w6DcCrPLqgJojSzrnCceoMYUy9pG/hToo9w/gNJaOE/EEubYcVZDtuSoyw== X-Received: by 2002:a17:907:b60b:b0:9b2:cee1:1f82 with SMTP id vl11-20020a170907b60b00b009b2cee11f82mr1301071ejc.7.1695965965746; Thu, 28 Sep 2023 22:39:25 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:25 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 03/28] clk: renesas: rzg2l: lock around writes to mux register Date: Fri, 29 Sep 2023 08:38:50 +0300 Message-Id: <20230929053915.1530607-4-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea SD MUX output (SD0) is further divided by 4 in G2{L, UL}. The divided clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which means a rate request for it is propagated to the MUX and could reach rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0. Add proper locking to avoid concurrent access on SD MUX set rate registers. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - adapted delay_us to 10us - adapted CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US to 200us; tested with this adjustements on RZ/G3S and RZ/G2L SoCs drivers/clk/renesas/rzg2l-cpg.c | 23 +++++++++++++---------- drivers/clk/renesas/rzg2l-cpg.h | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 5343d04fd70d..0679f2c7649e 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -189,6 +189,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) u32 shift = GET_SHIFT(hwdata->conf); const u32 clk_src_266 = 2; u32 msk, val, bitmask; + unsigned long flags; int ret; /* @@ -204,23 +205,25 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) */ bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; + spin_lock_irqsave(&priv->rmw_lock, flags); if (index != clk_src_266) { writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off); - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 100, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); - if (ret) { - dev_err(priv->dev, "failed to switch clk source\n"); - return ret; - } + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, + !(val & msk), 10, + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); + if (ret) + goto unlock; } writel(bitmask | ((index + 1) << shift), priv->base + off); - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 100, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, + !(val & msk), 10, + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); +unlock: + spin_unlock_irqrestore(&priv->rmw_lock, flags); + if (ret) dev_err(priv->dev, "failed to switch clk source\n"); diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 0b28870a6f9d..097fd8f61680 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -43,7 +43,7 @@ #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) -#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000 +#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 200 /* n = 0/1/2 for PLL1/4/6 */ #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) From patchwork Fri Sep 29 05:38:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=M8Scall2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfLl4DjJz1ynm for ; Fri, 29 Sep 2023 15:39:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232625AbjI2Fj5 (ORCPT ); Fri, 29 Sep 2023 01:39:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232692AbjI2Fjd (ORCPT ); Fri, 29 Sep 2023 01:39:33 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4982B195 for ; Thu, 28 Sep 2023 22:39:29 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-99c3c8adb27so1842013366b.1 for ; Thu, 28 Sep 2023 22:39:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965968; x=1696570768; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TQ5vJt4uEBZYxaoCUMCaBdZYOuAagvaFox1SiyVlaFY=; b=M8Scall27LM9JZIEc0lNb6z87WIUQzcanG8ecsXwR1YcH2cZKsl2X/RsuQoIeTR0Y/ oVs7ZYbCW50dhWM56t3/ofoOpo7n9YAMB7xpmwmKroD+ymLuAHcpWeqzp7hQWQX9SbZj VEP+hRKJJFLGfIeyItINIlDYAcIQkqPq61AdLTa4mKFSmNzKxRkSjbnLBKUeyhK8+avJ +7+tvkmHBOialyd1xxGu8pOvdfr+qp0oFs+d3PfROkVvl/JeAG9w2WjbvXJucBT+KtqB maZLISG48QzeFqyOBYnQ77eiu3yL9IasvuGkxknYgYB7dzEoU7BScIo3SHssTA1KDI59 dyjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965968; x=1696570768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TQ5vJt4uEBZYxaoCUMCaBdZYOuAagvaFox1SiyVlaFY=; b=AyHbuFdCqSRxAD/Ll7TPv05bVjFBJ81egP+cnyUOhOoZnfOMIqB0YgoEuY3W93DUwF juyyzx/6T4ae8QUP1TqcQXsxvZGGd5gHEgiNMntgGktrlIyoiH+XcPkVlVqzqUsP3Zvf oZGwoZCeYWIdjNlEv2JrCAZaz+1ZblHsccpuUGROKj51PS64XCvvDmsnPPmZoSLW9P2F UYOPV4KorbQWY9vcWkqNUyfgpn4/I8jGFP7qdCw+aNDO4vRvn5EhDuwzzdOjJ8kEz+oi jqCbXr2+aYsHxplxKckun3N4hjWPmGQRqLOmr2BZGmDq7wUF52mOg81GBpD9qMHaXDz7 935g== X-Gm-Message-State: AOJu0YzQzH9oTeQStEd8wL2cqDMuBnWwMHiPDAPXk/H8y29kbDGekSka mcXJQlzvTcy+fIuozesDQJKXmg== X-Google-Smtp-Source: AGHT+IF2d7y2sZctyVqepi31GT6G13UI30T9U1ZXO4+TvKL35jVYdGIA1Qbh0TvHWtTX5d5AgXLNmQ== X-Received: by 2002:a17:907:2717:b0:9b2:d78c:aff4 with SMTP id w23-20020a170907271700b009b2d78caff4mr175767ejk.74.1695965967847; Thu, 28 Sep 2023 22:39:27 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 04/28] clk: renesas: rzg2l: trust value returned by hardware Date: Fri, 29 Sep 2023 08:38:51 +0300 Message-Id: <20230929053915.1530607-5-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Initial value of CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. Hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that setting 0 is prohibited. The rzg2l_cpg_sd_clk_mux_get_parent() should just read CPG_PL2SDHI_DSEL, trust the value and return the proper clock parent index based on the read value. Do this. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - Used "return val ? val - 1 : 0;" drivers/clk/renesas/rzg2l-cpg.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 0679f2c7649e..6f50f0329ecf 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -238,14 +238,8 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) val >>= GET_SHIFT(hwdata->conf); val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); - if (val) { - val--; - } else { - /* Prohibited clk source, change it to 533 MHz(reset value) */ - rzg2l_cpg_sd_clk_mux_set_parent(hw, 0); - } - return val; + return val ? val - 1 : 0; } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { From patchwork Fri Sep 29 05:38:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841075 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=Hrado1My; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfLn53qKz1ynm for ; Fri, 29 Sep 2023 15:40:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232740AbjI2Fj7 (ORCPT ); Fri, 29 Sep 2023 01:39:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232706AbjI2Fje (ORCPT ); Fri, 29 Sep 2023 01:39:34 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D1E71BD for ; Thu, 28 Sep 2023 22:39:31 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-9b281a2aa94so1213229966b.2 for ; Thu, 28 Sep 2023 22:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965970; x=1696570770; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QnqQLNYZz3xo/Z2CLQzgm+cKizcANRje7hedbfOoLFU=; b=Hrado1MyFwyR7mvK71RCyzFzGbXu9MJSQDBMIk2zhzioAc+6XROHOWJB/cBcbuTfUF W9Fm6EFk+wf1A5DJSHTmyD1yLcFfzj8xGQQWeoVFGy481cmja3fakRuMwIxflcPE/ApU B8wXyUSU73HhUFi4TldIQZmkFSRLHg3zuT9GGd7OkoQYGf6r3Wz3ocGgmOCtOJ41uCUB tbGTrSoWpb65wx9bUoj55JsJJO3DN12Bvi6EE3ahDNonoccdVYvf0hN4igMSAq26ka9Y syyRKAzK93j3OAhtIpDxdWvlD6oqCH0yT7bA/E3zGxGdTf+fpKUzhNCiG6WLLiQJwwwK RmuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965970; x=1696570770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QnqQLNYZz3xo/Z2CLQzgm+cKizcANRje7hedbfOoLFU=; b=GXgNsBCVAyjpoErP6efcjftKNWS7rp33b/TrmO6jyz+UKPGZskE8p8LA+T939AZ7g6 idnbYdXPiyQbufZvjAb6uDzWJmOxf5pIcl6M0SBEENOsPe+/pRDc5Zt+fcsolKGOhecE ybvV4DpI6ROaYCUZrShx/9lK2imzN6yYmP6lFXaEzZqA9eom6P8ekaVxVcpK2ZdEFL4/ ZHHcOgbkvfUC3dgxgmyRHzuHaxWmDwmTwAs72gifwzRUORgH9WZTX82i+0yblD1GsJ3X zYq4vJcxNtNAWnd/B7f98xqnw/8ZnW6J5BkFii+BC4NpDM61D1Jxu5GaADY2iFwv032M e60g== X-Gm-Message-State: AOJu0Yz523fGOR1fw3HP4y1ZevRwtl7bBcYvWfBUV/+ukxyb9N+4Y1an h5Km00SANASY+QHDPrwKCoEf4w== X-Google-Smtp-Source: AGHT+IHQNetWLkVJ62VPE+HyiTqj5WFfnB+Bs5B1knSVeh9ea0t+7zjVn4DhCdK1IlZdfEVAxrGMkQ== X-Received: by 2002:a17:906:3019:b0:9b2:73b3:29a1 with SMTP id 25-20020a170906301900b009b273b329a1mr3092024ejz.23.1695965969759; Thu, 28 Sep 2023 22:39:29 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:29 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 05/28] clk: renesas: rzg2l: fix computation formula Date: Fri, 29 Sep 2023 08:38:52 +0300 Message-Id: <20230929053915.1530607-6-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea According to hardware manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf) the computation formula for PLL rate is as follows: Fout = ((m + k/65536) * Fin) / (p * 2^s) and k has values in range [-32768, 32767]. Dividing k by 65536 with integer variables leads all the time to zero. Thus we may have slight differences b/w what has been set vs. what is displayed. Thus, get rid of this and decompose the formula before dividing k by 65536. Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - used mul_u64_u32_shr() drivers/clk/renesas/rzg2l-cpg.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 6f50f0329ecf..f411e428196c 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -695,18 +695,18 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, struct pll_clk *pll_clk = to_pll(hw); struct rzg2l_cpg_priv *priv = pll_clk->priv; unsigned int val1, val2; - unsigned int mult = 1; - unsigned int div = 1; + u64 rate; if (pll_clk->type != CLK_TYPE_SAM_PLL) return parent_rate; val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); - mult = MDIV(val1) + KDIV(val1) / 65536; - div = PDIV(val1) << SDIV(val2); - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); + rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + (s16)KDIV(val1), + 16 + SDIV(val2)); + + return DIV_ROUND_CLOSEST_ULL(rate, PDIV(val1)); } static const struct clk_ops rzg2l_cpg_pll_ops = { From patchwork Fri Sep 29 05:38:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=C4lp08O6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfLr2XGnz1yp0 for ; Fri, 29 Sep 2023 15:40:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232770AbjI2FkC (ORCPT ); Fri, 29 Sep 2023 01:40:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232662AbjI2Fj6 (ORCPT ); Fri, 29 Sep 2023 01:39:58 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 359521BF for ; Thu, 28 Sep 2023 22:39:33 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-9ad8bf9bfabso1842762166b.3 for ; Thu, 28 Sep 2023 22:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965971; x=1696570771; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Tx8IsOEvb8qkvUy2Or6MBahI0OwwMce9fHoVPFho48=; b=C4lp08O6yska7znKdYMmclZfGa3X6+zuJBT3DJfQ5oFKoe9K9y7j8LuAzgRiYdNfmh 5hzYKxAleR/W+F4qeYhKDx7HWinwO/whkxrbHVI84w6dN9Qxh8shf/x62wyy5g3zPsCa N1xq1GjBB50q7BwpUN8RchxaYfphycRls3aHGCMsN6VgFjWAV3CozP37FGuU4/UTU3DO kyeR1VNOoMj2Lsxg085moJky6ahF+z7OABVZtHX1No3Cx6kOPD8g2YcOCdTgXJ/JV+GT EhyqUJC8cET6tgiAFt3jBN2SCqRgCIBNp2WEeDqwpwcBUuhJcyKyymOgsL6y79be6J/l 3mXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965971; x=1696570771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Tx8IsOEvb8qkvUy2Or6MBahI0OwwMce9fHoVPFho48=; b=h1hnbSVrQK+OQ1brjiXNZrTRbNrKJQLsNDFgEl5ylcKpZzP0cvHSwWrnZnBV0pZ4KL gLo/KE/NkGGzCT9lxc94SsYkadXYATYH7wVHp1QuGMUu3ufIpzRfzOyBiWysDlmtWEEI QejFyfhQP6YF2s/CV+SUsA4s31KcNBnV6S+/Vk+mSEhymy2ZVCsyP8HMTUuGVcmIxzJ3 ZViXwGiZMkuTsH3C/zzHIREJyl2yF/RjTAlV2pdTTKoytKRumX0pUoiqHUCEfoS+UCDW udPdGLSuGmGC3BGaMkN0+WXK60neceHHxdOzLA7htYo2udJMHueAAsGQWm0RAPxmwy3x Tctw== X-Gm-Message-State: AOJu0YxGK2KHKSc2/uAZTz5lrZSlarXMCvMVXTYxEy+LZAAYkoPoYWyu 9RJVB+9R5eEXBLXPm6NGDikcTw== X-Google-Smtp-Source: AGHT+IFssgixc+IrMTS/V7svcvYp3mqrtz9kBpFjxlgOV+eCYx41PSPSVkMAV0EmJXCg9RRV7OOD1A== X-Received: by 2002:a17:906:845b:b0:9ae:695a:fed1 with SMTP id e27-20020a170906845b00b009ae695afed1mr2909592ejy.1.1695965971645; Thu, 28 Sep 2023 22:39:31 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:31 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 06/28] clk: renesas: rzg2l: remove critical area Date: Fri, 29 Sep 2023 08:38:53 +0300 Message-Id: <20230929053915.1530607-7-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea spinlock in rzg2l_mod_clock_endisable() is intended to protect the accesses to hardware register. There is no need to protect the instructions that set temporary variable which will be then written to register. With this only one write to one clock register is executed thus locking/unlocking rmw_lock is removed. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - removed also the spinlock - s/reduce/remove in patch title drivers/clk/renesas/rzg2l-cpg.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index f411e428196c..d936832e098f 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -895,7 +895,6 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) struct rzg2l_cpg_priv *priv = clock->priv; unsigned int reg = clock->off; struct device *dev = priv->dev; - unsigned long flags; u32 bitmask = BIT(clock->bit); u32 value; int error; @@ -907,14 +906,12 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk, enable ? "ON" : "OFF"); - spin_lock_irqsave(&priv->rmw_lock, flags); value = bitmask << 16; if (enable) value |= bitmask; - writel(value, priv->base + CLK_ON_R(reg)); - spin_unlock_irqrestore(&priv->rmw_lock, flags); + writel(value, priv->base + CLK_ON_R(reg)); if (!enable) return 0; From patchwork Fri Sep 29 05:38:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841078 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=Diq/e86J; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfLy6CCvz1yng for ; Fri, 29 Sep 2023 15:40:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232759AbjI2FkJ (ORCPT ); Fri, 29 Sep 2023 01:40:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232704AbjI2Fj7 (ORCPT ); Fri, 29 Sep 2023 01:39:59 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F42ACCE for ; Thu, 28 Sep 2023 22:39:35 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-99c1c66876aso1826614366b.2 for ; Thu, 28 Sep 2023 22:39:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965973; x=1696570773; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CWu2NOpEhtT7vu1ptq0dyyGepYPElryMWW3Aiedhw/Y=; b=Diq/e86JH4Zvnlnw+82UBFRVFDOYMU/OMRLgnWW5BSc/cpTismvmBxY9ArOHt6WIf+ iq8ISQi+LyPczOlmUTKbrK7janwPYVw03V8gF5VKuE3bsejbLoon0uODs+wymAKsZWK2 3pMHX6FdTt4Q+WgY+BL0I/RTsurE3u7Y9R2DqwJKXGAVqnik1JKIJZcmnhvbY47MRr0q PSxentyAU2vr/VT4/gMUjhAAkVsB5z6m6rNXFi4lws9JndEfLKMIdT4zKlUukDpJ8D/O Ay/3RRDU6r0WBJRHSQT5wB9P9GQ9XyGrKSEl65JHq70RP3khhPogTCvUpZvVQx8Nh+YG aXNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965973; x=1696570773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CWu2NOpEhtT7vu1ptq0dyyGepYPElryMWW3Aiedhw/Y=; b=OPrH4Pnsc1oOvjm43ZgMwhbcfywGNMwJNhbmXCekjznwKW7xndfYeqdrj29YT0WkTi +fOzdd9MmwigeWprJmzOrrGPr7AkGjnT4JlRHA5PjQe0ETahAX6ZVwgY7EDVK0CY+Jdb wjbnXkAkFeHn3N5BmW7aSMzs3VpJtui299/KpvRXuraki847GjKyqWyuWTiUiSse6em4 rzvOa34oPgXQ95sK+qDon42dorPzYhTDfQte/JfK8tUdjqX2I6/uegFL7QgYSMioXqOJ tNwraFFj0ysU/hJbr2diajeaJufMU5uzlh+wvxil36r64c0l2ybnE+EpfZVCsRIxcJN9 anhA== X-Gm-Message-State: AOJu0Yx3MjZQPRY1Qx2F9YfhjK4HZaJj7qAwVZYtdMdw3oDchMOSh1qB ePxEqOcpCZTh+dfmdqz0N6385w== X-Google-Smtp-Source: AGHT+IHvPByZHCHjh5YJx3lKgABwOn0+a6IQiB+LyPtqP4ZxODN8MzxnUaVLmNw09PCkAR97OX0rXQ== X-Received: by 2002:a17:906:301a:b0:9a5:d972:af50 with SMTP id 26-20020a170906301a00b009a5d972af50mr3353715ejz.19.1695965973544; Thu, 28 Sep 2023 22:39:33 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:33 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 07/28] clk: renesas: rzg2l: add support for RZ/G3S PLL Date: Fri, 29 Sep 2023 08:38:54 +0300 Message-Id: <20230929053915.1530607-8-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add support for reading the frequency of PLL1/4/6 available on RZ/G3S. The computation formula for PLL frequency is as follows: Fout = (nir + nfr / 4096) * Fin / (mr * pr) Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - added GENMASK() defines for DIV_P, DIV_M, DIV_NI, DIV_NF - used mul_u64_u32_shr() as suggested by Geert on v1 - s/CLK_TYPE_G3S_SAM_PLL/CLK_TYPE_G3S_PLL/g drivers/clk/renesas/rzg2l-cpg.c | 49 ++++++++++++++++++++++++++++++--- drivers/clk/renesas/rzg2l-cpg.h | 3 ++ 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index d936832e098f..02058a2d39ca 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -47,6 +47,11 @@ #define PDIV(val) FIELD_GET(GENMASK(5, 0), val) #define SDIV(val) FIELD_GET(GENMASK(2, 0), val) +#define RZG3S_DIV_P GENMASK(28, 26) +#define RZG3S_DIV_M GENMASK(25, 22) +#define RZG3S_DIV_NI GENMASK(21, 13) +#define RZG3S_DIV_NF GENMASK(12, 1) + #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) #define CLK_RST_R(reg) (reg) @@ -713,11 +718,43 @@ static const struct clk_ops rzg2l_cpg_pll_ops = { .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate, }; +static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk = to_pll(hw); + struct rzg2l_cpg_priv *priv = pll_clk->priv; + u32 nir, nfr, mr, pr, val; + u64 rate; + + if (pll_clk->type != CLK_TYPE_G3S_PLL) + return parent_rate; + + val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); + + pr = 1 << FIELD_GET(RZG3S_DIV_P, val); + /* Hardware interprets values higher than 8 as p = 16. */ + if (pr > 8) + pr = 16; + + mr = FIELD_GET(RZG3S_DIV_M, val) + 1; + nir = FIELD_GET(RZG3S_DIV_NI, val) + 1; + nfr = FIELD_GET(RZG3S_DIV_NF, val); + + rate = mul_u64_u32_shr(parent_rate, 4096 * nir + nfr, 12); + + return DIV_ROUND_CLOSEST_ULL(rate, (mr * pr)); +} + +static const struct clk_ops rzg3s_cpg_pll_ops = { + .recalc_rate = rzg3s_cpg_pll_clk_recalc_rate, +}; + static struct clk * __init rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, struct clk **clks, void __iomem *base, - struct rzg2l_cpg_priv *priv) + struct rzg2l_cpg_priv *priv, + const struct clk_ops *ops) { struct device *dev = priv->dev; const struct clk *parent; @@ -735,7 +772,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, parent_name = __clk_get_name(parent); init.name = core->name; - init.ops = &rzg2l_cpg_pll_ops; + init.ops = ops; init.flags = 0; init.parent_names = &parent_name; init.num_parents = 1; @@ -830,8 +867,12 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, core->mult, div); break; case CLK_TYPE_SAM_PLL: - clk = rzg2l_cpg_pll_clk_register(core, priv->clks, - priv->base, priv); + clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, + &rzg2l_cpg_pll_ops); + break; + case CLK_TYPE_G3S_PLL: + clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, + &rzg3s_cpg_pll_ops); break; case CLK_TYPE_SIPLL5: clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv); diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 097fd8f61680..20da0c620b90 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -102,6 +102,7 @@ enum clk_types { CLK_TYPE_IN, /* External Clock Input */ CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_SAM_PLL, + CLK_TYPE_G3S_PLL, /* Clock with divider */ CLK_TYPE_DIV, @@ -129,6 +130,8 @@ enum clk_types { DEF_TYPE(_name, _id, _type, .parent = _parent) #define DEF_SAMPLL(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) +#define DEF_G3S_PLL(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf) #define DEF_INPUT(_name, _id) \ DEF_TYPE(_name, _id, CLK_TYPE_IN) #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ From patchwork Fri Sep 29 05:38:55 2023 Content-Type: text/plain; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:35 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/28] clk: renesas: rzg2l: add struct clk_hw_data Date: Fri, 29 Sep 2023 08:38:55 +0300 Message-Id: <20230929053915.1530607-9-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add clk_hw_data struct that keeps the core part of a clock data. The sd_hw_data embeds a member of type struct clk_hw_data along with other members (in the next commits). This commit prepares the field for refactoring the SD MUX clock driver. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected tags drivers/clk/renesas/rzg2l-cpg.c | 52 +++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 02058a2d39ca..ac05463d1d98 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -63,13 +63,29 @@ #define MAX_VCLK_FREQ (148500000) -struct sd_hw_data { +/** + * struct clk_hw_data - clock hardware data + * @hw: clock hw + * @conf: clock configuration (register offset, shift, width) + * @priv: CPG private data structure + */ +struct clk_hw_data { struct clk_hw hw; u32 conf; struct rzg2l_cpg_priv *priv; }; -#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw) +#define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw) + +/** + * struct sd_hw_data - SD clock hardware data + * @hw_data: clock hw data + */ +struct sd_hw_data { + struct clk_hw_data hw_data; +}; + +#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw_data) struct rzg2l_pll5_param { u32 pl5_fracin; @@ -188,10 +204,10 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { - struct sd_hw_data *hwdata = to_sd_hw_data(hw); - struct rzg2l_cpg_priv *priv = hwdata->priv; - u32 off = GET_REG_OFFSET(hwdata->conf); - u32 shift = GET_SHIFT(hwdata->conf); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); const u32 clk_src_266 = 2; u32 msk, val, bitmask; unsigned long flags; @@ -208,7 +224,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and * the index to value mapping is done by adding 1 to the index. */ - bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; + bitmask = (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16; msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; spin_lock_irqsave(&priv->rmw_lock, flags); if (index != clk_src_266) { @@ -237,12 +253,12 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) { - struct sd_hw_data *hwdata = to_sd_hw_data(hw); - struct rzg2l_cpg_priv *priv = hwdata->priv; - u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf)); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); - val >>= GET_SHIFT(hwdata->conf); - val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); + val >>= GET_SHIFT(clk_hw_data->conf); + val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); return val ? val - 1 : 0; } @@ -258,17 +274,17 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, void __iomem *base, struct rzg2l_cpg_priv *priv) { - struct sd_hw_data *clk_hw_data; + struct sd_hw_data *sd_hw_data; struct clk_init_data init; struct clk_hw *clk_hw; int ret; - clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); - if (!clk_hw_data) + sd_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_hw_data), GFP_KERNEL); + if (!sd_hw_data) return ERR_PTR(-ENOMEM); - clk_hw_data->priv = priv; - clk_hw_data->conf = core->conf; + sd_hw_data->hw_data.priv = priv; + sd_hw_data->hw_data.conf = core->conf; init.name = core->name; init.ops = &rzg2l_cpg_sd_clk_mux_ops; @@ -276,7 +292,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, init.num_parents = core->num_parents; init.parent_names = core->parent_names; - clk_hw = &clk_hw_data->hw; + clk_hw = &sd_hw_data->hw_data.hw; clk_hw->init = &init; ret = devm_clk_hw_register(priv->dev, clk_hw); From patchwork Fri Sep 29 05:38:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:37 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 09/28] clk: renesas: rzg2l: remove CPG_SDHI_DSEL from generic header Date: Fri, 29 Sep 2023 08:38:56 +0300 Message-Id: <20230929053915.1530607-10-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Remove CPG_SDHI_DSEL and its bits from generic header as RZ/G3S has different offset register and bits for this, thus avoid mixing them. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - s/form/from in commit description - removed "G2UL_" prefix from macros' names - collected tags drivers/clk/renesas/r9a07g043-cpg.c | 7 +++++++ drivers/clk/renesas/r9a07g044-cpg.c | 7 +++++++ drivers/clk/renesas/rzg2l-cpg.h | 4 ---- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 1a7a6d60aca4..e0ae25644e1a 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -14,6 +14,13 @@ #include "rzg2l-cpg.h" +/* Specific registers. */ +#define CPG_PL2SDHI_DSEL (0x218) + +/* Clock select configuration. */ +#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) +#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index c597414a94d8..d4dcf5d896d4 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -15,6 +15,13 @@ #include "rzg2l-cpg.h" +/* Specific registers. */ +#define CPG_PL2SDHI_DSEL (0x218) + +/* Clock select configuration. */ +#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) +#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 20da0c620b90..f5382333d327 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -19,7 +19,6 @@ #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) #define CPG_PL6_DDIV (0x210) -#define CPG_PL2SDHI_DSEL (0x218) #define CPG_CLKSTATUS (0x280) #define CPG_PL3_SSEL (0x408) #define CPG_PL6_SSEL (0x414) @@ -69,9 +68,6 @@ #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) -#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) -#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) - #define EXTAL_FREQ_IN_MEGA_HZ (24) /** From patchwork Fri Sep 29 05:38:57 2023 Content-Type: text/plain; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:39 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 10/28] clk: renesas: rzg2l: refactor sd mux driver Date: Fri, 29 Sep 2023 08:38:57 +0300 Message-Id: <20230929053915.1530607-11-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Refactor SD MUX driver to be able to reuse the same code on RZ/G3S. RZ/G2{L, UL} has a limitation with regards to switching the clock source for SD MUX (MUX clock source has to be switched to 266MHz before switching b/w 533MHz and 400MHz). This limitation has been introduced as a clock notifier that is registered on platform based initialization data thus the SD MUX code could be reused on RZ/G3S. As both RZ/G2{L, UL} and RZ/G3S has specific bits in specific registers to check if the clock switching has been done, this configuration (register offset, register bits and bits width) is now passed though struct cpg_core_clk::sconf (status configuration) from platform specific initialization code. Along with struct cpg_core_clk::sconf the mux table indices are also passed from platform specific initialization code. Also, mux flags are now passed to DEF_SD_MUX() as they will be later used by RZ/G3S. Signed-off-by: Claudiu Beznea --- Changes in v2: - s/indexes/indices in commit description - mentioned in commit description that mux flags can now be passed to driver though DEF_SD_MUX() macro - removed SoC specific names from macros' names - added spaces after { and before } when initializing arrays - preserved the order of .[gs]set_parent() API definitions for simpler diff b/w versions - removed SD_MUX_NOTIF macro drivers/clk/renesas/r9a07g043-cpg.c | 12 ++- drivers/clk/renesas/r9a07g044-cpg.c | 12 ++- drivers/clk/renesas/rzg2l-cpg.c | 157 ++++++++++++++++++++-------- drivers/clk/renesas/rzg2l-cpg.h | 16 ++- 4 files changed, 143 insertions(+), 54 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index e0ae25644e1a..d831ac8eb4ce 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -21,6 +21,10 @@ #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) #define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) +/* Clock status configuration. */ +#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1) +#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, @@ -85,6 +89,8 @@ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; +static const u32 mtable_sdhi[] = { 1, 2, 3 }; + static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -130,8 +136,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi), - DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi), + DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_mux_clk_notifier), + DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_mux_clk_notifier), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index d4dcf5d896d4..a335f6eb1f80 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -22,6 +22,10 @@ #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) #define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) +/* Clock status configuration. */ +#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1) +#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, @@ -105,6 +109,8 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; +static const u32 mtable_sdhi[] = { 1, 2, 3 }; + static const struct { struct cpg_core_clk common[56]; #ifdef CONFIG_CLK_R9A07G054 @@ -170,8 +176,10 @@ static const struct { DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi), - DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi), + DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_mux_clk_notifier), + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_mux_clk_notifier), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8), diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index ac05463d1d98..f4b70e07b9c6 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -67,25 +67,29 @@ * struct clk_hw_data - clock hardware data * @hw: clock hw * @conf: clock configuration (register offset, shift, width) + * @sconf: clock status configuration (register offset, shift, width) * @priv: CPG private data structure */ struct clk_hw_data { struct clk_hw hw; u32 conf; + u32 sconf; struct rzg2l_cpg_priv *priv; }; #define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw) /** - * struct sd_hw_data - SD clock hardware data + * struct sd_mux_hw_data - SD MUX clock hardware data * @hw_data: clock hw data + * @mtable: clock mux table */ -struct sd_hw_data { +struct sd_mux_hw_data { struct clk_hw_data hw_data; + const u32 *mtable; }; -#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw_data) +#define to_sd_mux_hw_data(_hw) container_of(_hw, struct sd_mux_hw_data, hw_data) struct rzg2l_pll5_param { u32 pl5_fracin; @@ -142,6 +146,77 @@ static void rzg2l_cpg_del_clk_provider(void *data) of_clk_del_provider(data); } +/* Must be called in atomic context. */ +static int rzg2l_cpg_wait_clk_update_done(void __iomem *base, u32 conf) +{ + u32 bitmask = GENMASK(GET_WIDTH(conf) - 1, 0) << GET_SHIFT(conf); + u32 off = GET_REG_OFFSET(conf); + u32 val; + + return readl_poll_timeout_atomic(base + off, val, !(val & bitmask), 10, 200); +} + +int rzg2l_cpg_sd_mux_clk_notifier(struct notifier_block *nb, unsigned long event, + void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(cnd->clk); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); + const u32 clk_src_266 = 3; + unsigned long flags; + u32 bitmask; + int ret; + + if (event != PRE_RATE_CHANGE || (cnd->new_rate / MEGA == 266)) + return 0; + + spin_lock_irqsave(&priv->rmw_lock, flags); + + /* + * As per the HW manual, we should not directly switch from 533 MHz to + * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) + * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, + * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 + * (400 MHz)). + * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock + * switching register is prohibited. + * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and + * the index to value mapping is done by adding 1 to the index. + */ + bitmask = (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16; + writel(bitmask | (clk_src_266 << shift), priv->base + off); + + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); + + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + if (ret) + dev_err(priv->dev, "failed to switch to safe clk source\n"); + + return ret; +} + +static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk *core, + struct rzg2l_cpg_priv *priv) +{ + struct notifier_block *nb; + + if (!core->notifier) + return 0; + + nb = devm_kzalloc(priv->dev, sizeof(*nb), GFP_KERNEL); + if (!nb) + return -ENOMEM; + + nb->notifier_call = core->notifier; + + return clk_notifier_register(hw->clk, nb); +} + static struct clk * __init rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, @@ -202,71 +277,54 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, return clk_hw->clk; } -static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) +static int rzg2l_cpg_sd_mux_clk_set_parent(struct clk_hw *hw, u8 index) { struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data); struct rzg2l_cpg_priv *priv = clk_hw_data->priv; u32 off = GET_REG_OFFSET(clk_hw_data->conf); u32 shift = GET_SHIFT(clk_hw_data->conf); - const u32 clk_src_266 = 2; - u32 msk, val, bitmask; unsigned long flags; + u32 bitmask, val; int ret; - /* - * As per the HW manual, we should not directly switch from 533 MHz to - * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) - * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, - * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 - * (400 MHz)). - * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock - * switching register is prohibited. - * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and - * the index to value mapping is done by adding 1 to the index. - */ + val = clk_mux_index_to_val(sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, index); + bitmask = (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16; - msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; + spin_lock_irqsave(&priv->rmw_lock, flags); - if (index != clk_src_266) { - writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off); - - ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 10, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); - if (ret) - goto unlock; - } - writel(bitmask | ((index + 1) << shift), priv->base + off); + writel(bitmask | (val << shift), priv->base + off); + + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); - ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 10, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); -unlock: spin_unlock_irqrestore(&priv->rmw_lock, flags); if (ret) - dev_err(priv->dev, "failed to switch clk source\n"); + dev_err(priv->dev, "Failed to switch parent\n"); return ret; } -static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) +static u8 rzg2l_cpg_sd_mux_clk_get_parent(struct clk_hw *hw) { struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data); struct rzg2l_cpg_priv *priv = clk_hw_data->priv; - u32 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); + u32 val; + val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); val >>= GET_SHIFT(clk_hw_data->conf); val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); - return val ? val - 1 : 0; + return clk_mux_val_to_index(hw, sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, val); } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { .determine_rate = __clk_mux_determine_rate_closest, - .set_parent = rzg2l_cpg_sd_clk_mux_set_parent, - .get_parent = rzg2l_cpg_sd_clk_mux_get_parent, + .set_parent = rzg2l_cpg_sd_mux_clk_set_parent, + .get_parent = rzg2l_cpg_sd_mux_clk_get_parent, }; static struct clk * __init @@ -274,31 +332,40 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, void __iomem *base, struct rzg2l_cpg_priv *priv) { - struct sd_hw_data *sd_hw_data; + struct sd_mux_hw_data *sd_mux_hw_data; struct clk_init_data init; struct clk_hw *clk_hw; int ret; - sd_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_hw_data), GFP_KERNEL); - if (!sd_hw_data) + sd_mux_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_mux_hw_data), GFP_KERNEL); + if (!sd_mux_hw_data) return ERR_PTR(-ENOMEM); - sd_hw_data->hw_data.priv = priv; - sd_hw_data->hw_data.conf = core->conf; + sd_mux_hw_data->hw_data.priv = priv; + sd_mux_hw_data->hw_data.conf = core->conf; + sd_mux_hw_data->hw_data.sconf = core->sconf; + sd_mux_hw_data->mtable = core->mtable; init.name = core->name; init.ops = &rzg2l_cpg_sd_clk_mux_ops; - init.flags = 0; + init.flags = core->flag; init.num_parents = core->num_parents; init.parent_names = core->parent_names; - clk_hw = &sd_hw_data->hw_data.hw; + clk_hw = &sd_mux_hw_data->hw_data.hw; clk_hw->init = &init; ret = devm_clk_hw_register(priv->dev, clk_hw); if (ret) return ERR_PTR(ret); + ret = rzg2l_register_notifier(clk_hw, core, priv); + if (ret) { + dev_err(priv->dev, "Failed to register notifier for %s\n", + core->name); + return ERR_PTR(ret); + } + return clk_hw->clk; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index f5382333d327..edac34037cf0 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -9,6 +9,8 @@ #ifndef __RENESAS_RZG2L_CPG_H__ #define __RENESAS_RZG2L_CPG_H__ +#include + #define CPG_SIPLL5_STBY (0x140) #define CPG_SIPLL5_CLK1 (0x144) #define CPG_SIPLL5_CLK3 (0x14C) @@ -42,8 +44,6 @@ #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) -#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 200 - /* n = 0/1/2 for PLL1/4/6 */ #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) @@ -86,8 +86,11 @@ struct cpg_core_clk { unsigned int mult; unsigned int type; unsigned int conf; + unsigned int sconf; const struct clk_div_table *dtable; + const u32 *mtable; const char * const *parent_names; + notifier_fn_t notifier; u32 flag; u32 mux_flags; int num_parents; @@ -150,10 +153,11 @@ enum clk_types { .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ .mux_flags = CLK_MUX_READ_ONLY) -#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \ - DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ +#define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \ + DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \ .parent_names = _parent_names, \ - .num_parents = ARRAY_SIZE(_parent_names)) + .num_parents = ARRAY_SIZE(_parent_names), \ + .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier) #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ @@ -272,4 +276,6 @@ extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; +int rzg2l_cpg_sd_mux_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); + #endif From patchwork Fri Sep 29 05:38:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=Z7cMXwuI; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfMg6d7cz1yng for ; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:41 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 11/28] clk: renesas: rzg2l: add a divider clock for RZ/G3S Date: Fri, 29 Sep 2023 08:38:58 +0300 Message-Id: <20230929053915.1530607-12-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add a divider clock driver for RZ/G3S. This will be used in RZ/G3S by SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, P3 core clocks. The divider has some limitation for SDHI and OCTA clocks: - SD div cannot be 1 if parent rate is 800MHz - OCTA div cannot be 1 if parent rate is 400MHz For these clocks a notifier could be registered from platform specific clock driver and proper actions are taken before clock rate is changed, if needed. Signed-off-by: Claudiu Beznea --- Changes in v2: - removed DIV_NOTIF macro drivers/clk/renesas/rzg2l-cpg.c | 207 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 9 ++ 2 files changed, 216 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index f4b70e07b9c6..3080e9391f71 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -91,6 +91,22 @@ struct sd_mux_hw_data { #define to_sd_mux_hw_data(_hw) container_of(_hw, struct sd_mux_hw_data, hw_data) +/** + * struct div_hw_data - divider clock hardware data + * @hw_data: clock hw data + * @dtable: pointer to divider table + * @invalid_rate: invalid rate for divider + * @width: divider width + */ +struct div_hw_data { + struct clk_hw_data hw_data; + const struct clk_div_table *dtable; + unsigned long invalid_rate; + u32 width; +}; + +#define to_div_hw_data(_hw) container_of(_hw, struct div_hw_data, hw_data) + struct rzg2l_pll5_param { u32 pl5_fracin; u8 pl5_refdiv; @@ -200,6 +216,54 @@ int rzg2l_cpg_sd_mux_clk_notifier(struct notifier_block *nb, unsigned long event return ret; } +int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, + void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(cnd->clk); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); + u32 bitmask = GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); + unsigned long flags; + int ret = 0; + u32 val; + + if (event != PRE_RATE_CHANGE || !div_hw_data->invalid_rate || + div_hw_data->invalid_rate % cnd->new_rate) + return 0; + + spin_lock_irqsave(&priv->rmw_lock, flags); + + val = readl(priv->base + off); + val >>= shift; + val &= bitmask; + + /* + * There are different constraints for the user of this notifiers as follows: + * 1/ SD div cannot be 1 (val == 0) if parent rate is 800MHz + * 2/ OCTA div cannot be 1 (val == 0) if parent rate is 400MHz + * As SD can have only one parent having 800MHz and OCTA div can have + * only one parent having 400MHz we took into account the parent rate + * at the beginning of function (by checking invalid_rate % new_rate). + * Now it is time to check the hardware divider and update it accordingly. + */ + if (!val) { + writel(((bitmask << shift) << 16) | BIT(shift), priv->base + off); + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); + } + + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + if (ret) + dev_err(priv->dev, "Failed to downgrade the div\n"); + + return ret; +} + static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk *core, struct rzg2l_cpg_priv *priv) { @@ -217,6 +281,146 @@ static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk return clk_notifier_register(hw->clk, nb); } +static unsigned long rzg3s_div_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 val; + + val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); + val >>= GET_SHIFT(clk_hw_data->conf); + val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); + + return divider_recalc_rate(hw, parent_rate, val, div_hw_data->dtable, + CLK_DIVIDER_ROUND_CLOSEST, div_hw_data->width); +} + +static bool rzg3s_div_clk_is_rate_valid(const unsigned long invalid_rate, unsigned long rate) +{ + if (invalid_rate && rate >= invalid_rate) + return false; + + return true; +} + +static long rzg3s_div_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + long round_rate; + + round_rate = divider_round_rate(hw, rate, parent_rate, div_hw_data->dtable, + div_hw_data->width, CLK_DIVIDER_ROUND_CLOSEST); + + if (!rzg3s_div_clk_is_rate_valid(div_hw_data->invalid_rate, round_rate)) + return -EINVAL; + + return round_rate; +} + +static int rzg3s_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); + unsigned long flags; + u32 bitmask, val; + int ret; + + /* + * Some dividers cannot support some rates: + * - SD div cannot support 800 MHz when parent is @800MHz and div = 1 + * - OCTA div cannot support 400 MHz when parent is @400MHz and div = 1 + * Check these scenarios. + */ + if (!rzg3s_div_clk_is_rate_valid(div_hw_data->invalid_rate, rate)) + return -EINVAL; + + val = divider_get_val(rate, parent_rate, div_hw_data->dtable, div_hw_data->width, + CLK_DIVIDER_ROUND_CLOSEST); + + bitmask = (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16; + + spin_lock_irqsave(&priv->rmw_lock, flags); + writel(bitmask | (val << shift), priv->base + off); + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + return ret; +} + +static const struct clk_ops rzg3s_div_clk_ops = { + .recalc_rate = rzg3s_div_clk_recalc_rate, + .round_rate = rzg3s_div_clk_round_rate, + .set_rate = rzg3s_div_clk_set_rate, +}; + +static struct clk * __init +rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, + void __iomem *base, struct rzg2l_cpg_priv *priv) +{ + struct div_hw_data *div_hw_data; + struct clk_init_data init = {}; + const struct clk_div_table *clkt; + struct clk_hw *clk_hw; + const struct clk *parent; + const char *parent_name; + u32 max; + int ret; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name = __clk_get_name(parent); + + div_hw_data = devm_kzalloc(priv->dev, sizeof(*div_hw_data), GFP_KERNEL); + if (!div_hw_data) + return ERR_PTR(-ENOMEM); + + init.name = core->name; + init.flags = core->flag; + init.ops = &rzg3s_div_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + /* Get the maximum divider to retrieve div width. */ + for (clkt = core->dtable; clkt->div; clkt++) { + if (max < clkt->div) + max = clkt->div; + } + + div_hw_data->hw_data.priv = priv; + div_hw_data->hw_data.conf = core->conf; + div_hw_data->hw_data.sconf = core->sconf; + div_hw_data->dtable = core->dtable; + div_hw_data->invalid_rate = core->invalid_rate; + div_hw_data->width = fls(max) - 1; + + clk_hw = &div_hw_data->hw_data.hw; + clk_hw->init = &init; + + ret = devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + ret = rzg2l_register_notifier(clk_hw, core, priv); + if (ret) { + dev_err(priv->dev, "Failed to register notifier for %s\n", + core->name); + return ERR_PTR(ret); + } + + return clk_hw->clk; +} + static struct clk * __init rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, @@ -964,6 +1168,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, clk = rzg2l_cpg_div_clk_register(core, priv->clks, priv->base, priv); break; + case CLK_TYPE_G3S_DIV: + clk = rzg3s_cpg_div_clk_register(core, priv->clks, priv->base, priv); + break; case CLK_TYPE_MUX: clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv); break; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index edac34037cf0..8312972cc496 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -89,6 +89,7 @@ struct cpg_core_clk { unsigned int sconf; const struct clk_div_table *dtable; const u32 *mtable; + const unsigned long invalid_rate; const char * const *parent_names; notifier_fn_t notifier; u32 flag; @@ -105,6 +106,7 @@ enum clk_types { /* Clock with divider */ CLK_TYPE_DIV, + CLK_TYPE_G3S_DIV, /* Clock with clock source selector */ CLK_TYPE_MUX, @@ -143,6 +145,12 @@ enum clk_types { DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, \ .flag = CLK_DIVIDER_READ_ONLY) +#define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ + _clk_flags, _notif) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \ + .parent = _parent, .dtable = _dtable, \ + .invalid_rate = _invalid_rate, .flag = (_clk_flags), \ + .notifier = _notif) #define DEF_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ .parent_names = _parent_names, \ @@ -277,5 +285,6 @@ extern const struct rzg2l_cpg_info r9a07g054_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; int rzg2l_cpg_sd_mux_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); +int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); #endif From patchwork Fri Sep 29 05:38:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=VXJTvgxO; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfN31kDvz1yng for ; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 12/28] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC Date: Fri, 29 Sep 2023 08:38:59 +0300 Message-Id: <20230929053915.1530607-13-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add documentation for RZ/G3S CPG. RZ/G3S CPG module is almost identical with the one available in RZ/G2{L, UL} the exception being some core clocks as follows: - SD clock is composed by a mux and a divider and the divider has some limitation (div = 1 cannot be set if mux rate is 800MHz). - there are 3 SD clocks - OCTA and TSU clocks are specific to RZ/G3S - PLL1/4/6 are specific to RZ/G3S with its own computation formula Even with this RZ/G3S could use the same bindings as RZ/G2L. Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module clocks and resets were added. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected Rob's tag - squashed with [PATCH 21/37] dt-bindings: clock: add r9a08g045 CPG clocks and resets from v1 - updated commit message to reflect that bindings were also added to this patch - removed R9A08G045_USB_SCLK - @Geert: please note I haven't collected your Rb tag as I did the squash .../bindings/clock/renesas,rzg2l-cpg.yaml | 1 + include/dt-bindings/clock/r9a08g045-cpg.h | 242 ++++++++++++++++++ 2 files changed, 243 insertions(+) create mode 100644 include/dt-bindings/clock/r9a08g045-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index fe2fba18ae84..80a8c7114c31 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -27,6 +27,7 @@ properties: - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a08g045-cpg # RZ/G3S - renesas,r9a09g011-cpg # RZ/V2M reg: diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h new file mode 100644 index 000000000000..410725b778a8 --- /dev/null +++ b/include/dt-bindings/clock/r9a08g045-cpg.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ + +#include + +/* R9A08G045 CPG Core Clocks */ +#define R9A08G045_CLK_I 0 +#define R9A08G045_CLK_I2 1 +#define R9A08G045_CLK_I3 2 +#define R9A08G045_CLK_S0 3 +#define R9A08G045_CLK_SPI0 4 +#define R9A08G045_CLK_SPI1 5 +#define R9A08G045_CLK_SD0 6 +#define R9A08G045_CLK_SD1 7 +#define R9A08G045_CLK_SD2 8 +#define R9A08G045_CLK_M0 9 +#define R9A08G045_CLK_HP 10 +#define R9A08G045_CLK_TSU 11 +#define R9A08G045_CLK_ZT 12 +#define R9A08G045_CLK_P0 13 +#define R9A08G045_CLK_P1 14 +#define R9A08G045_CLK_P2 15 +#define R9A08G045_CLK_P3 16 +#define R9A08G045_CLK_P4 17 +#define R9A08G045_CLK_P5 18 +#define R9A08G045_CLK_AT 19 +#define R9A08G045_CLK_OC0 20 +#define R9A08G045_CLK_OC1 21 +#define R9A08G045_OSCCLK 22 +#define R9A08G045_OSCCLK2 23 +#define R9A08G045_SWD 24 + +/* R9A08G045 Module Clocks */ +#define R9A08G045_OCTA_ACLK 0 +#define R9A08G045_OCTA_MCLK 1 +#define R9A08G045_CA55_SCLK 2 +#define R9A08G045_CA55_PCLK 3 +#define R9A08G045_CA55_ATCLK 4 +#define R9A08G045_CA55_GICCLK 5 +#define R9A08G045_CA55_PERICLK 6 +#define R9A08G045_CA55_ACLK 7 +#define R9A08G045_CA55_TSCLK 8 +#define R9A08G045_SRAM_ACPU_ACLK0 9 +#define R9A08G045_SRAM_ACPU_ACLK1 10 +#define R9A08G045_SRAM_ACPU_ACLK2 11 +#define R9A08G045_GIC600_GICCLK 12 +#define R9A08G045_IA55_CLK 13 +#define R9A08G045_IA55_PCLK 14 +#define R9A08G045_MHU_PCLK 15 +#define R9A08G045_SYC_CNT_CLK 16 +#define R9A08G045_DMAC_ACLK 17 +#define R9A08G045_DMAC_PCLK 18 +#define R9A08G045_OSTM0_PCLK 19 +#define R9A08G045_OSTM1_PCLK 20 +#define R9A08G045_OSTM2_PCLK 21 +#define R9A08G045_OSTM3_PCLK 22 +#define R9A08G045_OSTM4_PCLK 23 +#define R9A08G045_OSTM5_PCLK 24 +#define R9A08G045_OSTM6_PCLK 25 +#define R9A08G045_OSTM7_PCLK 26 +#define R9A08G045_MTU_X_MCK_MTU3 27 +#define R9A08G045_POE3_CLKM_POE 28 +#define R9A08G045_GPT_PCLK 29 +#define R9A08G045_POEG_A_CLKP 30 +#define R9A08G045_POEG_B_CLKP 31 +#define R9A08G045_POEG_C_CLKP 32 +#define R9A08G045_POEG_D_CLKP 33 +#define R9A08G045_WDT0_PCLK 34 +#define R9A08G045_WDT0_CLK 35 +#define R9A08G045_WDT1_PCLK 36 +#define R9A08G045_WDT1_CLK 37 +#define R9A08G045_WDT2_PCLK 38 +#define R9A08G045_WDT2_CLK 39 +#define R9A08G045_SPI_HCLK 40 +#define R9A08G045_SPI_ACLK 41 +#define R9A08G045_SPI_CLK 42 +#define R9A08G045_SPI_CLKX2 43 +#define R9A08G045_SDHI0_IMCLK 44 +#define R9A08G045_SDHI0_IMCLK2 45 +#define R9A08G045_SDHI0_CLK_HS 46 +#define R9A08G045_SDHI0_ACLK 47 +#define R9A08G045_SDHI1_IMCLK 48 +#define R9A08G045_SDHI1_IMCLK2 49 +#define R9A08G045_SDHI1_CLK_HS 50 +#define R9A08G045_SDHI1_ACLK 51 +#define R9A08G045_SDHI2_IMCLK 52 +#define R9A08G045_SDHI2_IMCLK2 53 +#define R9A08G045_SDHI2_CLK_HS 54 +#define R9A08G045_SDHI2_ACLK 55 +#define R9A08G045_SSI0_PCLK2 56 +#define R9A08G045_SSI0_PCLK_SFR 57 +#define R9A08G045_SSI1_PCLK2 58 +#define R9A08G045_SSI1_PCLK_SFR 59 +#define R9A08G045_SSI2_PCLK2 60 +#define R9A08G045_SSI2_PCLK_SFR 61 +#define R9A08G045_SSI3_PCLK2 62 +#define R9A08G045_SSI3_PCLK_SFR 63 +#define R9A08G045_SRC_CLKP 64 +#define R9A08G045_USB_U2H0_HCLK 65 +#define R9A08G045_USB_U2H1_HCLK 66 +#define R9A08G045_USB_U2P_EXR_CPUCLK 67 +#define R9A08G045_USB_PCLK 68 +#define R9A08G045_ETH0_CLK_AXI 69 +#define R9A08G045_ETH0_CLK_CHI 70 +#define R9A08G045_ETH0_REFCLK 71 +#define R9A08G045_ETH1_CLK_AXI 72 +#define R9A08G045_ETH1_CLK_CHI 73 +#define R9A08G045_ETH1_REFCLK 74 +#define R9A08G045_I2C0_PCLK 75 +#define R9A08G045_I2C1_PCLK 76 +#define R9A08G045_I2C2_PCLK 77 +#define R9A08G045_I2C3_PCLK 78 +#define R9A08G045_SCIF0_CLK_PCK 79 +#define R9A08G045_SCIF1_CLK_PCK 80 +#define R9A08G045_SCIF2_CLK_PCK 81 +#define R9A08G045_SCIF3_CLK_PCK 82 +#define R9A08G045_SCIF4_CLK_PCK 83 +#define R9A08G045_SCIF5_CLK_PCK 84 +#define R9A08G045_SCI0_CLKP 85 +#define R9A08G045_SCI1_CLKP 86 +#define R9A08G045_IRDA_CLKP 87 +#define R9A08G045_RSPI0_CLKB 88 +#define R9A08G045_RSPI1_CLKB 89 +#define R9A08G045_RSPI2_CLKB 90 +#define R9A08G045_RSPI3_CLKB 91 +#define R9A08G045_RSPI4_CLKB 92 +#define R9A08G045_CANFD_PCLK 93 +#define R9A08G045_CANFD_CLK_RAM 94 +#define R9A08G045_GPIO_HCLK 95 +#define R9A08G045_ADC_ADCLK 96 +#define R9A08G045_ADC_PCLK 97 +#define R9A08G045_TSU_PCLK 98 +#define R9A08G045_PDM_PCLK 99 +#define R9A08G045_PDM_CCLK 100 +#define R9A08G045_PCI_ACLK 101 +#define R9A08G045_PCI_CLKL1PM 102 +#define R9A08G045_SPDIF_PCLK 103 +#define R9A08G045_I3C_PCLK 104 +#define R9A08G045_I3C_TCLK 105 +#define R9A08G045_VBAT_BCLK 106 + +/* R9A08G045 Resets */ +#define R9A08G045_CA55_RST_1_0 0 +#define R9A08G045_CA55_RST_3_0 1 +#define R9A08G045_CA55_RST_4 2 +#define R9A08G045_CA55_RST_5 3 +#define R9A08G045_CA55_RST_6 4 +#define R9A08G045_CA55_RST_7 5 +#define R9A08G045_CA55_RST_8 6 +#define R9A08G045_CA55_RST_9 7 +#define R9A08G045_CA55_RST_10 8 +#define R9A08G045_CA55_RST_11 9 +#define R9A08G045_CA55_RST_12 10 +#define R9A08G045_SRAM_ACPU_ARESETN0 11 +#define R9A08G045_SRAM_ACPU_ARESETN1 12 +#define R9A08G045_SRAM_ACPU_ARESETN2 13 +#define R9A08G045_GIC600_GICRESET_N 14 +#define R9A08G045_GIC600_DBG_GICRESET_N 15 +#define R9A08G045_IA55_RESETN 16 +#define R9A08G045_MHU_RESETN 17 +#define R9A08G045_DMAC_ARESETN 18 +#define R9A08G045_DMAC_RST_ASYNC 19 +#define R9A08G045_SYC_RESETN 20 +#define R9A08G045_OSTM0_PRESETZ 21 +#define R9A08G045_OSTM1_PRESETZ 22 +#define R9A08G045_OSTM2_PRESETZ 23 +#define R9A08G045_OSTM3_PRESETZ 24 +#define R9A08G045_OSTM4_PRESETZ 25 +#define R9A08G045_OSTM5_PRESETZ 26 +#define R9A08G045_OSTM6_PRESETZ 27 +#define R9A08G045_OSTM7_PRESETZ 28 +#define R9A08G045_MTU_X_PRESET_MTU3 29 +#define R9A08G045_POE3_RST_M_REG 30 +#define R9A08G045_GPT_RST_C 31 +#define R9A08G045_POEG_A_RST 32 +#define R9A08G045_POEG_B_RST 33 +#define R9A08G045_POEG_C_RST 34 +#define R9A08G045_POEG_D_RST 35 +#define R9A08G045_WDT0_PRESETN 36 +#define R9A08G045_WDT1_PRESETN 37 +#define R9A08G045_WDT2_PRESETN 38 +#define R9A08G045_SPI_HRESETN 39 +#define R9A08G045_SPI_ARESETN 40 +#define R9A08G045_SDHI0_IXRST 41 +#define R9A08G045_SDHI1_IXRST 42 +#define R9A08G045_SDHI2_IXRST 43 +#define R9A08G045_SSI0_RST_M2_REG 44 +#define R9A08G045_SSI1_RST_M2_REG 45 +#define R9A08G045_SSI2_RST_M2_REG 46 +#define R9A08G045_SSI3_RST_M2_REG 47 +#define R9A08G045_SRC_RST 48 +#define R9A08G045_USB_U2H0_HRESETN 49 +#define R9A08G045_USB_U2H1_HRESETN 50 +#define R9A08G045_USB_U2P_EXL_SYSRST 51 +#define R9A08G045_USB_PRESETN 52 +#define R9A08G045_ETH0_RST_HW_N 53 +#define R9A08G045_ETH1_RST_HW_N 54 +#define R9A08G045_I2C0_MRST 55 +#define R9A08G045_I2C1_MRST 56 +#define R9A08G045_I2C2_MRST 57 +#define R9A08G045_I2C3_MRST 58 +#define R9A08G045_SCIF0_RST_SYSTEM_N 59 +#define R9A08G045_SCIF1_RST_SYSTEM_N 60 +#define R9A08G045_SCIF2_RST_SYSTEM_N 61 +#define R9A08G045_SCIF3_RST_SYSTEM_N 62 +#define R9A08G045_SCIF4_RST_SYSTEM_N 63 +#define R9A08G045_SCIF5_RST_SYSTEM_N 64 +#define R9A08G045_SCI0_RST 65 +#define R9A08G045_SCI1_RST 66 +#define R9A08G045_IRDA_RST 67 +#define R9A08G045_RSPI0_RST 68 +#define R9A08G045_RSPI1_RST 69 +#define R9A08G045_RSPI2_RST 70 +#define R9A08G045_RSPI3_RST 71 +#define R9A08G045_RSPI4_RST 72 +#define R9A08G045_CANFD_RSTP_N 73 +#define R9A08G045_CANFD_RSTC_N 74 +#define R9A08G045_GPIO_RSTN 75 +#define R9A08G045_GPIO_PORT_RESETN 76 +#define R9A08G045_GPIO_SPARE_RESETN 77 +#define R9A08G045_ADC_PRESETN 78 +#define R9A08G045_ADC_ADRST_N 79 +#define R9A08G045_TSU_PRESETN 80 +#define R9A08G045_OCTA_ARESETN 81 +#define R9A08G045_PDM0_PRESETNT 82 +#define R9A08G045_PCI_ARESETN 83 +#define R9A08G045_PCI_RST_B 84 +#define R9A08G045_PCI_RST_GP_B 85 +#define R9A08G045_PCI_RST_PS_B 86 +#define R9A08G045_PCI_RST_RSM_B 87 +#define R9A08G045_PCI_RST_CFG_B 88 +#define R9A08G045_PCI_RST_LOAD_B 89 +#define R9A08G045_SPDIF_RST 90 +#define R9A08G045_I3C_TRESETN 91 +#define R9A08G045_I3C_PRESETN 92 +#define R9A08G045_VBAT_BRESETN 93 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ From patchwork Fri Sep 29 05:39:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=lwL8cviL; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 13/28] clk: renesas: add minimal boot support for RZ/G3S SoC Date: Fri, 29 Sep 2023 08:39:00 +0300 Message-Id: <20230929053915.1530607-14-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add minimal clock and reset support for RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, SD0 mod clocks and resets. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - used RZ/G3S specific definition for CPG_CLKDIVSTATUS register - removed CLK_PLL3_DIV2_2, CLK_SD0_DIV, CLK_S0_DIV2 - added space after { and before } in array initializations - s/indexes/indices/g - s/.osc/OSC and moved it in core output clocks section - s/.osc2/OSC2 and moved it in core output clock section - s/SD0_DIV4/.sd0_div4 drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a08g045-cpg.c | 213 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 6 + drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 227 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a08g045-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 37632a0659d8..69396e197959 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -37,6 +37,7 @@ config CLK_RENESAS select CLK_R9A07G043 if ARCH_R9A07G043 select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_R9A07G054 if ARCH_R9A07G054 + select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_SH73A0 if ARCH_SH73A0 @@ -179,6 +180,10 @@ config CLK_R9A07G054 bool "RZ/V2L clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A08G045 + bool "RZ/G3S clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L @@ -215,7 +220,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector config CLK_RZG2L - bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST + bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER # Generic diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index de907623fe3f..879a07d445f9 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o +obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c new file mode 100644 index 000000000000..6e4ac0860694 --- /dev/null +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S CPG driver + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzg2l-cpg.h" + +/* RZ/G3S Specific registers. */ +#define G3S_CPG_PL2_DDIV (0x204) +#define G3S_CPG_SDHI_DDIV (0x218) +#define G3S_CPG_PLL_DSEL (0x240) +#define G3S_CPG_SDHI_DSEL (0x244) +#define G3S_CLKDIVSTATUS (0x280) +#define G3S_CLKSELSTATUS (0x284) + +/* RZ/G3S Specific division configuration. */ +#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3) +#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1) + +/* RZ/G3S Clock status configuration. */ +#define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1) +#define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1) +#define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1) +#define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1) +#define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1) +#define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1) + +#define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1) +#define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1) + +/* RZ/G3S Specific clocks select. */ +#define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1) +#define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2) + +/* PLL 1/4/6 configuration registers macro. */ +#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) + +#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \ + .parent_names = (_parent_names), \ + .num_parents = ARRAY_SIZE((_parent_names)), \ + .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \ + .flag = (_clk_flags)) + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A08G045_SWD, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_OSC_DIV1000, + CLK_PLL1, + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL2_DIV2_8, + CLK_PLL2_DIV6, + CLK_PLL3, + CLK_PLL3_DIV2, + CLK_PLL3_DIV2_4, + CLK_PLL3_DIV2_8, + CLK_PLL3_DIV6, + CLK_PLL4, + CLK_PLL6, + CLK_PLL6_DIV2, + CLK_SEL_SDHI0, + CLK_SEL_PLL4, + CLK_P1_DIV2, + CLK_P3_DIV2, + CLK_SD0_DIV4, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_1_2[] = { + { 0, 1 }, + { 1, 2 }, + { 0, 0 }, +}; + +static const struct clk_div_table dtable_1_8[] = { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 0, 0 }, +}; + +static const struct clk_div_table dtable_1_32[] = { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 32 }, + { 0, 0 }, +}; + +/* Mux clock names tables. */ +static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" }; +static const char * const sel_pll4[] = { ".osc_div1000", ".pll4" }; + +/* Mux clock indices tables. */ +static const u32 mtable_sd[] = { 0, 2, 3 }; +static const u32 mtable_pll4[] = { 0, 1 }; + +static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3), + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), + DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), + DEF_FIXED(".pll3_div2_8", CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8), + DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6), + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), + DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi, + mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4, + mtable_pll4, CLK_SET_PARENT_GATE, NULL), + + /* Core output clk */ + DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8, + 0, 0, NULL), + DEF_G3S_DIV("P0", R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS, + dtable_1_32, 0, 0, NULL), + DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS, + dtable_1_2, 800000000UL, CLK_SET_RATE_PARENT, rzg3s_cpg_div_clk_notifier), + DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4), + DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), + DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS, + dtable_1_32, 0, 0, NULL), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2), + DEF_G3S_DIV("P2", R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS, + dtable_1_32, 0, 0, NULL), + DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS, + dtable_1_32, 0, 0, NULL), + DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), + DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), + DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), +}; + +static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { + DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), + DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), + DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), + DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), + DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), + DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), + DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3), + DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), + DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), +}; + +static const struct rzg2l_reset r9a08g045_resets[] = { + DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), + DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), + DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), +}; + +static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { + MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G045_IA55_CLK, + MOD_CLK_BASE + R9A08G045_DMAC_ACLK, +}; + +const struct rzg2l_cpg_info r9a08g045_cpg_info = { + /* Core Clocks */ + .core_clks = r9a08g045_core_clks, + .num_core_clks = ARRAY_SIZE(r9a08g045_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a08g045_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = r9a08g045_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks), + .num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1, + + /* Resets */ + .resets = r9a08g045_resets, + .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3080e9391f71..bf49b40a3b63 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1728,6 +1728,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { .data = &r9a07g054_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A08G045 + { + .compatible = "renesas,r9a08g045-cpg", + .data = &r9a08g045_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A09G011 { .compatible = "renesas,r9a09g011-cpg", diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 8312972cc496..7112320f26e2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -282,6 +282,7 @@ struct rzg2l_cpg_info { extern const struct rzg2l_cpg_info r9a07g043_cpg_info; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; +extern const struct rzg2l_cpg_info r9a08g045_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; int rzg2l_cpg_sd_mux_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); From patchwork Fri Sep 29 05:39:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841089 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=MFRzzpO7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 14/28] pinctrl: renesas: rzg2l: index all registers based on port offset Date: Fri, 29 Sep 2023 08:39:01 +0300 Message-Id: <20230929053915.1530607-15-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea To get address that needs to be read/write for specific port functionalities the P(), PM(), PMC(), PFC(), PIN(), IOLH() IEN(), ISEL() macros are used. Some of these macros received as argument the hardware port identifier, some hardware port offset address (e.g. ISEL() received port identifier, IOLH() received port offset address). This makes hard to extend the current driver for SoCs were port identifiers are not continuous in memory map of pin controller. This is the case for RZ/G3S pin controller were ports are mapped as follows: port offset port identifier ----------- --------------- 0x20 P0 0x21 P5 0x22 P6 0x23 P11 0x24 P12 0x25 P13 0x26 P14 0x27 P15 0x28 P16 0x29 P17 0x2a P18 0x30 P1 0x31 P2 0x32 P3 0x33 P4 0x34 P7 0x35 P8 0x36 P8 0x37 P10 To make this achievable change all the above macros used to get the address of a port register for specific port functionality based on port hardware address. Shortly, all the above macros will get as argument the port offset address listed in the above table. With this RZG2L_SINGLE_PIN_GET_PORT_OFFSET(), RZG2L_PIN_ID_TO_PORT_OFFSET() and RZG2L_GPIO_PORT_GET_INDEX() were replaced by RZG2L_PIN_CFG_TO_PORT_OFFSET(), RZG2L_SINGLE_PIN_GET_CFGS() and RZG2L_GPIO_PORT_GET_CFGS() were replaced by RZG2L_PIN_CFG_TO_CAPS(). Also rzg2l_pinctrl_set_pfc_mode() don't need port argument anymore. Also rzg2l_gpio_direction_input() and rzg2l_gpio_direction_output() don't need to translate port and bit locally as this can be done by rzg2l_gpio_set_direction(). To use the same naming for port, bit/pin and register offset the port_offset variable names in different places was replaced by variable named off and there is no need to initialize anymore cfg and bit in different code places. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar --- Changes in v2: - mentioned in commit description about the replacement of RZG2L_GPIO_PORT_GET_INDEX() with RZG2L_PIN_CFG_TO_PORT_OFFSET() - moved variable declaration inside for() - got rid of local variable and used directly RZG2L_PIN_ID_TO_PORT() in debug message from rzg2l_pinctrl_set_mux() function - collected tags drivers/pinctrl/renesas/pinctrl-rzg2l.c | 183 ++++++++++++------------ 1 file changed, 95 insertions(+), 88 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 03b36c6b2b6d..96fd829131bd 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -74,8 +74,6 @@ */ #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) -#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) -#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) /* * BIT(31) indicates dedicated pin, p is the register index while @@ -85,18 +83,21 @@ #define RZG2L_SINGLE_PIN BIT(31) #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ ((p) << 24) | ((b) << 20) | (f)) -#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) -#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) - -#define P(n) (0x0000 + 0x10 + (n)) -#define PM(n) (0x0100 + 0x20 + (n) * 2) -#define PMC(n) (0x0200 + 0x10 + (n)) -#define PFC(n) (0x0400 + 0x40 + (n) * 4) -#define PIN(n) (0x0800 + 0x10 + (n)) -#define IOLH(n) (0x1000 + (n) * 8) -#define IEN(n) (0x1800 + (n) * 8) -#define ISEL(n) (0x2c80 + (n) * 8) + +#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & GENMASK(19, 0)) +#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ + (((cfg) & GENMASK(30, 24)) >> 24) : \ + (((cfg) & GENMASK(26, 20)) >> 20)) + +#define P(off) (0x0000 + (off)) +#define PM(off) (0x0100 + (off) * 2) +#define PMC(off) (0x0200 + (off)) +#define PFC(off) (0x0400 + (off) * 4) +#define PIN(off) (0x0800 + (off)) +#define IOLH(off) (0x1000 + (off) * 8) +#define IEN(off) (0x1800 + (off) * 8) +#define ISEL(off) (0x2C00 + (off) * 8) #define PWPR (0x3014) #define SD_CH(n) (0x3000 + (n) * 4) #define QSPI (0x3008) @@ -117,7 +118,6 @@ #define PM_OUTPUT 0x2 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) -#define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) #define RZG2L_TINT_MAX_INTERRUPT 32 @@ -161,7 +161,7 @@ static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, - u8 port, u8 pin, u8 func) + u8 pin, u8 off, u8 func) { unsigned long flags; u32 reg; @@ -169,30 +169,30 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, spin_lock_irqsave(&pctrl->lock, flags); /* Set pin to 'Non-use (Hi-Z input protection)' */ - reg = readw(pctrl->base + PM(port)); + reg = readw(pctrl->base + PM(off)); reg &= ~(PM_MASK << (pin * 2)); - writew(reg, pctrl->base + PM(port)); + writew(reg, pctrl->base + PM(off)); /* Temporarily switch to GPIO mode with PMC register */ - reg = readb(pctrl->base + PMC(port)); - writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); + reg = readb(pctrl->base + PMC(off)); + writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); /* Set the PWPR register to allow PFC register to write */ writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ /* Select Pin function mode with PFC register */ - reg = readl(pctrl->base + PFC(port)); + reg = readl(pctrl->base + PFC(off)); reg &= ~(PFC_MASK << (pin * 4)); - writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); + writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); /* Set the PWPR register to be write-protected */ writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ /* Switch to Peripheral pin function with PMC register */ - reg = readb(pctrl->base + PMC(port)); - writeb(reg | BIT(pin), pctrl->base + PMC(port)); + reg = readb(pctrl->base + PMC(off)); + writeb(reg | BIT(pin), pctrl->base + PMC(off)); spin_unlock_irqrestore(&pctrl->lock, flags); }; @@ -202,9 +202,11 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int group_selector) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct pinctrl_pin_desc *pin_desc; + unsigned int *psel_val, *pin_data; struct function_desc *func; - unsigned int i, *psel_val; struct group_desc *group; + u32 pin, off; int *pins; func = pinmux_generic_get_function(pctldev, func_selector); @@ -217,12 +219,17 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, psel_val = func->data; pins = group->pins; - for (i = 0; i < group->num_pins; i++) { - dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), - psel_val[i]); - rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), - RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); + for (unsigned int i = 0; i < group->num_pins; i++) { + pin_desc = &pctrl->desc.pins[pins[i]]; + pin_data = pin_desc->drv_data; + + pin = RZG2L_PIN_ID_TO_PIN(pins[i]); + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + + dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", + RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i]); + + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]); } return 0; @@ -468,14 +475,14 @@ static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, u32 cfg, u32 port, u8 bit) { u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); - u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); u32 data; if (bit >= pincount || port >= pctrl->data->n_port_pins) return -EINVAL; data = pctrl->data->port_pin_configs[port]; - if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) + if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) return -EINVAL; return 0; @@ -525,20 +532,17 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int arg = 0; unsigned long flags; void __iomem *addr; - u32 port_offset; - u32 cfg = 0; - u8 bit = 0; + u32 off, cfg; + u8 bit; if (!pin_data) return -EINVAL; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); - cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } else { - cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); - port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); bit = RZG2L_PIN_ID_TO_PIN(_pin); if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) @@ -549,7 +553,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_ENABLE: if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); + arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); if (!arg) return -EINVAL; break; @@ -579,7 +583,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_A)) return -EINVAL; - index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); + index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg = iolh_groupa_mA[index]; break; } @@ -590,7 +594,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_B)) return -EINVAL; - index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); + index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg = iolh_groupb_oi[index]; break; } @@ -615,21 +619,18 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, enum pin_config_param param; unsigned long flags; void __iomem *addr; - u32 port_offset; unsigned int i; - u32 cfg = 0; - u8 bit = 0; + u32 cfg, off; + u8 bit; if (!pin_data) return -EINVAL; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); - cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } else { - cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); - port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); bit = RZG2L_PIN_ID_TO_PIN(_pin); if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) @@ -646,7 +647,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); + rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); break; } @@ -687,7 +688,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (index >= ARRAY_SIZE(iolh_groupa_mA)) return -EINVAL; - rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; } @@ -705,7 +706,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (index >= ARRAY_SIZE(iolh_groupb_oi)) return -EINVAL; - rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; } @@ -795,7 +796,9 @@ static const struct pinconf_ops rzg2l_pinctrl_confops = { static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; u8 reg8; @@ -808,28 +811,32 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) spin_lock_irqsave(&pctrl->lock, flags); /* Select GPIO mode in PMC Register */ - reg8 = readb(pctrl->base + PMC(port)); + reg8 = readb(pctrl->base + PMC(off)); reg8 &= ~BIT(bit); - writeb(reg8, pctrl->base + PMC(port)); + writeb(reg8, pctrl->base + PMC(off)); spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } -static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, - u8 bit, bool output) +static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, + bool output) { + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; u16 reg16; spin_lock_irqsave(&pctrl->lock, flags); - reg16 = readw(pctrl->base + PM(port)); + reg16 = readw(pctrl->base + PM(off)); reg16 &= ~(PM_MASK << (bit * 2)); reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); - writew(reg16, pctrl->base + PM(port)); + writew(reg16, pctrl->base + PM(off)); spin_unlock_irqrestore(&pctrl->lock, flags); } @@ -837,13 +844,15 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); - if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { + if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { u16 reg16; - reg16 = readw(pctrl->base + PM(port)); + reg16 = readw(pctrl->base + PM(off)); reg16 = (reg16 >> (bit * 2)) & PM_MASK; if (reg16 == PM_OUTPUT) return GPIO_LINE_DIRECTION_OUT; @@ -856,10 +865,8 @@ static int rzg2l_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); - u8 bit = RZG2L_PIN_ID_TO_PIN(offset); - rzg2l_gpio_set_direction(pctrl, port, bit, false); + rzg2l_gpio_set_direction(pctrl, offset, false); return 0; } @@ -868,19 +875,21 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; u8 reg8; spin_lock_irqsave(&pctrl->lock, flags); - reg8 = readb(pctrl->base + P(port)); + reg8 = readb(pctrl->base + P(off)); if (value) - writeb(reg8 | BIT(bit), pctrl->base + P(port)); + writeb(reg8 | BIT(bit), pctrl->base + P(off)); else - writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); + writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); spin_unlock_irqrestore(&pctrl->lock, flags); } @@ -889,11 +898,9 @@ static int rzg2l_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); - u8 bit = RZG2L_PIN_ID_TO_PIN(offset); rzg2l_gpio_set(chip, offset, value); - rzg2l_gpio_set_direction(pctrl, port, bit, true); + rzg2l_gpio_set_direction(pctrl, offset, true); return 0; } @@ -901,17 +908,19 @@ static int rzg2l_gpio_direction_output(struct gpio_chip *chip, static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); u16 reg16; - reg16 = readw(pctrl->base + PM(port)); + reg16 = readw(pctrl->base + PM(off)); reg16 = (reg16 >> (bit * 2)) & PM_MASK; if (reg16 == PM_INPUT) - return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); + return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); else if (reg16 == PM_OUTPUT) - return !!(readb(pctrl->base + P(port)) & BIT(bit)); + return !!(readb(pctrl->base + P(off)) & BIT(bit)); else return -EINVAL; } @@ -1170,17 +1179,16 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; void __iomem *addr; - u32 port; - u8 bit; irq_chip_disable_parent(d); - port = RZG2L_PIN_ID_TO_PORT(hwirq); - bit = RZG2L_PIN_ID_TO_PIN(hwirq); - - addr = pctrl->base + ISEL(port); + addr = pctrl->base + ISEL(off); if (bit >= 4) { bit -= 4; addr += 4; @@ -1198,17 +1206,16 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; void __iomem *addr; - u32 port; - u8 bit; gpiochip_enable_irq(gc, hwirq); - port = RZG2L_PIN_ID_TO_PORT(hwirq); - bit = RZG2L_PIN_ID_TO_PIN(hwirq); - - addr = pctrl->base + ISEL(port); + addr = pctrl->base + ISEL(off); if (bit >= 4) { bit -= 4; addr += 4; From patchwork Fri Sep 29 05:39:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 15/28] pinctrl: renesas: rzg2l: adapt for different SD/PWPR register offsets Date: Fri, 29 Sep 2023 08:39:02 +0300 Message-Id: <20230929053915.1530607-16-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S. Commit adds a per SoC configuration data structure that is initialized with proper register offset for individual SoCs. The struct rzg2l_hwcfg will be further extended in next commits. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected tags drivers/pinctrl/renesas/pinctrl-rzg2l.c | 52 ++++++++++++++++++++----- 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 96fd829131bd..7256d99fd552 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -98,8 +98,7 @@ #define IOLH(off) (0x1000 + (off) * 8) #define IEN(off) (0x1800 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) -#define PWPR (0x3014) -#define SD_CH(n) (0x3000 + (n) * 4) +#define SD_CH(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -124,6 +123,24 @@ #define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) +/** + * struct rzg2l_register_offsets - specific register offsets + * @pwpr: PWPR register offset + * @sd_ch: SD_CH register offset + */ +struct rzg2l_register_offsets { + u16 pwpr; + u16 sd_ch; +}; + +/** + * struct rzg2l_hwcfg - hardware configuration data structure + * @regs: hardware specific register offsets + */ +struct rzg2l_hwcfg { + const struct rzg2l_register_offsets regs; +}; + struct rzg2l_dedicated_configs { const char *name; u32 config; @@ -136,6 +153,7 @@ struct rzg2l_pinctrl_data { const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; + const struct rzg2l_hwcfg *hwcfg; }; struct rzg2l_pinctrl { @@ -163,6 +181,7 @@ static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; unsigned long flags; u32 reg; @@ -178,8 +197,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); /* Set the PWPR register to allow PFC register to write */ - writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ - writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ /* Select Pin function mode with PFC register */ reg = readl(pctrl->base + PFC(off)); @@ -187,8 +206,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); /* Set the PWPR register to be write-protected */ - writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ - writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ + writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ /* Switch to Peripheral pin function with PMC register */ reg = readb(pctrl->base + PMC(off)); @@ -527,6 +546,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; unsigned int arg = 0; @@ -562,9 +583,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, u32 pwr_reg = 0x0; if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(0); + pwr_reg = SD_CH(regs->sd_ch, 0); else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(1); + pwr_reg = SD_CH(regs->sd_ch, 1); else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg = QSPI; else @@ -616,6 +637,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; enum pin_config_param param; unsigned long flags; void __iomem *addr; @@ -659,9 +682,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, return -EINVAL; if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(0); + pwr_reg = SD_CH(regs->sd_ch, 0); else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(1); + pwr_reg = SD_CH(regs->sd_ch, 1); else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg = QSPI; else @@ -1531,6 +1554,13 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) return 0; } +static const struct rzg2l_hwcfg rzg2l_hwcfg = { + .regs = { + .pwpr = 0x3014, + .sd_ch = 0x3000, + }, +}; + static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, @@ -1538,6 +1568,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), + .hwcfg = &rzg2l_hwcfg, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -1548,6 +1579,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), + .hwcfg = &rzg2l_hwcfg, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = { From patchwork Fri Sep 29 05:39:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841091 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=pCGX6Pvf; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 16/28] pinctrl: renesas: rzg2l: adapt function number for RZ/G3S Date: Fri, 29 Sep 2023 08:39:03 +0300 Message-Id: <20230929053915.1530607-17-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea On RZ/G3S PFC register allow setting 8 functions for individual ports (function1 to function8). For function1 register need to be configured with 0, for function8 register need to be configured with 7. We cannot use zero based addressing when requesting functions from different code places as documentation (RZG3S_pinfunction_List_r1.0.xlsx) states explicitly that function0 is GPIO. For this add a new member to struct rzg2l_hwcfg that will keep the offset that need to be substracted before applying a value to PFC register. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - in commit description mentioned that function0 is GPIO - collected tags drivers/pinctrl/renesas/pinctrl-rzg2l.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 7256d99fd552..73d8a84af04a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -136,9 +136,11 @@ struct rzg2l_register_offsets { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + u8 func_base; }; struct rzg2l_dedicated_configs { @@ -221,6 +223,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int group_selector) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin_desc; unsigned int *psel_val, *pin_data; struct function_desc *func; @@ -246,9 +249,9 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i]); + RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]); + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); } return 0; From patchwork Fri Sep 29 05:39:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841093 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=qWDj0CNd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfPC1WqFz1ypT for ; Fri, 29 Sep 2023 15:42:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232870AbjI2FmG (ORCPT ); Fri, 29 Sep 2023 01:42:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232784AbjI2Fl3 (ORCPT ); Fri, 29 Sep 2023 01:41:29 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB3001BF2 for ; Thu, 28 Sep 2023 22:39:55 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-99de884ad25so1823110466b.3 for ; Thu, 28 Sep 2023 22:39:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965994; x=1696570794; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wCdeJPGU8dd/6qVQQoCrQDlRgEb+6zveKJgbVuoeTT8=; b=qWDj0CNdUuVobCzg1x216C9G+35D1Hag3kCMV4Jn9KtPQAvKd7FBauhjbTsVJyeWh3 pky6o0pcym/oY1XFx7cCJNEZYSPQ/tFtqt6DSp+XExSLPksX56xoz7o3hKQU/jIAq/Vy wjqt8i2AgLeJ9PoYBVIobVdirUCCDffSaTFG6WpclcH3cCtqNA+imxV1s78cRFuo8LKI Oqn+3OIQkkdpmT5l+DI7HEp9wUgnfS3a3zH6jTEJVCY9mhHBTtOYYn34YoQS1F++Co7f anhwWY6+N1OCK2zTB5eu/+ccOO9icZJ+rkAL9ZiqnccXKPtDLGQpTXIr2U5fn9idsRZt dWsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965994; x=1696570794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wCdeJPGU8dd/6qVQQoCrQDlRgEb+6zveKJgbVuoeTT8=; b=FZiQVzGqlNSWoUbUXBqqKZBimg4CAy+4yeviwiefz/19al7aRO/nPGPFMGiyhGqfD+ zxPSISi0IbwWgg4ar3uPCvn9+NlVQvOVEAWgkzrqrcZ+zbIlkzSx0Q1UR9SuXjp+/FKq ZHHOl6NEqmgTVMMRQGXACayd88dylq6ZcDPpDB6EEXbaYO9NxAQGIVr6uDQny8DKJhK/ umIYrDCxxhls2/s4RL35GKOv4pd2QlE/n3uuSQRizFQav6MqBTmcU2KDcpSZdyhUCXBn bXvH+VpnqIb8uCMu0Gj/OvCVxP/NHBWFfYs0ztfJjpytWsXh8cGk8Wwy7+Gao8x5wc0y amnw== X-Gm-Message-State: AOJu0YzUVUjYSXkspQJpz5u8T7vT8i5kvPvqPhz4a8fVC6ew7XZYLFEu x0HuwBQ+O9j+Hzol/0+F6Sivjg== X-Google-Smtp-Source: AGHT+IE8LyqXyBhXf7YsTLE5wkHLmEQar6G84DOrxW13gzxDyxH9XYdGUfrDleuLvNQy+MtuRQr7og== X-Received: by 2002:a17:906:3089:b0:9ae:46f3:b03f with SMTP id 9-20020a170906308900b009ae46f3b03fmr2835364ejv.0.1695965993884; Thu, 28 Sep 2023 22:39:53 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 17/28] pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration Date: Fri, 29 Sep 2023 08:39:04 +0300 Message-Id: <20230929053915.1530607-18-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Move drive strength and output impedance values to SoC specific configuration data structure (struct rzg2l_hwcfg). This allows extending the drive strength support for RZ/G3S. Along with this the DS values were converted to uA for simple integration with RZ/G3S support. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - s/indexes/indices in code documentation - s/micro amps/uA in code documentation - added RZG2L_IOLH_MAX_DS_ENTRIES for "+ 4" statements in code - changed struct rzg2l_hwcfg::iolh_groupb_oi[] size to 4 to avoid oversize it in next commits when RZG2L_IOLH_IDX_MAX will be increased and thus avoiding issues when executing "if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))" in rzg2l_pinctrl_pinconf_set() - collected tags drivers/pinctrl/renesas/pinctrl-rzg2l.c | 42 ++++++++++++++++++------- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 73d8a84af04a..2afc9a34ffa3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -133,13 +133,30 @@ struct rzg2l_register_offsets { u16 sd_ch; }; +/** + * enum rzg2l_iolh_index - starting indices in IOLH specific arrays + * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source + * @RZG2L_IOLH_IDX_MAX: maximum index + */ +enum rzg2l_iolh_index { + RZG2L_IOLH_IDX_3V3 = 0, + RZG2L_IOLH_IDX_MAX = 4, +}; + +/* Maximum number of driver strength entries per power source. */ +#define RZG2L_IOLH_MAX_DS_ENTRIES (4) + /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @iolh_groupa_ua: IOLH group A uA specific values + * @iolh_groupb_oi: IOLH group B output impedance specific values * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; + u16 iolh_groupb_oi[4]; u8 func_base; }; @@ -177,9 +194,6 @@ struct rzg2l_pinctrl { struct mutex mutex; /* serialize adding groups and functions */ }; -static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; -static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; - static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -608,7 +622,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); - arg = iolh_groupa_mA[index]; + arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; break; } @@ -619,7 +633,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); - arg = iolh_groupb_oi[index]; + arg = hwcfg->iolh_groupb_oi[index]; break; } @@ -707,11 +721,12 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_A)) return -EINVAL; - for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { - if (arg == iolh_groupa_mA[index]) + for (index = RZG2L_IOLH_IDX_3V3; + index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { + if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) break; } - if (index >= ARRAY_SIZE(iolh_groupa_mA)) + if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) return -EINVAL; rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); @@ -725,11 +740,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_B)) return -EINVAL; - for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { - if (arg == iolh_groupb_oi[index]) + for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { + if (arg == hwcfg->iolh_groupb_oi[index]) break; } - if (index >= ARRAY_SIZE(iolh_groupb_oi)) + if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) return -EINVAL; rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); @@ -1562,6 +1577,11 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .pwpr = 0x3014, .sd_ch = 0x3000, }, + .iolh_groupa_ua = { + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, + }, + .iolh_groupb_oi = { 100, 66, 50, 33, }, }; static struct rzg2l_pinctrl_data r9a07g043_data = { From patchwork Fri Sep 29 05:39:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 18/28] pinctrl: renesas: rzg2l: add support for different ds values on different groups Date: Fri, 29 Sep 2023 08:39:05 +0300 Message-Id: <20230929053915.1530607-19-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea RZ/G3S supports different drive strength values for different power sources and pin groups (A, B, C). On each group there could be up to 4 drive strength values per power source. Available power sources are 1v8, 2v5, 3v3. Drive strength values are fine tuned than what was previously available on the driver thus the necessity of having micro-amp support. As drive strength and power source values are linked together the hardware setup for these was moved at the end of rzg2l_pinctrl_pinconf_set() to ensure proper validation of the new values. The drive strength values are expected to be initialized though SoC specific hardware configuration data structure. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - s/strenght/strength, s/togheter/together in commit description - got rid of RZG2L_INVALID_IOLH_VAL macro and consider zero as invalid value for entries in struct rzg2l_hwcfg::iolh_group[abc]_ua[] arrays - removed spinlock in rzg2l_[sg]et_power_source() - introduced caps_to_pwr_reg() and simplified the code in rzg2l_[sg]et_power_source() - changed return type of rzg2l_iolh_ua_to_val() to int and return -EINVAL on failure cases - s/rzg2l_ds_supported/rzg2l_ds_is_supported - inverted the logic in rzg2l_pinctrl_pinconf_set() when applying drive strength and power source to hardware registers and thus simplified the code - used devm_kcalloc() instead of devm_kzalloc() - adderessed the rest of the review comments drivers/pinctrl/renesas/pinctrl-rzg2l.c | 323 ++++++++++++++++++++---- 1 file changed, 272 insertions(+), 51 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 2afc9a34ffa3..8b74838510ad 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -55,6 +55,8 @@ #define PIN_CFG_FILONOFF BIT(10) #define PIN_CFG_FILNUM BIT(11) #define PIN_CFG_FILCLKSEL BIT(12) +#define PIN_CFG_IOLH_C BIT(13) +#define PIN_CFG_SOFT_PS BIT(14) #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ @@ -135,12 +137,16 @@ struct rzg2l_register_offsets { /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays + * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source + * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source * @RZG2L_IOLH_IDX_MAX: maximum index */ enum rzg2l_iolh_index { - RZG2L_IOLH_IDX_3V3 = 0, - RZG2L_IOLH_IDX_MAX = 4, + RZG2L_IOLH_IDX_1V8 = 0, + RZG2L_IOLH_IDX_2V5 = 4, + RZG2L_IOLH_IDX_3V3 = 8, + RZG2L_IOLH_IDX_MAX = 12, }; /* Maximum number of driver strength entries per power source. */ @@ -150,13 +156,19 @@ enum rzg2l_iolh_index { * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets * @iolh_groupa_ua: IOLH group A uA specific values + * @iolh_groupb_ua: IOLH group B uA specific values + * @iolh_groupc_ua: IOLH group C uA specific values * @iolh_groupb_oi: IOLH group B output impedance specific values + * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; + u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; + u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_oi[4]; + bool drive_strength_ua; u8 func_base; }; @@ -175,6 +187,16 @@ struct rzg2l_pinctrl_data { const struct rzg2l_hwcfg *hwcfg; }; +/** + * struct rzg2l_pinctrl_pin_settings - pin data + * @power_source: power source + * @drive_strength_ua: drive strength (in micro amps) + */ +struct rzg2l_pinctrl_pin_settings { + u16 power_source; + u16 drive_strength_ua; +}; + struct rzg2l_pinctrl { struct pinctrl_dev *pctl; struct pinctrl_desc desc; @@ -192,8 +214,12 @@ struct rzg2l_pinctrl { spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ + + struct rzg2l_pinctrl_pin_settings *settings; }; +static const u16 available_ps[] = { 1800, 2500, 3300 }; + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -557,6 +583,156 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, spin_unlock_irqrestore(&pctrl->lock, flags); } +static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) +{ + if (caps & PIN_CFG_IO_VMC_SD0) + return SD_CH(regs->sd_ch, 0); + if (caps & PIN_CFG_IO_VMC_SD1) + return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_QSPI) + return QSPI; + + return -EINVAL; +} + +static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) +{ + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + int pwr_reg; + + if (caps & PIN_CFG_SOFT_PS) + return pctrl->settings[pin].power_source; + + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + if (pwr_reg == -EINVAL) + return -EINVAL; + + return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300; +} + +static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) +{ + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + int pwr_reg; + + if (caps & PIN_CFG_SOFT_PS) { + pctrl->settings[pin].power_source = ps; + return 0; + } + + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + if (pwr_reg == -EINVAL) + return -EINVAL; + + writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg); + pctrl->settings[pin].power_source = ps; + + return 0; +} + +static bool rzg2l_ps_is_supported(u16 ps) +{ + u8 i; + + for (i = 0; i < ARRAY_SIZE(available_ps); i++) { + if (available_ps[i] == ps) + return true; + } + + return false; +} + +static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(available_ps); i++) { + if (available_ps[i] == ps) + break; + } + + /* + * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have + * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source + */ + return i * RZG2L_IOLH_MAX_DS_ENTRIES; +} + +static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) +{ + if (caps & PIN_CFG_IOLH_A) + return hwcfg->iolh_groupa_ua[val]; + + if (caps & PIN_CFG_IOLH_B) + return hwcfg->iolh_groupb_ua[val]; + + if (caps & PIN_CFG_IOLH_C) + return hwcfg->iolh_groupc_ua[val]; + + /* Should not happen. */ + return 0; +} + +static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, + enum rzg2l_iolh_index ps_index, u16 ua) +{ + const u16 *array = NULL; + u16 i; + + if (caps & PIN_CFG_IOLH_A) + array = &hwcfg->iolh_groupa_ua[ps_index]; + + if (caps & PIN_CFG_IOLH_B) + array = &hwcfg->iolh_groupb_ua[ps_index]; + + if (caps & PIN_CFG_IOLH_C) + array = &hwcfg->iolh_groupc_ua[ps_index]; + + if (!array) + return -EINVAL; + + for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { + if (array[i] == ua) + return i; + } + + return -EINVAL; +} + +static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, + enum rzg2l_iolh_index iolh_idx, + u16 ds) +{ + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const u16 *array = NULL; + u16 i; + + if (caps & PIN_CFG_IOLH_A) + array = hwcfg->iolh_groupa_ua; + + if (caps & PIN_CFG_IOLH_B) + array = hwcfg->iolh_groupb_ua; + + if (caps & PIN_CFG_IOLH_C) + array = hwcfg->iolh_groupc_ua; + + /* Should not happen. */ + if (!array) + return false; + + if (!array[iolh_idx]) + return false; + + for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { + if (array[iolh_idx + i] == ds) + return true; + } + + return false; +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -564,13 +740,11 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; - const struct rzg2l_register_offsets *regs = &hwcfg->regs; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; unsigned int arg = 0; - unsigned long flags; - void __iomem *addr; u32 off, cfg; + int ret; u8 bit; if (!pin_data) @@ -596,40 +770,49 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; break; - case PIN_CONFIG_POWER_SOURCE: { - u32 pwr_reg = 0x0; - - if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(regs->sd_ch, 0); - else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(regs->sd_ch, 1); - else if (cfg & PIN_CFG_IO_VMC_QSPI) - pwr_reg = QSPI; - else - return -EINVAL; - - spin_lock_irqsave(&pctrl->lock, flags); - addr = pctrl->base + pwr_reg; - arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; - spin_unlock_irqrestore(&pctrl->lock, flags); + case PIN_CONFIG_POWER_SOURCE: + ret = rzg2l_get_power_source(pctrl, _pin, cfg); + if (ret < 0) + return ret; + arg = ret; break; - } case PIN_CONFIG_DRIVE_STRENGTH: { unsigned int index; - if (!(cfg & PIN_CFG_IOLH_A)) + if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); + /* + * Drive strenght mA is supported only by group A and only + * for 3V3 port source. + */ arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; break; } + case PIN_CONFIG_DRIVE_STRENGTH_UA: { + enum rzg2l_iolh_index iolh_idx; + u8 val; + + if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || + !hwcfg->drive_strength_ua) + return -EINVAL; + + ret = rzg2l_get_power_source(pctrl, _pin, cfg); + if (ret < 0) + return ret; + iolh_idx = rzg2l_ps_to_iolh_idx(ret); + val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); + arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); + break; + } + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { unsigned int index; - if (!(cfg & PIN_CFG_IOLH_B)) + if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); @@ -653,14 +836,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; - const struct rzg2l_register_offsets *regs = &hwcfg->regs; + struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; + unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - unsigned long flags; - void __iomem *addr; unsigned int i; u32 cfg, off; + int ret; u8 bit; if (!pin_data) @@ -691,34 +873,15 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, break; } - case PIN_CONFIG_POWER_SOURCE: { - unsigned int mV = pinconf_to_config_argument(_configs[i]); - u32 pwr_reg = 0x0; - - if (mV != 1800 && mV != 3300) - return -EINVAL; - - if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(regs->sd_ch, 0); - else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(regs->sd_ch, 1); - else if (cfg & PIN_CFG_IO_VMC_QSPI) - pwr_reg = QSPI; - else - return -EINVAL; - - addr = pctrl->base + pwr_reg; - spin_lock_irqsave(&pctrl->lock, flags); - writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); - spin_unlock_irqrestore(&pctrl->lock, flags); + case PIN_CONFIG_POWER_SOURCE: + settings.power_source = pinconf_to_config_argument(_configs[i]); break; - } case PIN_CONFIG_DRIVE_STRENGTH: { unsigned int arg = pinconf_to_config_argument(_configs[i]); unsigned int index; - if (!(cfg & PIN_CFG_IOLH_A)) + if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; for (index = RZG2L_IOLH_IDX_3V3; @@ -733,11 +896,19 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, break; } + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || + !hwcfg->drive_strength_ua) + return -EINVAL; + + settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); + break; + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { unsigned int arg = pinconf_to_config_argument(_configs[i]); unsigned int index; - if (!(cfg & PIN_CFG_IOLH_B)) + if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { @@ -756,6 +927,39 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, } } + /* Apply power source. */ + if (settings.power_source != pctrl->settings[_pin].power_source) { + ret = rzg2l_ps_is_supported(settings.power_source); + if (!ret) + return -EINVAL; + + /* Apply power source. */ + ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); + if (ret) + return ret; + } + + /* Apply drive strength. */ + if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { + enum rzg2l_iolh_index iolh_idx; + int val; + + iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); + ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, + settings.drive_strength_ua); + if (!ret) + return -EINVAL; + + /* Get register value for this PS/DS tuple. */ + val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); + if (val == -EINVAL) + return -EINVAL; + + /* Apply drive strength. */ + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); + pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; + } + return 0; } @@ -1463,6 +1667,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) { + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct pinctrl_pin_desc *pins; unsigned int i, j; u32 *pin_data; @@ -1505,6 +1710,22 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) pins[index].drv_data = &pin_data[index]; } + pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), + GFP_KERNEL); + if (!pctrl->settings) + return -ENOMEM; + + for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { + if (pin_data[i] & PIN_CFG_SOFT_PS) { + pctrl->settings[i].power_source = 3300; + } else { + ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); + if (ret < 0) + continue; + pctrl->settings[i].power_source = ret; + } + } + ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, &pctrl->pctl); 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 19/28] dt-bindings: pinctrl: renesas: set additionalProperties: false Date: Fri, 29 Sep 2023 08:39:06 +0300 Message-Id: <20230929053915.1530607-20-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Set additionalProperties: false. Suggested-by: Rob Herring Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley --- Changes in v2: - this patch is new in v2 and added as suggested by Rob .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 4782f96feb7e..eb726770f571 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -106,8 +106,7 @@ additionalProperties: line-name: true - type: object - additionalProperties: - $ref: "#/additionalProperties/anyOf/0" + additionalProperties: false allOf: - $ref: pinctrl.yaml# From patchwork Fri Sep 29 05:39:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841095 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=hv11lyyq; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfPG3hcVz1yng for ; Fri, 29 Sep 2023 15:42:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232755AbjI2FmJ (ORCPT ); Fri, 29 Sep 2023 01:42:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232648AbjI2Fl3 (ORCPT ); Fri, 29 Sep 2023 01:41:29 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27C2E1FCA for ; Thu, 28 Sep 2023 22:40:01 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-9adb9fa7200so63893566b.0 for ; Thu, 28 Sep 2023 22:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695965999; x=1696570799; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wor+2ysYovWwz79wDHgf6lw48XDzirr+UHoMWUaKK0I=; b=hv11lyyqdIZllhGvop+tiXsvBx+tCxEzKcTeHASCgpgZ9P2/FvzCwN43vmBXmgW9lU WT5FouJdYvDCClB9VU8nBoiBZb5IbUKYe2aHIZmaGrBOeqt4xX/1SiDuj4zEQF83xA6+ XPqTN8YFTydiGU2wCnBNzQDIkhWp6pm6D5htLXIX+W4tzaxfm6A6BkQe2tPyFeyDhDK2 qV1AcaIYCZlwbLFSMgIxEdEgpIzgUij3uquB0kjLpJ3FrfUB4hIJD5MZ1mvvdZn+6JQX l3IAv6QWf/bAzaRyzleVx0O5xlLqVd8BCDO6ZDyenLshiMqa12ghthwRxc3vqXZ+egsT wPUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695965999; x=1696570799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wor+2ysYovWwz79wDHgf6lw48XDzirr+UHoMWUaKK0I=; b=Rpe4wv1Cmm7g8+GAVZ0LNjfp9RURYUB1uhDqHGgHFg9OdQEqXQvAccEX1bWOLXbo6x p+zZH11p49rQX8A3hufpzE/eo2ri0ZQDPnT6uEEhTneIgq5G+99PS2gFZqdsIm0aqe/S sURAXvxSFeMwVZhgOmUeF2Sw1spkCQJCRnVpQa3ANjlOQlcCcVoDPvYDch72MtBUAlBO U6zFqGSabLJEzO7XS3FCyVA9MRE+C1vQrOKg7QZbIjhL4rl2tZnLeu0UMrhbhRGh66Ld qm+M8fkFqymm1U9KZCu4IfasPpmVdyDVEyUQEtGmk6xtdjOJ/jl8x8Rxe8ASTt9QxbNL fYPw== X-Gm-Message-State: AOJu0YzTu74Z3FQySjTj0F6ENic9FXatQI3mr8txHXh4A8+DDtXZXirR 3h8C2lkwi5WMkSp8laBe+HCaFw== X-Google-Smtp-Source: AGHT+IGuHtC57n+o1bpWpASywaDobhLzZbsZm4sa2GVeKsCcbnMjDU8gtdTIYb+NLm0dPD1iTjOvRQ== X-Received: by 2002:a17:907:948b:b0:9a5:aa43:1c7c with SMTP id dm11-20020a170907948b00b009a5aa431c7cmr3069995ejc.26.1695965999656; Thu, 28 Sep 2023 22:39:59 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 20/28] dt-bindings: pinctrl: renesas: document RZ/G3S SoC Date: Fri, 29 Sep 2023 08:39:07 +0300 Message-Id: <20230929053915.1530607-21-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add documentation for pin controller found on RZ/G3S (R9A08G045) SoC. Compared with RZ/G2{L,UL} RZ/G3S has 82 general-purpose IOs, no slew rate and output impedance support and more values for drive strength which needs to be expressed in microamp. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- Changes in v2: - defined drive-strength-microamp as general and make if/then schema to not allow specific properties depending on compatible .../pinctrl/renesas,rzg2l-pinctrl.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index eb726770f571..86228ba69aab 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -25,6 +25,7 @@ properties: - enum: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + - renesas,r9a08g045-pinctrl # RZ/G3S - items: - enum: @@ -78,6 +79,21 @@ additionalProperties: - $ref: pincfg-node.yaml# - $ref: pinmux-node.yaml# + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a08g045-pinctrl + then: + properties: + drive-strength: false + output-impedance-ohms: false + slew-rate: false + else: + properties: + drive-strength-microamp: false + description: Pin controller client devices use pin configuration subnodes (children and grandchildren) for desired pin configuration. @@ -92,6 +108,10 @@ additionalProperties: pins: true drive-strength: enum: [ 2, 4, 8, 12 ] + drive-strength-microamp: + enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700, + 5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000, + 10000 ] output-impedance-ohms: enum: [ 33, 50, 66, 100 ] power-source: From patchwork Fri Sep 29 05:39:08 2023 Content-Type: text/plain; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:01 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 21/28] pinctrl: renesas: rzg2l: add support for RZ/G3S SoC Date: Fri, 29 Sep 2023 08:39:08 +0300 Message-Id: <20230929053915.1530607-22-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add basic support for RZ/G3S to be able to boot from SD card, have a running console port and use GPIOs. RZ/G3S has 82 general-purpose IO ports. Support for the remaining pin functions (e.g. Ethernet, XSPI) will be added along with controller specific support. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - dropped [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL initializations from v1 as these are not needed anymore with the new code adjustements - added BUILD_BUG_ON() for r9a08g045_gpio_configs[] in rzg2l_pinctrl_probe() drivers/pinctrl/renesas/pinctrl-rzg2l.c | 126 +++++++++++++++++++++++- 1 file changed, 124 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 8b74838510ad..57af2db445e1 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -58,13 +58,19 @@ #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) -#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ - PIN_CFG_SR | \ +#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ + (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ PIN_CFG_FILONOFF | \ PIN_CFG_FILNUM | \ PIN_CFG_FILCLKSEL) +#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ + PIN_CFG_SR) + +#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ + PIN_CFG_SOFT_PS) + #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ PIN_CFG_FILONOFF | \ PIN_CFG_FILNUM | \ @@ -1313,6 +1319,36 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; +static const u32 r9a08g045_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ + RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P1 */ + RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P2 */ + RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P3 */ + RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P4 */ + RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ + RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ + RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P7 */ + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P8 */ + RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P9 */ + RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P10 */ + RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ + RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ + RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ + RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ + RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ + RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ + RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ +}; + static const struct { struct rzg2l_dedicated_configs common[35]; struct rzg2l_dedicated_configs rzg2l_pins[7]; @@ -1399,6 +1435,46 @@ static const struct { } }; +static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | + PIN_CFG_FILCLKSEL)) }, + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | + PIN_CFG_SOFT_PS)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) { unsigned int gpioint; @@ -1760,6 +1836,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -1805,6 +1884,35 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .iolh_groupb_oi = { 100, 66, 50, 33, }, }; +static const struct rzg2l_hwcfg rzg3s_hwcfg = { + .regs = { + .pwpr = 0x3000, + .sd_ch = 0x3004, + }, + .iolh_groupa_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, + }, + .iolh_groupb_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, + }, + .iolh_groupc_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, + /* 2v5 source */ + [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, + }, + .drive_strength_ua = true, + .func_base = 1, +}; + static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, @@ -1826,6 +1934,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, }; +static struct rzg2l_pinctrl_data r9a08g045_data = { + .port_pins = rzg2l_gpio_names, + .port_pin_configs = r9a08g045_gpio_configs, + .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), + .dedicated_pins = rzg3s_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), + .hwcfg = &rzg3s_hwcfg, +}; + static const struct of_device_id rzg2l_pinctrl_of_table[] = { { .compatible = "renesas,r9a07g043-pinctrl", @@ -1835,6 +1953,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .compatible = "renesas,r9a07g044-pinctrl", .data = &r9a07g044_data, }, + { + .compatible = "renesas,r9a08g045-pinctrl", + .data = &r9a08g045_data, + }, { /* sentinel */ } }; From patchwork Fri Sep 29 05:39:09 2023 Content-Type: text/plain; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:03 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 22/28] arm64: dts: renesas: add initial DTSI for RZ/G3S SoC Date: Fri, 29 Sep 2023 08:39:09 +0300 Message-Id: <20230929053915.1530607-23-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add initial DTSI for RZ/G3S SoC. Files in commit has the following meaning: r9a08g045.dtsi RZ/G3S family SoC common parts r9a08g045s33.dtsi RZ/G3S R0A08G045S33 SoC specific parts Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected tags arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 139 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 14 ++ 2 files changed, 153 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi new file mode 100644 index 000000000000..7971e44a5a0a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a08g045"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a08g045-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a08g045-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g045-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_GPIO_RSTN>, + <&cpg R9A08G045_GPIO_PORT_RESETN>, + <&cpg R9A08G045_GPIO_SPARE_RESETN>; + }; + + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + gic: interrupt-controller@12400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x12400000 0 0x40000>, + <0x0 0x12440000 0 0x60000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi new file mode 100644 index 000000000000..3351f26c7a2a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S R9A08G045S33 SoC specific part + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045.dtsi" + +/ { + compatible = "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; From patchwork Fri Sep 29 05:39:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=Eh0BMORP; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfPb5H29z1yng for ; Fri, 29 Sep 2023 15:42:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232893AbjI2Fm0 (ORCPT ); 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:05 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 23/28] dt-bindings: arm: renesas: document RZ/G3S SMARC SoM Date: Fri, 29 Sep 2023 08:39:10 +0300 Message-Id: <20230929053915.1530607-24-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Document Renesas RZ/G3S SMARC SoM board which is based on RZ/G3S (R9A08G045S33) SoC. Suggested-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- Changes in v2: - this patch is new in v2 and added as suggested by Geert Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 822faf081e84..31d0539bb168 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -480,6 +480,12 @@ properties: - renesas,r9a08g045s33 # PCIe support - const: renesas,r9a08g045 + - description: RZ/G3S SMARC Module (SoM) + items: + - const: renesas,rzg3s-smarcm # RZ/G3S SMARC Module (SoM) + - const: renesas,r9a08g045s33 # PCIe support + - const: renesas,r9a08g045 + additionalProperties: true ... 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:07 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 24/28] arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S SMARC SoM Date: Fri, 29 Sep 2023 08:39:11 +0300 Message-Id: <20230929053915.1530607-25-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add initial support for RZ/G3S SMARC SoM. The following devices available on SoM were added to this initial device tree: - RZ/G3S SoC: Renesas R9A08G045S33GBG - Clock Generator (only 24MHz output): Renesas 5L35023B - 1GiB LPDDR4 SDRAM: Micron MT53D512M16D1DS-046 - 64GB eMMC Flash (though SD ch0): Micron MTFC64GBCAQTC SD channel 0 of RZ/G3S is connected to an uSD card interface and an eMMC. The selection b/w them is done though a hardware switch. The DT will select b/w uSD and eMMC though SW_SD0_DEV_SEL build flag. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - s/Carrier-II SoM/SoM in patch title - listed in commit description only devices addressed by this initial dtsi - s/8G LPDDR4/1GiB LPDDR4 in commit description - removed sd0-pwr-en-hog node and use specific GPIO in vcc_sdhi0 regulator - added SoM compatible: compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi new file mode 100644 index 000000000000..185ca8289a35 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include + +/* + * Signals of SW_CONFIG switches: + * @SW_SD0_DEV_SEL: + * 0 - SD0 is connected to eMMC + * 1 - SD0 is connected to uSD0 card + */ +#define SW_SD0_DEV_SEL 1 + +/ { + compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; + + aliases { + mmc0 = &sdhi0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device-type = "memory"; + /* First 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + vcc_sdhi0: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + +#if SW_SD0_DEV_SEL + vccq_sdhi0: regulator1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +#else + reg_1p8v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +#endif +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +#if SW_SD0_DEV_SEL +/* SD0 slot */ +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +}; +#else +/* eMMC */ +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + max-frequency = <125000000>; + status = "okay"; +}; +#endif + +&pinctrl { + sdhi0_pins: sd0 { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_uhs_pins: sd0-uhs { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_emmc_pins: sd0-emmc { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD", "SD0_RST#"; + power-source = <1800>; + }; +}; From patchwork Fri Sep 29 05:39:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841100 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=IKHnYsRN; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.40.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:09 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 25/28] arm64: dts: renesas: rzg3s-smarc: add initial device tree for RZ SMARC Carrier-II Board Date: Fri, 29 Sep 2023 08:39:12 +0300 Message-Id: <20230929053915.1530607-26-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add initial device tree for RZ SMARC Carrier-II. At the moment it contains only serial interface. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - inversed the pin naming arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi new file mode 100644 index 000000000000..e7073a09ed2e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include + +/ { + aliases { + serial0 = &scif0; + }; +}; + +&pinctrl { + scif0_pins: scif0 { + pinmux = , /* RXD */ + ; /* TXD */ + }; +}; + +&scif0 { + pinctrl-names = "default"; + pinctrl-0 = <&scif0_pins>; + status = "okay"; +}; From patchwork Fri Sep 29 05:39:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841101 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=TriGYrBV; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfQR45dCz1ypT for ; Fri, 29 Sep 2023 15:43:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232926AbjI2FnK (ORCPT ); Fri, 29 Sep 2023 01:43:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232866AbjI2FmF (ORCPT ); Fri, 29 Sep 2023 01:42:05 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7CCB1FF6 for ; Thu, 28 Sep 2023 22:40:13 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-99357737980so1796347866b.2 for ; Thu, 28 Sep 2023 22:40:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695966012; x=1696570812; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gxy7hugg4UkryDIMa4s8AtATMA0VYhplDs86iw31hOQ=; b=TriGYrBVLhtzjt/qVuKHXdAC7luqvSOjmTLUQHKBKaYAv5ZX+RzF2/DSL6a/bfyKoa WHIWc4Nue/6Ned/qZxcnv9Vn5LXkvL9lMktBGBGa1f5MFaRKH2SUWZfws4yAxd8uPWb3 kXraV8MCxzBlryIVCVTDjtDcVtT9pXBirW5ZYnq7VVjm/ZA4BGndH0Aozf8kSaviXjee Z93gxC32w07nHE66X5VJELXqUsqi7uKCbUb98pTj1VhLyAhlAQrJEfeBwcPmmDL5NcND 4u2avJKFpb/JmQMmviPyf9OjKQXQbPzD2jpNNdpMdfVnNKllbHAcVzAFrcYQMAkL5UHE G62g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695966012; x=1696570812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gxy7hugg4UkryDIMa4s8AtATMA0VYhplDs86iw31hOQ=; b=uWzSYEQXeQmYOpn+A6sGL3EpZUFK0IvIeEa4ZGs9aQ1ErxzlMRrn9VXu/Ge7awvZx6 HAs782kpysVndtdkN3jMmx6SyizFg51mJwlqdxVnlLmQ+f/75Xpt+BChDYVEouvFoVhq UjYZ3CkzwAUGKX9jRteJLqZWCxgLoKf1dYYaOq2D5R9g166gOTqLfoyo5LymVcSdrLSk A3wY7L0CUGeLrz0wYrqorgpf7YHXajB70bc7pGoQRomrTpzwHLnkg07qT5FeiwHGYZ2m ucYDgYL7R6MUwDangm5plY71Q55gE65OkqN2k0zIgrO9TJpXIFq+QWqxZS7gA5iqVppr lzfA== X-Gm-Message-State: AOJu0Yx0O6zmD9frgDmB38suTAJP/MUw3wCUGGurDeGJMzvnLJ1ADwi4 ezSQOZhb5R9Yoz9UlvlRK3aang== X-Google-Smtp-Source: AGHT+IFjdkJ8pv4paZlOJE5w3vxwyMxycLeU7FNfeuTuZ5x96UbobcwdJecd6pVt0Z9PpK2qhSMmPA== X-Received: by 2002:a17:906:714a:b0:9b2:baa1:5910 with SMTP id z10-20020a170906714a00b009b2baa15910mr3126522ejj.1.1695966012350; Thu, 28 Sep 2023 22:40:12 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 26/28] dt-bindings: arm: renesas: document SMARC Carrier-II EVK Date: Fri, 29 Sep 2023 08:39:13 +0300 Message-Id: <20230929053915.1530607-27-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Document Renesas SMARC Carrier-II EVK board which is based on RZ/G3S SMARC SoM. The SMARC Carrier-II EVK consists of RZ/G3S SoM module and SMARC Carrier-II carrier board, the SoM module sits on top of carrier board. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- Changes in v2: - this patch is new in v2 Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 31d0539bb168..594a7d7a6ee4 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -486,6 +486,13 @@ properties: - const: renesas,r9a08g045s33 # PCIe support - const: renesas,r9a08g045 + - description: RZ SMARC Carrier-II Evaluation Kit + items: + - const: renesas,smarc2-evk # RZ SMARC Carrier-II EVK + - const: renesas,rzg3s-smarcm # RZ/G3S SMARC SoM + - const: renesas,r9a08g045s33 # PCIe support + - const: renesas,r9a08g045 + additionalProperties: true ... From patchwork Fri Sep 29 05:39:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841103 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=N/fYhnvR; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfR66Slcz1yng for ; Fri, 29 Sep 2023 15:43:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232988AbjI2Fnp (ORCPT ); Fri, 29 Sep 2023 01:43:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232793AbjI2Fnd (ORCPT ); Fri, 29 Sep 2023 01:43:33 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4EFA2101 for ; Thu, 28 Sep 2023 22:40:15 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-99c136ee106so1797135866b.1 for ; Thu, 28 Sep 2023 22:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1695966014; x=1696570814; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/cPgz6zkkuP/QvbsAnjGs89IXSWE24BO+d6az/jrPNY=; b=N/fYhnvRLb36lt1eapguKiqxqVYNlsqrv+Ui3l5CPTtLJ7m3pLF6ZOuQnZay2XCm2C QP60ou75tAJXPncyqANmlJBMWwQcRiSHrWsfOMSR5/0/z47BAnxnCGjVmQ4aohQg0yad BAeL2dOfyNn+c3ppwIcDQ0ERlSjRHOyDa+K+ziuTZjb1MY/2AZ15l2abLRJXc0FM1V7x t58L5FiJSUSMU45CQJTwp2+KD+vJIuy24zxFLiclNNmXGibLBhhmEQviuxd5oE4/xUWp v2kw8KWsKJuwmq11vP4u+ACZrQEZjKmwXEXT9adm+pUhbVmDQ5r2cPkBoiJ+0BU+qfAk Eczg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695966014; x=1696570814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/cPgz6zkkuP/QvbsAnjGs89IXSWE24BO+d6az/jrPNY=; b=mHwT1ReO6GRdci01bE6KdvcKKlxRx6+GLwGmHW9FACgujyyB09IXFrum9G/UhzYpXa ZAkvC7791bW3Ihivov5svnHHfb6+4XleTH5G1wyZ2HvQ+0DM5O/NkZmn8UVSZsYElDwY LbtlzT4ad7HwtEAtzI0rX9z8fW84WIy773pNov1wgPwiIQIlz0Exxb6/ddMgCyT8cGds EJYUoJRCz2y9gSoLII3nseUPaeEZFwL9ecrS6Bmhtw5azCQ1jByu7Rh51+nvfdCE/+Na 4AX0ooWLJpS2Eagdf/CNiivq6L4ZIQZgWqsPzQhNTnipGcsZVGDVqAgpwmf1L/C/B4Go 8XfQ== X-Gm-Message-State: AOJu0YzgIluiwIe+FRo6xVvuFKXr1/QYwvmvjR/15H60qqsf0gGANiHC shqqAO/YoNBRawjyCI2AGkjPAQ== X-Google-Smtp-Source: AGHT+IFpSPh8yayTTchhgUGo5UVhQZBeySgfo2JdyqmupZ/CM1UnRoYelTOunDOQMI3TLbCEj6KiTg== X-Received: by 2002:a17:906:10dc:b0:9b2:bb02:a543 with SMTP id v28-20020a17090610dc00b009b2bb02a543mr3227213ejv.74.1695966014250; Thu, 28 Sep 2023 22:40:14 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.40.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:13 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 27/28] arm64: dts: renesas: r9a08g045s33-smarc: add initial device tree for RZ/G3S SMARC EVK board Date: Fri, 29 Sep 2023 08:39:14 +0300 Message-Id: <20230929053915.1530607-28-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Add initial device tree for RZ/G3S SMARC EVK board. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - modified compatible - @Geert: I haven't added you Rb tag as I've added "renesas,rzg3s-smarcm" to the compatible list arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a08g045s33-smarc.dts | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 7114cbbd8713..254983ca56a1 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -86,6 +86,8 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo +dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb + dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts new file mode 100644 index 000000000000..7d775d10a97e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SMARC EVK board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045s33.dtsi" +#include "rzg3s-smarc-som.dtsi" +#include "rzg3s-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a08g045s33"; + compatible = "renesas,smarc2-evk", "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; From patchwork Fri Sep 29 05:39:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 1841102 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256 header.s=google header.b=eofZB1GO; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RxfQz026xz1yng for ; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:40:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 28/28] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC Date: Fri, 29 Sep 2023 08:39:15 +0300 Message-Id: <20230929053915.1530607-29-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Claudiu Beznea Enable config flag for Renesas RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected tags arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 66bfbef73324..07011114eef8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1341,6 +1341,7 @@ CONFIG_ARCH_R8A774B1=y CONFIG_ARCH_R9A07G043=y CONFIG_ARCH_R9A07G044=y CONFIG_ARCH_R9A07G054=y +CONFIG_ARCH_R9A08G045=y CONFIG_ARCH_R9A09G011=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_ROCKCHIP_PM_DOMAINS=y